include/configs/TOP860.h

   1 /*
   2  * (C) Copyright 2003
   3  * EMK Elektronik GmbH <www.emk-elektronik.de>
   4  * Reinhard Meyer <r.meyer@emk-elektronik.de>
   5  *
   6  * Configuation settings for the TOP860 board.
   7  *
   8  * -----------------------------------------------------------------
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27 /*
  28  * TOP860 is a simple module:
  29  * 16-bit wide FLASH on CS0     (2MB or more)
  30  * 32-bit wide DRAM on CS2 (either 4MB or 16MB)
  31  * FEC with Am79C874 100-Base-T and Fiber Optic
  32  * Ports available, but we choose SMC1 for Console
  33  * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
  34  * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
  35  *
  36  * This config has been copied from MBX.h / MBX860T.h
  37  */
  38 /*
  39  * board/config.h - configuration options, board specific
  40  */
  41
  42 #ifndef __CONFIG_H
  43 #define __CONFIG_H
  44
  45 /*
  46  * High Level Configuration Options
  47  * (easy to change)
  48  */
  49
  50 /*-----------------------------------------------------------------------
  51  * CPU and BOARD type
  52  */
  53 #define CONFIG_MPC860   1       /* This is a MPC860 CPU         */
  54 #define CONFIG_MPC860T  1       /* even better... an FEC!       */
  55 #define CONFIG_TOP860   1       /* ...on a TOP860 module        */
  56
  57 #define CONFIG_SYS_TEXT_BASE    0x80000000
  58
  59 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  60 #define CONFIG_IDENT_STRING " EMK TOP860"
  61
  62 /*-----------------------------------------------------------------------
  63  * CLOCK settings
  64  */
  65 #define CONFIG_SYSCLK   49152000
  66 #define CONFIG_SYS_XTAL         32768
  67 #define CONFIG_EBDF             1
  68 #define CONFIG_COM              3
  69 #define CONFIG_RTC_MPC8xx
  70
  71 /*-----------------------------------------------------------------------
  72  * Physical memory map as defined by EMK
  73  */
  74 #define CONFIG_SYS_IMMR         0xFFF00000      /* Internal Memory Mapped Register */
  75 #define CONFIG_SYS_FLASH_BASE   0x80000000      /* FLASH in final mapping */
  76 #define CONFIG_SYS_DRAM_BASE    0x00000000      /* DRAM in final mapping */
  77 #define CONFIG_SYS_FLASH_MAX    0x00400000      /* max FLASH to expect */
  78 #define CONFIG_SYS_DRAM_MAX     0x01000000      /* max DRAM to expect */
  79
  80 /*-----------------------------------------------------------------------
  81  * derived values
  82  */
  83 #define CONFIG_SYS_MF                   (CONFIG_SYSCLK/CONFIG_SYS_XTAL)
  84 #define CONFIG_SYS_CPUCLOCK     CONFIG_SYSCLK
  85 #define CONFIG_SYS_BRGCLOCK     CONFIG_SYSCLK
  86 #define CONFIG_SYS_BUSCLOCK     (CONFIG_SYSCLK >> CONFIG_EBDF)
  87 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
  88 #define CONFIG_8xx_GCLK_FREQ    CONFIG_SYSCLK
  89
  90 /*-----------------------------------------------------------------------
  91  * FLASH organization
  92  */
  93 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
  94 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip    */
  95
  96 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
  97 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
  98
  99 #define CONFIG_SYS_FLASH_CFI
 100
 101 /*-----------------------------------------------------------------------
 102  * Command interpreter
 103  */
 104 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
 105 #undef  CONFIG_8xx_CONS_SMC2
 106 #define CONFIG_BAUDRATE         9600
 107
 108 /*
 109  * Allow partial commands to be matched to uniqueness.
 110  */
 111 #define CONFIG_SYS_MATCH_PARTIAL_CMD
 112
 113
 114 /*
 115  * Command line configuration.
 116  */
 117 #include <config_cmd_default.h>
 118
 119 #define CONFIG_CMD_ASKENV
 120 #define CONFIG_CMD_DHCP
 121 #define CONFIG_CMD_I2C
 122 #define CONFIG_CMD_EEPROM
 123 #define CONFIG_CMD_REGINFO
 124 #define CONFIG_CMD_IMMAP
 125 #define CONFIG_CMD_ELF
 126 #define CONFIG_CMD_DATE
 127 #define CONFIG_CMD_MII
 128 #define CONFIG_CMD_BEDBUG
 129
 130
 131 #define CONFIG_SOURCE                   1
 132 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1
 133 #undef  CONFIG_LOADS_ECHO                       /* NO echo on for serial download       */
 134
 135
 136 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 137 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 138
 139 #undef  CONFIG_SYS_HUSH_PARSER                  /* Hush parse for U-Boot        */
 140
 141 #ifdef  CONFIG_SYS_HUSH_PARSER
 142  #define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 143 #endif
 144
 145 #if defined(CONFIG_CMD_KGDB)
 146  #define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size      */
 147 #else
 148  #define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size      */
 149 #endif
 150
 151 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 152 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 153 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 154
 155 /*-----------------------------------------------------------------------
 156  * Memory Test Command
 157  */
 158 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 159 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 160
 161 /*-----------------------------------------------------------------------
 162  * Environment handler
 163  * only the first 6k in EEPROM are available for user. Of that we use 256b
 164  */
 165 #define CONFIG_SOFT_I2C
 166 #define CONFIG_ENV_IS_IN_EEPROM 1       /* turn on EEPROM env feature */
 167 #define CONFIG_ENV_OFFSET               0x1000
 168 #define CONFIG_ENV_SIZE         0x0700
 169 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
 170 #define CONFIG_SYS_FACT_OFFSET          0x1800
 171 #define CONFIG_SYS_FACT_SIZE            0x0800
 172 #define CONFIG_SYS_I2C_FACT_ADDR        0x57
 173 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 174 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 175 #define CONFIG_SYS_EEPROM_SIZE 0x2000
 176 #define CONFIG_SYS_I2C_SPEED    100000
 177 #define CONFIG_SYS_I2C_SLAVE    0xFE
 178 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
 179 #define CONFIG_ENV_OVERWRITE
 180 #define CONFIG_MISC_INIT_R
 181
 182 #if defined (CONFIG_SOFT_I2C)
 183 #define SDA     0x00010
 184 #define SCL     0x00020
 185 #define __I2C_DIR       immr->im_cpm.cp_pbdir
 186 #define __I2C_DAT       immr->im_cpm.cp_pbdat
 187 #define __I2C_PAR       immr->im_cpm.cp_pbpar
 188 #define __I2C_ODR       immr->im_cpm.cp_pbodr
 189 #define I2C_INIT        { __I2C_PAR &= ~(SDA|SCL);      \
 190                           __I2C_ODR &= ~(SDA|SCL);      \
 191                           __I2C_DAT |= (SDA|SCL);       \
 192                           __I2C_DIR|=(SDA|SCL); }
 193 #define I2C_READ        ((__I2C_DAT & SDA) ? 1 : 0)
 194 #define I2C_SDA(x)      { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
 195 #define I2C_SCL(x)      { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
 196 #define I2C_DELAY       { udelay(5); }
 197 #define I2C_ACTIVE      { __I2C_DIR |= SDA; }
 198 #define I2C_TRISTATE    { __I2C_DIR &= ~SDA; }
 199 #endif
 200
 201 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 202
 203 /*-----------------------------------------------------------------------
 204  * defines we need to get FEC running
 205  */
 206 #define CONFIG_NET_MULTI        1       /* the only way to get the FEC in */
 207 #define CONFIG_FEC_ENET         1       /* Ethernet only via FEC        */
 208 #define FEC_ENET                1       /* eth.c needs it that way... */
 209 #define CONFIG_SYS_DISCOVER_PHY 1
 210 #define CONFIG_MII              1
 211 #define CONFIG_MII_INIT         1
 212 #define CONFIG_PHY_ADDR         31
 213
 214 /*-----------------------------------------------------------------------
 215  * adresses
 216  */
 217 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 218 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 219 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 220
 221 /*-----------------------------------------------------------------------
 222  * Start addresses for the final memory configuration
 223  * (Set up by the startup code)
 224  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 225  */
 226 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 227 #define CONFIG_SYS_FLASH_BASE           0x80000000
 228
 229 /*-----------------------------------------------------------------------
 230  * Definitions for initial stack pointer and data area (in DPRAM)
 231  */
 232 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 233 #define CONFIG_SYS_INIT_RAM_SIZE        0x2f00  /* Size of used area in DPRAM   */
 234 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 235 #define CONFIG_SYS_INIT_VPD_SIZE        256 /* size in bytes reserved for vpd buffer */
 236 #define CONFIG_SYS_INIT_VPD_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
 237 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_VPD_OFFSET-8)
 238
 239 /*-----------------------------------------------------------------------
 240  * Cache Configuration
 241  */
 242 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 243 #if defined(CONFIG_CMD_KGDB)
 244 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 245 #endif
 246
 247 /* Interrupt level assignments.
 248 */
 249 #define FEC_INTERRUPT   SIU_LEVEL1      /* FEC interrupt */
 250
 251 /*-----------------------------------------------------------------------
 252  * Debug Enable Register
 253  *-----------------------------------------------------------------------
 254  *
 255  */
 256 #define CONFIG_SYS_DER 0                                        /* used in start.S */
 257
 258 /*-----------------------------------------------------------------------
 259  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 260  *-----------------------------------------------------------------------
 261  * set up PLPRCR (PLL, Low-Power, and Reset Control Register)
 262  *      12      MF              calculated      Multiplication factor
 263  *      4       0               0000
 264  *      1       SPLSS   0                       System PLL lock status sticky
 265  *      1       TEXPS   1                       Timer expired status
 266  *      1       0               0
 267  *      1       TMIST   0                       Timers interrupt status
 268  *      1       0               0
 269  *      1       CSRC    0                       Clock source (0=DFNH, 1=DFNL)
 270  *      2       LPM             00                      Low-power modes
 271  *      1       CSR             0                       Checkstop reset enable
 272  *      1       LOLRE   0                       Loss-of-lock reset enable
 273  *      1       FIOPD   0                       Force I/O pull down
 274  *      5       0               00000
 275  */
 276 #define CONFIG_SYS_PLPRCR       (PLPRCR_TEXPS | ((CONFIG_SYS_MF-1)<<20))
 277
 278 /*-----------------------------------------------------------------------
 279  * SYPCR - System Protection Control                            11-9
 280  * SYPCR can only be written once after reset!
 281  *-----------------------------------------------------------------------
 282  * set up SYPCR:
 283  *      16      SWTC    0xffff          Software watchdog timer count
 284  *      8       BMT             0xff            Bus monitor timing
 285  *      1       BME             1                       Bus monitor enable
 286  *      3       0               000
 287  *      1       SWF             1                       Software watchdog freeze
 288  *      1       SWE             0/1                     Software watchdog enable
 289  *      1       SWRI    0/1                     Software watchdog reset/interrupt select (1=HRESET)
 290  *      1       SWP             0/1                     Software watchdog prescale (1=/2048)
 291  */
 292 #if defined (CONFIG_WATCHDOG)
 293  #define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 294                                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 295 #else
 296  #define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
 297 #endif
 298
 299 /*-----------------------------------------------------------------------
 300  * SIUMCR - SIU Module Configuration                            11-6
 301  *-----------------------------------------------------------------------
 302  * set up SIUMCR
 303  *      1       EARB    0                       External arbitration
 304  *      3       EARP    000                     External arbitration request priority
 305  *      4       0               0000
 306  *      1       DSHW    0                       Data show cycles
 307  *      2       DBGC    00                      Debug pin configuration
 308  *      2       DBPC    00                      Debug port pins configuration
 309  *      1       0               0
 310  *      1       FRC             0                       FRZ pin configuration
 311  *      1       DLK             0                       Debug register lock
 312  *      1       OPAR    0                       Odd parity
 313  *      1       PNCS    0                       Parity enable for non memory controller regions
 314  *      1       DPC             0                       Data parity pins configuration
 315  *      1       MPRE    0                       Multiprocessor reservation enable
 316  *      2       MLRC    11                      Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
 317  *      1       AEME    0                       Async external master enable
 318  *      1       SEME    0                       Sync external master enable
 319  *      1       BSC             0                       Byte strobe configuration
 320  *      1       GB5E    0                       GPL_B5 enable
 321  *      1       B2DD    0                       Bank 2 double drive
 322  *      1       B3DD    0                       Bank 3 double drive
 323  *      4       0               0000
 324  */
 325 #define CONFIG_SYS_SIUMCR       (SIUMCR_MLRC11)
 326
 327 /*-----------------------------------------------------------------------
 328  * TBSCR - Time Base Status and Control                         11-26
 329  *-----------------------------------------------------------------------
 330  * Clear Reference Interrupt Status, Timebase freezing enabled
 331  */
 332 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 333
 334 /*-----------------------------------------------------------------------
 335  * PISCR - Periodic Interrupt Status and Control                11-31
 336  *-----------------------------------------------------------------------
 337  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 338  */
 339 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF | PISCR_PTE)
 340
 341 /*-----------------------------------------------------------------------
 342  * SCCR - System Clock and reset Control Register               15-27
 343  *-----------------------------------------------------------------------
 344  * set up SCCR (System Clock and Reset Control Register)
 345  *      1       0               0
 346  *      2       COM             11                      Clock output module (00=full, 01=half, 11=off)
 347  *      3       0               000
 348  *      1       TBS             1                       Timebase source (0=OSCCLK, 1=GCLK2)
 349  *      1       RTDIV   0                       Real-time clock divide (0=/4, 1=/512)
 350  *      1       RTSEL   0                       Real-time clock select (0=OSCM, 1=EXTCLK)
 351  *      1       CRQEN   0                       CPM request enable
 352  *      1       PRQEN   0                       Power management request enable
 353  *      2       0               00
 354  *      2       EBDF    xx                      External bus division factor
 355  *      2       0               00
 356  *      2       DFSYNC  00                      Division factor for SYNCLK
 357  *      2       DFBRG   00                      Division factor for BRGCLK
 358  *      3       DFNL    000                     Division factor low frequency
 359  *      3       DFNH    000                     Division factor high frequency
 360  *      5       0               00000
 361  */
 362 #define SCCR_MASK       0
 363 #ifdef CONFIG_EBDF
 364  #define CONFIG_SYS_SCCR        (SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
 365 #else
 366  #define CONFIG_SYS_SCCR        (SCCR_COM11 | SCCR_TBS)
 367 #endif
 368
 369 /*-----------------------------------------------------------------------
 370  * Chip Select 0 - FLASH
 371  *-----------------------------------------------------------------------
 372  * Preliminary Values
 373  */
 374 /* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */
 375 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
 376 #define CONFIG_SYS_OR0_PRELIM   (-CONFIG_SYS_FLASH_MAX | CONFIG_SYS_OR_TIMING_FLASH)
 377 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V )
 378
 379 /*-----------------------------------------------------------------------
 380  * misc
 381  *-----------------------------------------------------------------------
 382  *
 383  */
 384 /*
 385  * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
 386  */
 387 #define CONFIG_BOOTDELAY                                5
 388
 389 /*
 390  * Pass the clock frequency to the Linux kernel in units of MHz
 391  */
 392 #define CONFIG_CLOCKS_IN_MHZ
 393
 394 #define CONFIG_PREBOOT          \
 395         "echo;echo"
 396
 397 #undef  CONFIG_BOOTARGS
 398 #define CONFIG_BOOTCOMMAND      \
 399         "bootp;" \
 400         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
 401         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
 402         "bootm"
 403
 404 /*
 405  * BOOTP options
 406  */
 407 #define CONFIG_BOOTP_SUBNETMASK
 408 #define CONFIG_BOOTP_GATEWAY
 409 #define CONFIG_BOOTP_HOSTNAME
 410 #define CONFIG_BOOTP_BOOTPATH
 411 #define CONFIG_BOOTP_BOOTFILESIZE
 412
 413
 414 /*
 415  * Set default IP stuff just to get bootstrap entries into the
 416  * environment so that we can source the full default environment.
 417  */
 418 #define CONFIG_ETHADDR                                  9a:52:63:15:85:25
 419 #define CONFIG_SERVERIP                                 10.0.4.200
 420 #define CONFIG_IPADDR                                   10.0.4.111
 421
 422 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address */
 423 #define CONFIG_SYS_TFTP_LOADADDR        0x00100000
 424
 425 /*
 426  * For booting Linux, the board info and command line data
 427  * have to be in the first 8 MB of memory, since this is
 428  * the maximum mapped by the Linux kernel during initialization.
 429  */
 430 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 431
 432 #endif  /* __CONFIG_H */