include/configs/TQM823L.h

   1 /*
   2  * (C) Copyright 2000-2008
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC823           1       /* This is a MPC823 CPU         */
  37 #define CONFIG_TQM823L          1       /* ...on a TQM8xxL module       */
  38
  39 #ifdef  CONFIG_LCD                      /* with LCD controller ?        */
  40 #define CONFIG_LCD_LOGO         1       /* print our logo on the LCD    */
  41 #define CONFIG_LCD_INFO         1       /* ... and some board info      */
  42 #define CONFIG_SPLASH_SCREEN            /* ... with splashscreen support*/
  43 #endif
  44
  45 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  46 #undef  CONFIG_8xx_CONS_SMC2
  47 #undef  CONFIG_8xx_CONS_NONE
  48 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  49
  50 #define CONFIG_BOOTCOUNT_LIMIT
  51
  52 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  53
  54 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  55
  56 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  57
  58 #undef  CONFIG_BOOTARGS
  59
  60 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  61         "netdev=eth0\0"                                                 \
  62         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  63                 "nfsroot=${serverip}:${rootpath}\0"                     \
  64         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  65         "addip=setenv bootargs ${bootargs} "                            \
  66                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  67                 ":${hostname}:${netdev}:off panic=1\0"                  \
  68         "flash_nfs=run nfsargs addip;"                                  \
  69                 "bootm ${kernel_addr}\0"                                \
  70         "flash_self=run ramargs addip;"                                 \
  71                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  72         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  73         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  74         "hostname=TQM823L\0"                                            \
  75         "bootfile=TQM823L/uImage\0"                                     \
  76         "fdt_addr=40040000\0"                                           \
  77         "kernel_addr=40060000\0"                                        \
  78         "ramdisk_addr=40200000\0"                                       \
  79         "u-boot=TQM823L/u-image.bin\0"                                  \
  80         "load=tftp 200000 ${u-boot}\0"                                  \
  81         "update=prot off 40000000 +${filesize};"                        \
  82                 "era 40000000 +${filesize};"                            \
  83                 "cp.b 200000 40000000 ${filesize};"                     \
  84                 "sete filesize;save\0"                                  \
  85         ""
  86 #define CONFIG_BOOTCOMMAND      "run flash_self"
  87
  88 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  89 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  90
  91 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  92
  93 #if defined(CONFIG_LCD)
  94 # undef  CONFIG_STATUS_LED              /* disturbs display             */
  95 #else
  96 # define CONFIG_STATUS_LED      1       /* Status LED enabled           */
  97 #endif  /* CONFIG_LCD */
  98
  99 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
 100
 101 /*
 102  * BOOTP options
 103  */
 104 #define CONFIG_BOOTP_SUBNETMASK
 105 #define CONFIG_BOOTP_GATEWAY
 106 #define CONFIG_BOOTP_HOSTNAME
 107 #define CONFIG_BOOTP_BOOTPATH
 108 #define CONFIG_BOOTP_BOOTFILESIZE
 109
 110
 111 #define CONFIG_MAC_PARTITION
 112 #define CONFIG_DOS_PARTITION
 113
 114 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 115
 116
 117 /*
 118  * Command line configuration.
 119  */
 120 #include <config_cmd_default.h>
 121
 122 #define CONFIG_CMD_ASKENV
 123 #define CONFIG_CMD_DATE
 124 #define CONFIG_CMD_DHCP
 125 #define CONFIG_CMD_ELF
 126 #define CONFIG_CMD_IDE
 127 #define CONFIG_CMD_JFFS2
 128 #define CONFIG_CMD_NFS
 129 #define CONFIG_CMD_SNTP
 130
 131 #ifdef  CONFIG_SPLASH_SCREEN
 132     #define CONFIG_CMD_BMP
 133 #endif
 134
 135
 136 #define CONFIG_NETCONSOLE
 137
 138 /*
 139  * Miscellaneous configurable options
 140  */
 141 #define CFG_LONGHELP                    /* undef to save memory         */
 142 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 143
 144 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 145 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 146 #ifdef  CFG_HUSH_PARSER
 147 #define CFG_PROMPT_HUSH_PS2     "> "
 148 #endif
 149
 150 #if defined(CONFIG_CMD_KGDB)
 151 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 152 #else
 153 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 154 #endif
 155 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 156 #define CFG_MAXARGS             16      /* max number of command args   */
 157 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 158
 159 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 160 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 161
 162 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 163
 164 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 165
 166 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 167
 168 /*
 169  * Low Level Configuration Settings
 170  * (address mappings, register initial values, etc.)
 171  * You should know what you are doing if you make changes here.
 172  */
 173 /*-----------------------------------------------------------------------
 174  * Internal Memory Mapped Register
 175  */
 176 #define CFG_IMMR                0xFFF00000
 177
 178 /*-----------------------------------------------------------------------
 179  * Definitions for initial stack pointer and data area (in DPRAM)
 180  */
 181 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 182 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 183 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 184 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 185 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 186
 187 /*-----------------------------------------------------------------------
 188  * Start addresses for the final memory configuration
 189  * (Set up by the startup code)
 190  * Please note that CFG_SDRAM_BASE _must_ start at 0
 191  */
 192 #define CFG_SDRAM_BASE          0x00000000
 193 #define CFG_FLASH_BASE          0x40000000
 194 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 195 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 196 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 197
 198 /*
 199  * For booting Linux, the board info and command line data
 200  * have to be in the first 8 MB of memory, since this is
 201  * the maximum mapped by the Linux kernel during initialization.
 202  */
 203 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 204
 205 /*-----------------------------------------------------------------------
 206  * FLASH organization
 207  */
 208
 209 /* use CFI flash driver */
 210 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 211 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 212 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
 213 #define CFG_FLASH_EMPTY_INFO
 214 #define CFG_FLASH_USE_BUFFER_WRITE      1
 215 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks */
 216 #define CFG_MAX_FLASH_SECT      71      /* max number of sectors on one chip */
 217
 218 #define CONFIG_ENV_IS_IN_FLASH  1
 219 #define CONFIG_ENV_OFFSET               0x8000  /*   Offset   of Environment Sector     */
 220 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 221
 222 /* Address and size of Redundant Environment Sector     */
 223 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 224 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 225
 226 #define CFG_USE_PPCENV                  /* Environment embedded in sect .ppcenv */
 227
 228 /*-----------------------------------------------------------------------
 229  * Dynamic MTD partition support
 230  */
 231 #define CONFIG_JFFS2_CMDLINE
 232 #define MTDIDS_DEFAULT          "nor0=TQM8xxL-0"
 233
 234 #define MTDPARTS_DEFAULT        "mtdparts=TQM8xxL-0:256k(u-boot),"      \
 235                                                 "128k(dtb),"            \
 236                                                 "1664k(kernel),"        \
 237                                                 "2m(rootfs),"           \
 238                                                 "4m(data)"
 239
 240 /*-----------------------------------------------------------------------
 241  * Hardware Information Block
 242  */
 243 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 244 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 245 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 246
 247 /*-----------------------------------------------------------------------
 248  * Cache Configuration
 249  */
 250 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 251 #if defined(CONFIG_CMD_KGDB)
 252 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 253 #endif
 254
 255 /*-----------------------------------------------------------------------
 256  * SYPCR - System Protection Control                            11-9
 257  * SYPCR can only be written once after reset!
 258  *-----------------------------------------------------------------------
 259  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 260  */
 261 #if defined(CONFIG_WATCHDOG)
 262 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 263                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 264 #else
 265 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 266 #endif
 267
 268 /*-----------------------------------------------------------------------
 269  * SIUMCR - SIU Module Configuration                            11-6
 270  *-----------------------------------------------------------------------
 271  * PCMCIA config., multi-function pin tri-state
 272  */
 273 #ifndef CONFIG_CAN_DRIVER
 274 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 275 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 276 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 277 #endif  /* CONFIG_CAN_DRIVER */
 278
 279 /*-----------------------------------------------------------------------
 280  * TBSCR - Time Base Status and Control                         11-26
 281  *-----------------------------------------------------------------------
 282  * Clear Reference Interrupt Status, Timebase freezing enabled
 283  */
 284 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 285
 286 /*-----------------------------------------------------------------------
 287  * RTCSC - Real-Time Clock Status and Control Register          11-27
 288  *-----------------------------------------------------------------------
 289  */
 290 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 291
 292 /*-----------------------------------------------------------------------
 293  * PISCR - Periodic Interrupt Status and Control                11-31
 294  *-----------------------------------------------------------------------
 295  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 296  */
 297 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 298
 299 /*-----------------------------------------------------------------------
 300  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 301  *-----------------------------------------------------------------------
 302  * Reset PLL lock status sticky bit, timer expired status bit and timer
 303  * interrupt status bit
 304  */
 305 #define CFG_PLPRCR      (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 306
 307 /*-----------------------------------------------------------------------
 308  * SCCR - System Clock and reset Control Register               15-27
 309  *-----------------------------------------------------------------------
 310  * Set clock output, timebase and RTC source and divider,
 311  * power management and some other internal clocks
 312  */
 313 #define SCCR_MASK       SCCR_EBDF11
 314 #define CFG_SCCR        (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 315                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 316                          SCCR_DFALCD00)
 317
 318 /*-----------------------------------------------------------------------
 319  * PCMCIA stuff
 320  *-----------------------------------------------------------------------
 321  *
 322  */
 323 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 324 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 325 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 326 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 327 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 328 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 329 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 330 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 331
 332 /*-----------------------------------------------------------------------
 333  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 334  *-----------------------------------------------------------------------
 335  */
 336
 337 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 338
 339 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 340 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 341 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 342
 343 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 344 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 345
 346 #define CFG_ATA_IDE0_OFFSET     0x0000
 347
 348 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 349
 350 /* Offset for data I/O                  */
 351 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 352
 353 /* Offset for normal register accesses  */
 354 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 355
 356 /* Offset for alternate registers       */
 357 #define CFG_ATA_ALT_OFFSET      0x0100
 358
 359 /*-----------------------------------------------------------------------
 360  *
 361  *-----------------------------------------------------------------------
 362  *
 363  */
 364 #define CFG_DER 0
 365
 366 /*
 367  * Init Memory Controller:
 368  *
 369  * BR0/1 and OR0/1 (FLASH)
 370  */
 371
 372 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 373 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 374
 375 /* used to re-map FLASH both when starting from SRAM or FLASH:
 376  * restrict access enough to keep SRAM working (if any)
 377  * but not too much to meddle with FLASH accesses
 378  */
 379 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 380 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 381
 382 /*
 383  * FLASH timing:
 384  */
 385 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 386                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 387
 388 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 389 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 390 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 391
 392 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 393 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 394 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 395
 396 /*
 397  * BR2/3 and OR2/3 (SDRAM)
 398  *
 399  */
 400 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 401 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 402 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 403
 404 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 405 #define CFG_OR_TIMING_SDRAM     0x00000A00
 406
 407 #define CFG_OR2_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 408 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 409
 410 #ifndef CONFIG_CAN_DRIVER
 411 #define CFG_OR3_PRELIM  CFG_OR2_PRELIM
 412 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 413 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 414 #define CFG_CAN_BASE            0xC0000000      /* CAN mapped at 0xC0000000     */
 415 #define CFG_CAN_OR_AM           0xFFFF8000      /* 32 kB address mask           */
 416 #define CFG_OR3_CAN             (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
 417 #define CFG_BR3_CAN             ((CFG_CAN_BASE & BR_BA_MSK) | \
 418                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 419 #endif  /* CONFIG_CAN_DRIVER */
 420
 421 /*
 422  * Memory Periodic Timer Prescaler
 423  *
 424  * The Divider for PTA (refresh timer) configuration is based on an
 425  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 426  * the number of chip selects (NCS) and the actually needed refresh
 427  * rate is done by setting MPTPR.
 428  *
 429  * PTA is calculated from
 430  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 431  *
 432  *      gclk      CPU clock (not bus clock!)
 433  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 434  *
 435  * 4096  Rows from SDRAM example configuration
 436  * 1000  factor s -> ms
 437  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 438  *    4  Number of refresh cycles per period
 439  *   64  Refresh cycle in ms per number of rows
 440  * --------------------------------------------
 441  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 442  *
 443  * 50 MHz => 50.000.000 / Divider =  98
 444  * 66 Mhz => 66.000.000 / Divider = 129
 445  * 80 Mhz => 80.000.000 / Divider = 156
 446  */
 447
 448 #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
 449 #define CFG_MAMR_PTA    98
 450
 451 /*
 452  * For 16 MBit, refresh rates could be 31.3 us
 453  * (= 64 ms / 2K = 125 / quad bursts).
 454  * For a simpler initialization, 15.6 us is used instead.
 455  *
 456  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 457  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 458  */
 459 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 460 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 461
 462 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 463 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 464 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 465
 466 /*
 467  * MAMR settings for SDRAM
 468  */
 469
 470 /* 8 column SDRAM */
 471 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 472                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 473                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 474 /* 9 column SDRAM */
 475 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 476                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 477                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 478
 479
 480 /*
 481  * Internal Definitions
 482  *
 483  * Boot Flags
 484  */
 485 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 486 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 487
 488 #endif  /* __CONFIG_H */