include/configs/TQM8260.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * Imported from global configuration:
  33  *      CONFIG_L2_CACHE
  34  *      CONFIG_266MHz
  35  *      CONFIG_300MHz
  36  *      CONFIG_MPC8255
  37  */
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43
  44 #define CONFIG_MPC8260          1       /* This is a MPC8260 CPU                */
  45
  46 #if 0
  47 #define CONFIG_TQM8260          100     /* ...on a TQM8260 module Rev.100       */
  48 #else
  49 #define CONFIG_TQM8260          200     /* ...on a TQM8260 module Rev.200       */
  50 #endif
  51
  52 /* Define 60x busmode only if your TQM8260 has L2 cache! */
  53 #ifdef CONFIG_L2_CACHE
  54 #  define CONFIG_BUSMODE_60x    1       /* bus mode: 60x                        */
  55 #else
  56 #  undef  CONFIG_BUSMODE_60x            /* bus mode: 8260                       */
  57 #endif
  58
  59 /* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */
  60 #ifdef CONFIG_300MHz
  61 #  define CONFIG_BUSMODE_60x
  62 #endif
  63
  64 #define CONFIG_82xx_CONS_SMC1   1       /* console on SMC1                      */
  65
  66 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  67
  68 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  69
  70 #define CONFIG_PREBOOT  "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
  71
  72 #undef  CONFIG_BOOTARGS
  73
  74 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  75         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  76                 "nfsroot=$(serverip):$(rootpath)\0"                     \
  77         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  78         "addip=setenv bootargs $(bootargs) "                            \
  79                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
  80                 ":$(hostname):$(netdev):off panic=1\0"                  \
  81         "flash_nfs=run nfsargs addip;"                                  \
  82                 "bootm $(kernel_addr)\0"                                \
  83         "flash_self=run ramargs addip;"                                 \
  84                 "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
  85         "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"     \
  86         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
  87         "bootfile=/tftpboot/TQM8260/uImage\0"                           \
  88         "kernel_addr=40040000\0"                                        \
  89         "ramdisk_addr=40100000\0"                                       \
  90         ""
  91 #define CONFIG_BOOTCOMMAND      "run flash_self"
  92
  93 /* enable I2C and select the hardware/software driver */
  94 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  95 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  96 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
  97 #define CFG_I2C_SLAVE           0x7F
  98
  99 /*
 100  * Software (bit-bang) I2C driver configuration
 101  */
 102
 103 /* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
 104 #if (CONFIG_TQM8260 <= 100)
 105
 106 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 107 #define I2C_ACTIVE      (iop->pdir |=  0x00020000)
 108 #define I2C_TRISTATE    (iop->pdir &= ~0x00020000)
 109 #define I2C_READ        ((iop->pdat & 0x00020000) != 0)
 110 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00020000; \
 111                         else    iop->pdat &= ~0x00020000
 112 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00010000; \
 113                         else    iop->pdat &= ~0x00010000
 114 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 115
 116 #else
 117
 118 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 119 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 120 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 121 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 122 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 123                         else    iop->pdat &= ~0x00010000
 124 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 125                         else    iop->pdat &= ~0x00020000
 126 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 127 #endif
 128
 129 #define CFG_I2C_EEPROM_ADDR     0x50
 130 #define CFG_I2C_EEPROM_ADDR_LEN 2
 131 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 132 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 133
 134 #define CONFIG_I2C_X
 135
 136 /*
 137  * select serial console configuration
 138  *
 139  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 140  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 141  * for SCC).
 142  *
 143  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 144  * defined elsewhere (for example, on the cogent platform, there are serial
 145  * ports on the motherboard which are used for the serial console - see
 146  * cogent/cma101/serial.[ch]).
 147  */
 148 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
 149 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 150 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
 151 #ifdef CONFIG_82xx_CONS_SMC1
 152 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
 153 #endif
 154 #ifdef CONFIG_82xx_CONS_SMC2
 155 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
 156 #endif
 157
 158 #undef  CONFIG_CONS_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
 159 #define CONFIG_CONS_EXTC_RATE   3686400 /* SMC/SCC ext clk rate in Hz */
 160 #define CONFIG_CONS_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9 */
 161
 162 /*
 163  * select ethernet configuration
 164  *
 165  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 166  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 167  * for FCC)
 168  *
 169  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 170  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 171  * from CONFIG_COMMANDS to remove support for networking.
 172  *
 173  * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
 174  * X.29 connector, and FCC2 is hardwired to the X.1 connector)
 175  */
 176 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 177 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 178 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 179 #define CONFIG_ETHER_INDEX    2         /* which SCC/FCC channel for ethernet */
 180
 181 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
 182
 183 /*
 184  *  - RX clk is CLK11
 185  *  - TX clk is CLK12
 186  */
 187 # define CFG_CMXSCR_VALUE       (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
 188
 189 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 190
 191 /*
 192  * - Rx-CLK is CLK13
 193  * - Tx-CLK is CLK14
 194  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 195  * - Enable Full Duplex in FSMR
 196  */
 197 # define CFG_CMXFCR_MASK        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 198 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 199 # define CFG_CPMFCR_RAMTYPE     0
 200 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
 201
 202 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 203
 204
 205 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 206 #ifdef CONFIG_MPC8255
 207 #  define CONFIG_8260_CLKIN     66666666        /* in Hz */
 208 #else   /* !CONFIG_MPC8255 */
 209 # ifndef CONFIG_300MHz
 210 #  define CONFIG_8260_CLKIN     66666666        /* in Hz */
 211 # else
 212 #  define CONFIG_8260_CLKIN     83333000        /* in Hz */
 213 # endif
 214 #endif  /* CONFIG_MPC8255 */
 215
 216 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
 217 #define CONFIG_BAUDRATE         230400
 218 #else
 219 #define CONFIG_BAUDRATE         9600
 220 #endif
 221
 222 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 223 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
 224
 225 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 226
 227 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
 228
 229 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL | \
 230                                  CFG_CMD_I2C    | \
 231                                  CFG_CMD_EEPROM)
 232
 233 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 234 #include <cmd_confdefs.h>
 235
 236 /*
 237  * Miscellaneous configurable options
 238  */
 239 #define CFG_LONGHELP                    /* undef to save memory         */
 240 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 241 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 242 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 243 #else
 244 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 245 #endif
 246 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 247 #define CFG_MAXARGS     16              /* max number of command args   */
 248 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 249
 250 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 251 #define CFG_MEMTEST_END 0x0C00000       /* 4 ... 12 MB in DRAM  */
 252
 253 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 254
 255 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 256
 257 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 258
 259 #define CFG_RESET_ADDRESS 0xFFFFFFFC    /* "bad" address                */
 260
 261 /*
 262  * For booting Linux, the board info and command line data
 263  * have to be in the first 8 MB of memory, since this is
 264  * the maximum mapped by the Linux kernel during initialization.
 265  */
 266 #define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 267
 268
 269 /* What should the base address of the main FLASH be and how big is
 270  * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
 271  * The main FLASH is whichever is connected to *CS0.
 272  */
 273 #define CFG_FLASH0_BASE 0x40000000
 274 #define CFG_FLASH1_BASE 0x60000000
 275 #define CFG_FLASH0_SIZE 32
 276 #define CFG_FLASH1_SIZE 32
 277
 278 /* Flash bank size (for preliminary settings)
 279  */
 280 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
 281
 282 /*-----------------------------------------------------------------------
 283  * FLASH organization
 284  */
 285 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 286 #define CFG_MAX_FLASH_SECT      128     /* max num of sects on one chip */
 287
 288 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 289 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 290
 291 #if 0
 292 /* Start port with environment in flash; switch to EEPROM later */
 293 #define CFG_ENV_IS_IN_FLASH     1
 294 #define CFG_ENV_ADDR            (CFG_FLASH_BASE+0x40000)
 295 #define CFG_ENV_SIZE            0x40000
 296 #define CFG_ENV_SECT_SIZE       0x40000
 297 #else
 298 /* Final version: environment in EEPROM */
 299 #define CFG_ENV_IS_IN_EEPROM    1
 300 #define CFG_ENV_OFFSET          0
 301 #define CFG_ENV_SIZE            2048
 302 #endif
 303
 304 /*-----------------------------------------------------------------------
 305  * Hardware Information Block
 306  */
 307 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 308 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 309 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 310
 311 /*-----------------------------------------------------------------------
 312  * Hard Reset Configuration Words
 313  *
 314  * if you change bits in the HRCW, you must also change the CFG_*
 315  * defines for the various registers affected by the HRCW e.g. changing
 316  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 317  */
 318 #define __HRCW__ALL__           (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 319
 320 #ifdef  CONFIG_MPC8255
 321 #  define CFG_HRCW_MASTER       (__HRCW__ALL__ | HRCW_MODCK_H0111)
 322 #else   /* ! MPC8255 */
 323 # if defined(CONFIG_266MHz)
 324 #  define CFG_HRCW_MASTER       (__HRCW__ALL__ | HRCW_MODCK_H0111)
 325 # elif defined(CONFIG_300MHz)
 326 #  define CFG_HRCW_MASTER       (__HRCW__ALL__ | HRCW_MODCK_H0110)
 327 # else
 328 #  define CFG_HRCW_MASTER       (__HRCW__ALL__)
 329 # endif
 330 #endif  /* CONFIG_MPC8255 */
 331
 332 /* no slaves so just fill with zeros */
 333 #define CFG_HRCW_SLAVE1         0
 334 #define CFG_HRCW_SLAVE2         0
 335 #define CFG_HRCW_SLAVE3         0
 336 #define CFG_HRCW_SLAVE4         0
 337 #define CFG_HRCW_SLAVE5         0
 338 #define CFG_HRCW_SLAVE6         0
 339 #define CFG_HRCW_SLAVE7         0
 340
 341 /*-----------------------------------------------------------------------
 342  * Internal Memory Mapped Register
 343  */
 344 #define CFG_IMMR                0xFFF00000
 345
 346 /*-----------------------------------------------------------------------
 347  * Definitions for initial stack pointer and data area (in DPRAM)
 348  */
 349 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 350 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 351 #define CFG_GBL_DATA_SIZE       128 /* size in bytes reserved for initial data*/
 352 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 353 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 354
 355 /*-----------------------------------------------------------------------
 356  * Start addresses for the final memory configuration
 357  * (Set up by the startup code)
 358  * Please note that CFG_SDRAM_BASE _must_ start at 0
 359  *
 360  * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
 361  * is mapped at SDRAM_BASE2_PRELIM.
 362  */
 363 #define CFG_SDRAM_BASE          0x00000000
 364 #define CFG_FLASH_BASE          CFG_FLASH0_BASE
 365 #define CFG_MONITOR_BASE        TEXT_BASE
 366 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor */
 367 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()*/
 368
 369 /*
 370  * Internal Definitions
 371  *
 372  * Boot Flags
 373  */
 374 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH*/
 375 #define BOOTFLAG_WARM           0x02    /* Software reboot                 */
 376
 377
 378 /*-----------------------------------------------------------------------
 379  * Cache Configuration
 380  */
 381 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 382 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 383 # define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 384 #endif
 385
 386 /*-----------------------------------------------------------------------
 387  * HIDx - Hardware Implementation-dependent Registers                    2-11
 388  *-----------------------------------------------------------------------
 389  * HID0 also contains cache control - initially enable both caches and
 390  * invalidate contents, then the final state leaves only the instruction
 391  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 392  * but Soft reset does not.
 393  *
 394  * HID1 has only read-only information - nothing to set.
 395  */
 396 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 397                                 HID0_IFEM|HID0_ABE)
 398 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 399 #define CFG_HID2        0
 400
 401 /*-----------------------------------------------------------------------
 402  * RMR - Reset Mode Register                                     5-5
 403  *-----------------------------------------------------------------------
 404  * turn on Checkstop Reset Enable
 405  */
 406 #define CFG_RMR         RMR_CSRE
 407
 408 /*-----------------------------------------------------------------------
 409  * BCR - Bus Configuration                                       4-25
 410  *-----------------------------------------------------------------------
 411  */
 412 #ifdef  CONFIG_BUSMODE_60x
 413 #define CFG_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
 414                          BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode  */
 415 #else
 416 #define BCR_APD01       0x10000000
 417 #define CFG_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 418 #endif
 419
 420 /*-----------------------------------------------------------------------
 421  * SIUMCR - SIU Module Configuration                             4-31
 422  *-----------------------------------------------------------------------
 423  */
 424 #if 0
 425 #define CFG_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
 426 #else
 427 #define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
 428 #endif
 429
 430
 431 /*-----------------------------------------------------------------------
 432  * SYPCR - System Protection Control                             4-35
 433  * SYPCR can only be written once after reset!
 434  *-----------------------------------------------------------------------
 435  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 436  */
 437 #if defined(CONFIG_WATCHDOG)
 438 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 439                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 440 #else
 441 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 442                          SYPCR_SWRI|SYPCR_SWP)
 443 #endif /* CONFIG_WATCHDOG */
 444
 445 /*-----------------------------------------------------------------------
 446  * TMCNTSC - Time Counter Status and Control                     4-40
 447  *-----------------------------------------------------------------------
 448  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 449  * and enable Time Counter
 450  */
 451 #define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 452
 453 /*-----------------------------------------------------------------------
 454  * PISCR - Periodic Interrupt Status and Control                 4-42
 455  *-----------------------------------------------------------------------
 456  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 457  * Periodic timer
 458  */
 459 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 460
 461 /*-----------------------------------------------------------------------
 462  * SCCR - System Clock Control                                   9-8
 463  *-----------------------------------------------------------------------
 464  * Ensure DFBRG is Divide by 16
 465  */
 466 #define CFG_SCCR        0
 467
 468 /*-----------------------------------------------------------------------
 469  * RCCR - RISC Controller Configuration                         13-7
 470  *-----------------------------------------------------------------------
 471  */
 472 #define CFG_RCCR        0
 473
 474 /*
 475  * Init Memory Controller:
 476  *
 477  * Bank Bus     Machine PortSz  Device
 478  * ---- ---     ------- ------  ------
 479  *  0   60x     GPCM    64 bit  FLASH
 480  *  1   60x     SDRAM   64 bit  SDRAM
 481  *  2   Local   SDRAM   32 bit  SDRAM
 482  *
 483  */
 484
 485         /* Initialize SDRAM on local bus
 486          */
 487 #define CFG_INIT_LOCAL_SDRAM
 488
 489 #define SDRAM_MAX_SIZE  0x08000000      /* max. 128 MB          */
 490
 491 /* Minimum mask to separate preliminary
 492  * address ranges for CS[0:2]
 493  */
 494 #define CFG_GLOBAL_SDRAM_LIMIT  (512<<20)       /* less than 512 MB */
 495 #define CFG_LOCAL_SDRAM_LIMIT   (128<<20)       /* less than 128 MB */
 496
 497 #define CFG_MPTPR       0x4000
 498
 499 /*-----------------------------------------------------------------------------
 500  * Address for Mode Register Set (MRS) command
 501  *-----------------------------------------------------------------------------
 502  * In fact, the address is rather configuration data presented to the SDRAM on
 503  * its address lines. Because the address lines may be mux'ed externally either
 504  * for 8 column or 9 column devices, some bits appear twice in the 8260's
 505  * address:
 506  *
 507  * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
 508  * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
 509  *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
 510  *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
 511  *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
 512  *-----------------------------------------------------------------------------
 513  */
 514 #define CFG_MRS_OFFS    0x00000110
 515
 516
 517 /* Bank 0 - FLASH
 518  */
 519 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
 520                          BRx_PS_64                      |\
 521                          BRx_MS_GPCM_P                  |\
 522                          BRx_V)
 523
 524 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
 525                          ORxG_CSNT                      |\
 526                          ORxG_ACS_DIV1                  |\
 527                          ORxG_SCY_3_CLK                 |\
 528                          ORxG_EHTR                      |\
 529                          ORxG_TRLX)
 530
 531         /* SDRAM on TQM8260 can have either 8 or 9 columns.
 532          * The number affects configuration values.
 533          */
 534
 535 /* Bank 1 - 60x bus SDRAM
 536  */
 537 #define CFG_PSRT        0x20
 538 #define CFG_LSRT        0x20
 539 #ifndef CFG_RAMBOOT
 540 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
 541                          BRx_PS_64                      |\
 542                          BRx_MS_SDRAM_P                 |\
 543                          BRx_V)
 544
 545 #define CFG_OR1_PRELIM  CFG_OR1_8COL
 546
 547
 548         /* SDRAM initialization values for 8-column chips
 549          */
 550 #define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 551                          ORxS_BPD_4                     |\
 552                          ORxS_ROWST_PBI1_A7             |\
 553                          ORxS_NUMR_12)
 554
 555 #define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
 556                          PSDMR_SDAM_A15_IS_A5           |\
 557                          PSDMR_BSMA_A12_A14             |\
 558                          PSDMR_SDA10_PBI1_A8            |\
 559                          PSDMR_RFRC_7_CLK               |\
 560                          PSDMR_PRETOACT_2W              |\
 561                          PSDMR_ACTTORW_2W               |\
 562                          PSDMR_LDOTOPRE_1C              |\
 563                          PSDMR_WRC_2C                   |\
 564                          PSDMR_EAMUX                    |\
 565                          PSDMR_CL_2)
 566
 567         /* SDRAM initialization values for 9-column chips
 568          */
 569 #define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 570                          ORxS_BPD_4                     |\
 571                          ORxS_ROWST_PBI1_A5             |\
 572                          ORxS_NUMR_13)
 573
 574 #define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
 575                          PSDMR_SDAM_A16_IS_A5           |\
 576                          PSDMR_BSMA_A12_A14             |\
 577                          PSDMR_SDA10_PBI1_A7            |\
 578                          PSDMR_RFRC_7_CLK               |\
 579                          PSDMR_PRETOACT_2W              |\
 580                          PSDMR_ACTTORW_2W               |\
 581                          PSDMR_LDOTOPRE_1C              |\
 582                          PSDMR_WRC_2C                   |\
 583                          PSDMR_EAMUX                    |\
 584                          PSDMR_CL_2)
 585
 586 /* Bank 2 - Local bus SDRAM
 587  */
 588 #ifdef CFG_INIT_LOCAL_SDRAM
 589 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
 590                          BRx_PS_32                      |\
 591                          BRx_MS_SDRAM_L                 |\
 592                          BRx_V)
 593
 594 #define CFG_OR2_PRELIM  CFG_OR2_8COL
 595
 596 #define SDRAM_BASE2_PRELIM      0x80000000
 597
 598         /* SDRAM initialization values for 8-column chips
 599          */
 600 #define CFG_OR2_8COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 601                          ORxS_BPD_4                     |\
 602                          ORxS_ROWST_PBI1_A8             |\
 603                          ORxS_NUMR_12)
 604
 605 #define CFG_LSDMR_8COL  (PSDMR_PBI                      |\
 606                          PSDMR_SDAM_A15_IS_A5           |\
 607                          PSDMR_BSMA_A13_A15             |\
 608                          PSDMR_SDA10_PBI1_A9            |\
 609                          PSDMR_RFRC_7_CLK               |\
 610                          PSDMR_PRETOACT_2W              |\
 611                          PSDMR_ACTTORW_2W               |\
 612                          PSDMR_BL                       |\
 613                          PSDMR_LDOTOPRE_1C              |\
 614                          PSDMR_WRC_2C                   |\
 615                          PSDMR_CL_2)
 616
 617         /* SDRAM initialization values for 9-column chips
 618          */
 619 #define CFG_OR2_9COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 620                          ORxS_BPD_4                     |\
 621                          ORxS_ROWST_PBI1_A6             |\
 622                          ORxS_NUMR_13)
 623
 624 #define CFG_LSDMR_9COL  (PSDMR_PBI                      |\
 625                          PSDMR_SDAM_A16_IS_A5           |\
 626                          PSDMR_BSMA_A13_A15             |\
 627                          PSDMR_SDA10_PBI1_A8            |\
 628                          PSDMR_RFRC_7_CLK               |\
 629                          PSDMR_PRETOACT_2W              |\
 630                          PSDMR_ACTTORW_2W               |\
 631                          PSDMR_BL                       |\
 632                          PSDMR_LDOTOPRE_1C              |\
 633                          PSDMR_WRC_2C                   |\
 634                          PSDMR_CL_2)
 635
 636 #endif /* CFG_INIT_LOCAL_SDRAM */
 637
 638 #endif /* CFG_RAMBOOT */
 639
 640 #endif  /* __CONFIG_H */