]>
git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/TQM8260.h
2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * Imported from global configuration:
43 * High Level Configuration Options
47 #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
50 #define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */
52 #define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */
55 #define CONFIG_CPM2 1 /* Has a CPM2 */
57 #define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
59 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
61 #define CONFIG_BOOTCOUNT_LIMIT
63 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
64 #define CONFIG_BAUDRATE 230400
66 #define CONFIG_BAUDRATE 9600
69 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
71 #undef CONFIG_BOOTARGS
73 #define CONFIG_EXTRA_ENV_SETTINGS \
75 "nfsargs=setenv bootargs root=/dev/nfs rw " \
76 "nfsroot=${serverip}:${rootpath}\0" \
77 "ramargs=setenv bootargs root=/dev/ram rw\0" \
78 "addip=setenv bootargs ${bootargs} " \
79 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
80 ":${hostname}:${netdev}:off panic=1\0" \
81 "flash_nfs=run nfsargs addip;" \
82 "bootm ${kernel_addr}\0" \
83 "flash_self=run ramargs addip;" \
84 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
85 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
86 "rootpath=/opt/eldk/ppc_82xx\0" \
87 "bootfile=/tftpboot/TQM8260/uImage\0" \
88 "kernel_addr=40040000\0" \
89 "ramdisk_addr=40100000\0" \
91 #define CONFIG_BOOTCOMMAND "run flash_self"
93 /* enable I2C and select the hardware/software driver */
94 #undef CONFIG_HARD_I2C /* I2C with hardware support */
95 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
96 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
97 #define CFG_I2C_SLAVE 0x7F
100 * Software (bit-bang) I2C driver configuration
103 /* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
104 #if (CONFIG_TQM8260 <= 100)
106 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
107 #define I2C_ACTIVE (iop->pdir |= 0x00020000)
108 #define I2C_TRISTATE (iop->pdir &= ~0x00020000)
109 #define I2C_READ ((iop->pdat & 0x00020000) != 0)
110 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \
111 else iop->pdat &= ~0x00020000
112 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \
113 else iop->pdat &= ~0x00010000
114 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
118 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
119 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
120 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
121 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
122 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
123 else iop->pdat &= ~0x00010000
124 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
125 else iop->pdat &= ~0x00020000
126 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
129 #define CFG_I2C_EEPROM_ADDR 0x50
130 #define CFG_I2C_EEPROM_ADDR_LEN 2
131 #define CFG_EEPROM_PAGE_WRITE_BITS 4
132 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
137 * select serial console configuration
139 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
140 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
143 * if CONFIG_CONS_NONE is defined, then the serial console routines must
144 * defined elsewhere (for example, on the cogent platform, there are serial
145 * ports on the motherboard which are used for the serial console - see
146 * cogent/cma101/serial.[ch]).
148 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
149 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
150 #undef CONFIG_CONS_NONE /* define if console on something else*/
151 #ifdef CONFIG_82xx_CONS_SMC1
152 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
154 #ifdef CONFIG_82xx_CONS_SMC2
155 #define CONFIG_CONS_INDEX 2 /* which serial channel for console */
158 #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
159 #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
160 #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
163 * select ethernet configuration
165 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
166 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
169 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
170 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
172 * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
173 * X.29 connector, and FCC2 is hardwired to the X.1 connector)
175 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
176 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
177 #undef CONFIG_ETHER_NONE /* define if ether on something else */
178 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
180 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
186 # define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
188 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
193 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
194 * - Enable Full Duplex in FSMR
196 # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
197 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
198 # define CFG_CPMFCR_RAMTYPE 0
199 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
201 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
204 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
205 #if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
206 # define CONFIG_8260_CLKIN 66666666 /* in Hz */
207 #else /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */
208 # ifndef CONFIG_300MHz
209 # define CONFIG_8260_CLKIN 66666666 /* in Hz */
211 # define CONFIG_8260_CLKIN 83333000 /* in Hz */
213 #endif /* CONFIG_MPC8255 */
215 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
216 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
218 #undef CONFIG_WATCHDOG /* watchdog disabled */
220 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
222 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
226 * Command line configuration.
228 #include <config_cmd_default.h>
230 #define CONFIG_CMD_DHCP
231 #define CONFIG_CMD_I2C
232 #define CONFIG_CMD_EEPROM
233 #define CONFIG_CMD_NFS
234 #define CONFIG_CMD_SNTP
238 * Miscellaneous configurable options
240 #define CFG_LONGHELP /* undef to save memory */
241 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
243 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
244 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
245 #ifdef CFG_HUSH_PARSER
246 #define CFG_PROMPT_HUSH_PS2 "> "
249 #if defined(CONFIG_CMD_KGDB)
250 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
252 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
254 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
255 #define CFG_MAXARGS 16 /* max number of command args */
256 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
258 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
259 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
261 #define CFG_LOAD_ADDR 0x100000 /* default load address */
263 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
265 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
267 #define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */
270 * For booting Linux, the board info and command line data
271 * have to be in the first 8 MB of memory, since this is
272 * the maximum mapped by the Linux kernel during initialization.
274 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
277 /* What should the base address of the main FLASH be and how big is
278 * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
279 * The main FLASH is whichever is connected to *CS0.
281 #define CFG_FLASH0_BASE 0x40000000
282 #define CFG_FLASH1_BASE 0x60000000
283 #define CFG_FLASH0_SIZE 32
284 #define CFG_FLASH1_SIZE 32
286 /* Flash bank size (for preliminary settings)
288 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
290 /*-----------------------------------------------------------------------
293 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
294 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
296 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
297 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
300 /* Start port with environment in flash; switch to EEPROM later */
301 #define CFG_ENV_IS_IN_FLASH 1
302 #define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
303 #define CFG_ENV_SIZE 0x40000
304 #define CFG_ENV_SECT_SIZE 0x40000
306 /* Final version: environment in EEPROM */
307 #define CFG_ENV_IS_IN_EEPROM 1
308 #define CFG_ENV_OFFSET 0
309 #define CFG_ENV_SIZE 2048
312 /*-----------------------------------------------------------------------
313 * Hardware Information Block
315 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
316 #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
317 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
319 /*-----------------------------------------------------------------------
320 * Hard Reset Configuration Words
322 * if you change bits in the HRCW, you must also change the CFG_*
323 * defines for the various registers affected by the HRCW e.g. changing
324 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
326 #define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
328 #if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
329 # define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
330 #else /* ! MPC8255 && !MPC8265 */
331 # if defined(CONFIG_266MHz)
332 # define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
333 # elif defined(CONFIG_300MHz)
334 # define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110)
336 # define CFG_HRCW_MASTER (__HRCW__ALL__)
338 #endif /* CONFIG_MPC8255 */
340 /* no slaves so just fill with zeros */
341 #define CFG_HRCW_SLAVE1 0
342 #define CFG_HRCW_SLAVE2 0
343 #define CFG_HRCW_SLAVE3 0
344 #define CFG_HRCW_SLAVE4 0
345 #define CFG_HRCW_SLAVE5 0
346 #define CFG_HRCW_SLAVE6 0
347 #define CFG_HRCW_SLAVE7 0
349 /*-----------------------------------------------------------------------
350 * Internal Memory Mapped Register
352 #define CFG_IMMR 0xFFF00000
354 /*-----------------------------------------------------------------------
355 * Definitions for initial stack pointer and data area (in DPRAM)
357 #define CFG_INIT_RAM_ADDR CFG_IMMR
358 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
359 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
360 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
361 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
363 /*-----------------------------------------------------------------------
364 * Start addresses for the final memory configuration
365 * (Set up by the startup code)
366 * Please note that CFG_SDRAM_BASE _must_ start at 0
368 * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
369 * is mapped at SDRAM_BASE2_PRELIM.
371 #define CFG_SDRAM_BASE 0x00000000
372 #define CFG_FLASH_BASE CFG_FLASH0_BASE
373 #define CFG_MONITOR_BASE TEXT_BASE
374 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
375 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
378 * Internal Definitions
382 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
383 #define BOOTFLAG_WARM 0x02 /* Software reboot */
386 /*-----------------------------------------------------------------------
387 * Cache Configuration
389 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
390 #if defined(CONFIG_CMD_KGDB)
391 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
394 /*-----------------------------------------------------------------------
395 * HIDx - Hardware Implementation-dependent Registers 2-11
396 *-----------------------------------------------------------------------
397 * HID0 also contains cache control - initially enable both caches and
398 * invalidate contents, then the final state leaves only the instruction
399 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
400 * but Soft reset does not.
402 * HID1 has only read-only information - nothing to set.
404 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
406 #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
409 /*-----------------------------------------------------------------------
410 * RMR - Reset Mode Register 5-5
411 *-----------------------------------------------------------------------
412 * turn on Checkstop Reset Enable
414 #define CFG_RMR RMR_CSRE
416 /*-----------------------------------------------------------------------
417 * BCR - Bus Configuration 4-25
418 *-----------------------------------------------------------------------
420 #ifdef CONFIG_BUSMODE_60x
421 #define CFG_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\
422 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */
424 #define BCR_APD01 0x10000000
425 #define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
428 /*-----------------------------------------------------------------------
429 * SIUMCR - SIU Module Configuration 4-31
430 *-----------------------------------------------------------------------
433 #define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
435 #define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10)
439 /*-----------------------------------------------------------------------
440 * SYPCR - System Protection Control 4-35
441 * SYPCR can only be written once after reset!
442 *-----------------------------------------------------------------------
443 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
445 #if defined(CONFIG_WATCHDOG)
446 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
447 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
449 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
450 SYPCR_SWRI|SYPCR_SWP)
451 #endif /* CONFIG_WATCHDOG */
453 /*-----------------------------------------------------------------------
454 * TMCNTSC - Time Counter Status and Control 4-40
455 *-----------------------------------------------------------------------
456 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
457 * and enable Time Counter
459 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
461 /*-----------------------------------------------------------------------
462 * PISCR - Periodic Interrupt Status and Control 4-42
463 *-----------------------------------------------------------------------
464 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
467 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
469 /*-----------------------------------------------------------------------
470 * SCCR - System Clock Control 9-8
471 *-----------------------------------------------------------------------
472 * Ensure DFBRG is Divide by 16
476 /*-----------------------------------------------------------------------
477 * RCCR - RISC Controller Configuration 13-7
478 *-----------------------------------------------------------------------
483 * Init Memory Controller:
485 * Bank Bus Machine PortSz Device
486 * ---- --- ------- ------ ------
487 * 0 60x GPCM 64 bit FLASH
488 * 1 60x SDRAM 64 bit SDRAM
489 * 2 Local SDRAM 32 bit SDRAM
493 /* Initialize SDRAM on local bus
495 #define CFG_INIT_LOCAL_SDRAM
497 #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
499 /* Minimum mask to separate preliminary
500 * address ranges for CS[0:2]
502 #define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
503 #define CFG_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */
505 #define CFG_MPTPR 0x4000
507 /*-----------------------------------------------------------------------------
508 * Address for Mode Register Set (MRS) command
509 *-----------------------------------------------------------------------------
510 * In fact, the address is rather configuration data presented to the SDRAM on
511 * its address lines. Because the address lines may be mux'ed externally either
512 * for 8 column or 9 column devices, some bits appear twice in the 8260's
515 * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
516 * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
517 * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
518 * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
519 * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
520 *-----------------------------------------------------------------------------
522 #define CFG_MRS_OFFS 0x00000110
527 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
532 #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
539 /* SDRAM on TQM8260 can have either 8 or 9 columns.
540 * The number affects configuration values.
543 /* Bank 1 - 60x bus SDRAM
545 #define CFG_PSRT 0x20
546 #define CFG_LSRT 0x20
548 #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
553 #define CFG_OR1_PRELIM CFG_OR1_8COL
556 /* SDRAM initialization values for 8-column chips
558 #define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
560 ORxS_ROWST_PBI1_A7 |\
563 #define CFG_PSDMR_8COL (PSDMR_PBI |\
564 PSDMR_SDAM_A15_IS_A5 |\
565 PSDMR_BSMA_A12_A14 |\
566 PSDMR_SDA10_PBI1_A8 |\
575 /* SDRAM initialization values for 9-column chips
577 #define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
579 ORxS_ROWST_PBI1_A5 |\
582 #define CFG_PSDMR_9COL (PSDMR_PBI |\
583 PSDMR_SDAM_A16_IS_A5 |\
584 PSDMR_BSMA_A12_A14 |\
585 PSDMR_SDA10_PBI1_A7 |\
594 /* Bank 2 - Local bus SDRAM
596 #ifdef CFG_INIT_LOCAL_SDRAM
597 #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
602 #define CFG_OR2_PRELIM CFG_OR2_8COL
604 #define SDRAM_BASE2_PRELIM 0x80000000
606 /* SDRAM initialization values for 8-column chips
608 #define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
610 ORxS_ROWST_PBI1_A8 |\
613 #define CFG_LSDMR_8COL (PSDMR_PBI |\
614 PSDMR_SDAM_A15_IS_A5 |\
615 PSDMR_BSMA_A13_A15 |\
616 PSDMR_SDA10_PBI1_A9 |\
625 /* SDRAM initialization values for 9-column chips
627 #define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
629 ORxS_ROWST_PBI1_A6 |\
632 #define CFG_LSDMR_9COL (PSDMR_PBI |\
633 PSDMR_SDAM_A16_IS_A5 |\
634 PSDMR_BSMA_A13_A15 |\
635 PSDMR_SDA10_PBI1_A8 |\
644 #endif /* CFG_INIT_LOCAL_SDRAM */
646 #endif /* CFG_RAMBOOT */
648 #endif /* __CONFIG_H */