include/configs/TQM8272.h

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC8260          1       /* This is a MPC8260 CPU                */
  21 #define CONFIG_MPC8272_FAMILY   1
  22 #define CONFIG_TQM8272          1
  23
  24 #define CONFIG_SYS_TEXT_BASE    0x40000000
  25
  26 #define CONFIG_GET_CPU_STR_F    1       /* Get the CPU ID STR */
  27 #define CONFIG_BOARD_GET_CPU_CLK_F      1 /* Get the CLKIN from board fct */
  28
  29 #define STK82xx_150             1       /* on a STK82xx.150 */
  30
  31 #define CONFIG_CPM2             1       /* Has a CPM2 */
  32
  33 #define CONFIG_82xx_CONS_SMC1   1       /* console on SMC1              */
  34
  35 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  36
  37 #define CONFIG_BOARD_EARLY_INIT_R       1
  38
  39 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  40 #define CONFIG_BAUDRATE         230400
  41 #else
  42 #define CONFIG_BAUDRATE         115200
  43 #endif
  44
  45 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  46
  47 #undef  CONFIG_BOOTARGS
  48
  49 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  50         "netdev=eth0\0"                                                 \
  51         "consdev=ttyCPM0\0"                                             \
  52         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  53                 "nfsroot=${serverip}:${rootpath}\0"                     \
  54         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  55         "hostname=tqm8272\0"                                            \
  56         "addip=setenv bootargs ${bootargs} "                            \
  57                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  58                 ":${hostname}:${netdev}:off panic=1\0"                  \
  59         "addcons=setenv bootargs ${bootargs} "                          \
  60                 "console=$(consdev),$(baudrate)\0"                      \
  61         "flash_nfs=run nfsargs addip addcons;"                          \
  62                 "bootm ${kernel_addr}\0"                                \
  63         "flash_self=run ramargs addip addcons;"                         \
  64                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  65         "net_nfs=tftp 300000 ${bootfile};"                              \
  66                 "run nfsargs addip addcons;bootm\0"                     \
  67         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
  68         "bootfile=/tftpboot/tqm8272/uImage\0"                           \
  69         "kernel_addr=40080000\0"                                        \
  70         "ramdisk_addr=40100000\0"                                       \
  71         "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0"               \
  72         "update=protect off 40000000 4003ffff;era 40000000 4003ffff;"   \
  73                 "cp.b 300000 40000000 40000;"                           \
  74                 "setenv filesize;saveenv\0"                             \
  75         "cphwib=cp.b 4003fc00 33fc00 400\0"                             \
  76         "upd=run load cphwib update\0"                                  \
  77         ""
  78 #define CONFIG_BOOTCOMMAND      "run flash_self"
  79
  80 #define CONFIG_I2C      1
  81
  82 #if CONFIG_I2C
  83 /* enable I2C and select the hardware/software driver */
  84 #define CONFIG_SYS_I2C
  85 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
  86 #define CONFIG_SYS_I2C_SOFT_SPEED       400000
  87 #define CONFIG_SYS_I2C_SOFT_SLAVE       0x7F
  88 /*
  89  * Software (bit-bang) I2C driver configuration
  90  */
  91 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
  92 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
  93 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
  94 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
  95 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
  96                         else    iop->pdat &= ~0x00010000
  97 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
  98                         else    iop->pdat &= ~0x00020000
  99 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 100
 101 #define CONFIG_I2C_X
 102
 103 /* EEPROM */
 104 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 105 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 106 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 107 #define CONFIG_SYS_I2C_MULTI_EEPROMS            1       /* more than one eeprom */
 108
 109 /* I2C RTC */
 110 #define CONFIG_RTC_DS1337               /* Use ds1337 rtc via i2c       */
 111 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68              */
 112
 113 /* I2C SYSMON (LM75) */
 114 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 115 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 116 #define CONFIG_SYS_DTT_MAX_TEMP 70
 117 #define CONFIG_SYS_DTT_LOW_TEMP -30
 118 #define CONFIG_SYS_DTT_HYSTERESIS       3
 119
 120 #else
 121 #undef CONFIG_SYS_I2C
 122 #undef CONFIG_HARD_I2C
 123 #undef CONFIG_SYS_I2C_SOFT
 124 #endif
 125
 126 /*
 127  * select serial console configuration
 128  *
 129  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 130  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 131  * for SCC).
 132  *
 133  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 134  * defined elsewhere (for example, on the cogent platform, there are serial
 135  * ports on the motherboard which are used for the serial console - see
 136  * cogent/cma101/serial.[ch]).
 137  */
 138 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
 139 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 140 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
 141 #ifdef CONFIG_82xx_CONS_SMC1
 142 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
 143 #endif
 144 #ifdef CONFIG_82xx_CONS_SMC2
 145 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
 146 #endif
 147
 148 #undef  CONFIG_CONS_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
 149 #define CONFIG_CONS_EXTC_RATE   3686400 /* SMC/SCC ext clk rate in Hz */
 150 #define CONFIG_CONS_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9 */
 151
 152 /*
 153  * select ethernet configuration
 154  *
 155  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 156  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 157  * for FCC)
 158  *
 159  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 160  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 161  *
 162  * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
 163  * X.29 connector, and FCC2 is hardwired to the X.1 connector)
 164  */
 165 #define CONFIG_SYS_FCC_ETHERNET
 166
 167 #if defined(CONFIG_SYS_FCC_ETHERNET)
 168 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 169 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 170 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 171 #define CONFIG_ETHER_INDEX    2         /* which SCC/FCC channel for ethernet */
 172 #else
 173 #define CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 174 #undef  CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 175 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 176 #define CONFIG_ETHER_INDEX    1         /* which SCC/FCC channel for ethernet */
 177 #endif
 178
 179 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
 180
 181 /*
 182  *  - RX clk is CLK11
 183  *  - TX clk is CLK12
 184  */
 185 # define CONFIG_SYS_CMXSCR_VALUE        (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
 186
 187 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 188
 189 /*
 190  * - Rx-CLK is CLK13
 191  * - Tx-CLK is CLK14
 192  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 193  * - Enable Full Duplex in FSMR
 194  */
 195 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 196 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 197 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 198 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
 199
 200 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 201
 202 #define CONFIG_MII                      /* MII PHY management           */
 203 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 204 /*
 205  * GPIO pins used for bit-banged MII communications
 206  */
 207 #define MDIO_PORT       2               /* Port C */
 208 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 209                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 210 #define MDC_DECLARE     MDIO_DECLARE
 211
 212 #if STK82xx_150
 213 #define CONFIG_SYS_MDIO_PIN     0x00008000      /* PC16 */
 214 #define CONFIG_SYS_MDC_PIN      0x00004000      /* PC17 */
 215 #endif
 216
 217 #if STK82xx_100
 218 #define CONFIG_SYS_MDIO_PIN     0x00000002      /* PC30 */
 219 #define CONFIG_SYS_MDC_PIN      0x00000001      /* PC31 */
 220 #endif
 221
 222 #if 1
 223 #define MDIO_ACTIVE     (iop->pdir |=  CONFIG_SYS_MDIO_PIN)
 224 #define MDIO_TRISTATE   (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
 225 #define MDIO_READ       ((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 226
 227 #define MDIO(bit)       if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
 228                         else    iop->pdat &= ~CONFIG_SYS_MDIO_PIN
 229
 230 #define MDC(bit)        if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
 231                         else    iop->pdat &= ~CONFIG_SYS_MDC_PIN
 232 #else
 233 #define MDIO_ACTIVE     ({unsigned long tmp; tmp = iop->pdir; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
 234 #define MDIO_TRISTATE   ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
 235 #define MDIO_READ       ((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 236
 237 #define MDIO(bit)       if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\
 238                         else    {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}
 239
 240 #define MDC(bit)        if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\
 241                         else    {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}
 242 #endif
 243
 244 #define MIIDELAY        udelay(1)
 245
 246
 247 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 248 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
 249
 250 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 251 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 252
 253 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 254
 255 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 256
 257 /*
 258  * BOOTP options
 259  */
 260 #define CONFIG_BOOTP_SUBNETMASK
 261 #define CONFIG_BOOTP_GATEWAY
 262 #define CONFIG_BOOTP_HOSTNAME
 263 #define CONFIG_BOOTP_BOOTPATH
 264 #define CONFIG_BOOTP_BOOTFILESIZE
 265
 266
 267 /*
 268  * Command line configuration.
 269  */
 270 #include <config_cmd_default.h>
 271
 272 #define CONFIG_CMD_I2C
 273 #define CONFIG_CMD_DHCP
 274 #define CONFIG_CMD_MII
 275 #define CONFIG_CMD_NAND
 276 #define CONFIG_CMD_NFS
 277 #define CONFIG_CMD_PCI
 278 #define CONFIG_CMD_PING
 279 #define CONFIG_CMD_SNTP
 280
 281 #if CONFIG_I2C
 282     #define CONFIG_CMD_I2C
 283     #define CONFIG_CMD_DATE
 284     #define CONFIG_CMD_DTT
 285     #define CONFIG_CMD_EEPROM
 286 #endif
 287
 288
 289 /*
 290  * Miscellaneous configurable options
 291  */
 292 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 293
 294 #if 0
 295 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 296 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 297 #endif
 298
 299 #if defined(CONFIG_CMD_KGDB)
 300 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 301 #else
 302 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 303 #endif
 304 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 305 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 306 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 307
 308 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 309 #define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
 310
 311 #define CONFIG_SYS_LOAD_ADDR    0x300000        /* default load address */
 312
 313 #define CONFIG_SYS_RESET_ADDRESS 0x40000104     /* "bad" address                */
 314
 315 /*
 316  * For booting Linux, the board info and command line data
 317  * have to be in the first 8 MB of memory, since this is
 318  * the maximum mapped by the Linux kernel during initialization.
 319  */
 320 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 321
 322 /*-----------------------------------------------------------------------
 323  * CAN stuff
 324  *-----------------------------------------------------------------------
 325  */
 326 #define CONFIG_SYS_CAN_BASE     0x51000000
 327 #define CONFIG_SYS_CAN_SIZE     1
 328 #define CONFIG_SYS_CAN_BR       ((CONFIG_SYS_CAN_BASE & BRx_BA_MSK)     |\
 329                          BRx_PS_8                       |\
 330                          BRx_MS_UPMC                    |\
 331                          BRx_V)
 332
 333 #define CONFIG_SYS_CAN_OR       (MEG_TO_AM(CONFIG_SYS_CAN_SIZE) |\
 334                          ORxU_BI)
 335
 336
 337 /* What should the base address of the main FLASH be and how big is
 338  * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk
 339  * The main FLASH is whichever is connected to *CS0.
 340  */
 341 #define CONFIG_SYS_FLASH0_BASE 0x40000000
 342 #define CONFIG_SYS_FLASH0_SIZE 32       /* 32 MB */
 343
 344 /* Flash bank size (for preliminary settings)
 345  */
 346 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 347
 348 /*-----------------------------------------------------------------------
 349  * FLASH organization
 350  */
 351 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 352 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 353
 354 #define CONFIG_SYS_FLASH_CFI                            /* flash is CFI compat. */
 355 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver*/
 356 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector   */
 357 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash*/
 358
 359 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 360 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 361
 362 #define CONFIG_SYS_UPDATE_FLASH_SIZE
 363
 364 #define CONFIG_ENV_IS_IN_FLASH  1
 365 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x40000)
 366 #define CONFIG_ENV_SIZE         0x20000
 367 #define CONFIG_ENV_SECT_SIZE    0x20000
 368 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
 369 #define CONFIG_ENV_SIZE_REDUND  0x20000
 370
 371 /* Where is the Hardwareinformation Block (from Monitor Sources) */
 372 #define MON_RES_LENGTH          (0x0003FC00)
 373 #define HWIB_INFO_START_ADDR    (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH)
 374 #define HWIB_INFO_LEN           512
 375 #define CIB_INFO_START_ADDR     (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
 376 #define CIB_INFO_LEN            512
 377
 378 #define CONFIG_SYS_HWINFO_OFFSET        0x3fc00 /* offset of HW Info block */
 379 #define CONFIG_SYS_HWINFO_SIZE          0x00000060      /* size   of HW Info block */
 380 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 381
 382 /*-----------------------------------------------------------------------
 383  * NAND-FLASH stuff
 384  *-----------------------------------------------------------------------
 385  */
 386 #if defined(CONFIG_CMD_NAND)
 387
 388 #define CONFIG_SYS_NAND_CS_DIST         0x80
 389 #define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS       0x20
 390 #define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS      0x40
 391
 392 #define CONFIG_SYS_NAND_BR      ((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK)   |\
 393                          BRx_PS_8                       |\
 394                          BRx_MS_UPMB                    |\
 395                          BRx_V)
 396
 397 #define CONFIG_SYS_NAND_OR      (MEG_TO_AM(CONFIG_SYS_NAND_SIZE)        |\
 398                          ORxU_BI                        |\
 399                          ORxU_EHTR_8IDLE)
 400
 401 #define CONFIG_SYS_NAND_SIZE    1
 402 #define CONFIG_SYS_NAND0_BASE 0x50000000
 403 #define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
 404 #define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
 405 #define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
 406
 407 #define CONFIG_SYS_MAX_NAND_DEVICE     4       /* Max number of NAND devices           */
 408
 409 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
 410                              CONFIG_SYS_NAND1_BASE, \
 411                              CONFIG_SYS_NAND2_BASE, \
 412                              CONFIG_SYS_NAND3_BASE, \
 413                            }
 414
 415 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
 416 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
 417 #define WRITE_NAND_UPM(d, adr, off) do \
 418 { \
 419         volatile unsigned char *addr = (unsigned char *) (adr + off); \
 420         WRITE_NAND(d, addr); \
 421 } while(0)
 422
 423 #endif /* CONFIG_CMD_NAND */
 424
 425 #define CONFIG_PCI
 426 #ifdef CONFIG_PCI
 427 #define CONFIG_PCI_INDIRECT_BRIDGE
 428 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
 429 #define CONFIG_PCI_PNP
 430 #define CONFIG_EEPRO100
 431 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 432 #define CONFIG_PCI_SCAN_SHOW
 433 #endif
 434
 435 /*-----------------------------------------------------------------------
 436  * Hard Reset Configuration Words
 437  *
 438  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 439  * defines for the various registers affected by the HRCW e.g. changing
 440  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 441  */
 442 #if 0
 443 #define __HRCW__ALL__           (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 444
 445 #  define CONFIG_SYS_HRCW_MASTER        (__HRCW__ALL__ | HRCW_MODCK_H0111)
 446 #else
 447 #define CONFIG_SYS_HRCW_MASTER  (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
 448 #endif
 449
 450 /* no slaves so just fill with zeros */
 451 #define CONFIG_SYS_HRCW_SLAVE1          0
 452 #define CONFIG_SYS_HRCW_SLAVE2          0
 453 #define CONFIG_SYS_HRCW_SLAVE3          0
 454 #define CONFIG_SYS_HRCW_SLAVE4          0
 455 #define CONFIG_SYS_HRCW_SLAVE5          0
 456 #define CONFIG_SYS_HRCW_SLAVE6          0
 457 #define CONFIG_SYS_HRCW_SLAVE7          0
 458
 459 /*-----------------------------------------------------------------------
 460  * Internal Memory Mapped Register
 461  */
 462 #define CONFIG_SYS_IMMR         0xFFF00000
 463
 464 /*-----------------------------------------------------------------------
 465  * Definitions for initial stack pointer and data area (in DPRAM)
 466  */
 467 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 468 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in DPRAM    */
 469 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 470 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 471
 472 /*-----------------------------------------------------------------------
 473  * Start addresses for the final memory configuration
 474  * (Set up by the startup code)
 475  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 476  */
 477 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 478 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_FLASH0_BASE
 479 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 480 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor */
 481 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 482
 483 /*-----------------------------------------------------------------------
 484  * Cache Configuration
 485  */
 486 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 487 #if defined(CONFIG_CMD_KGDB)
 488 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 489 #endif
 490
 491 /*-----------------------------------------------------------------------
 492  * HIDx - Hardware Implementation-dependent Registers                    2-11
 493  *-----------------------------------------------------------------------
 494  * HID0 also contains cache control - initially enable both caches and
 495  * invalidate contents, then the final state leaves only the instruction
 496  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 497  * but Soft reset does not.
 498  *
 499  * HID1 has only read-only information - nothing to set.
 500  */
 501 #define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 502                                 HID0_IFEM|HID0_ABE)
 503 #define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 504 #define CONFIG_SYS_HID2        0
 505
 506 /*-----------------------------------------------------------------------
 507  * RMR - Reset Mode Register                                     5-5
 508  *-----------------------------------------------------------------------
 509  * turn on Checkstop Reset Enable
 510  */
 511 #define CONFIG_SYS_RMR         RMR_CSRE
 512
 513 /*-----------------------------------------------------------------------
 514  * BCR - Bus Configuration                                       4-25
 515  *-----------------------------------------------------------------------
 516  */
 517 #define CONFIG_SYS_BCR_60x         (BCR_EBM|BCR_NPQM0|BCR_NPQM2)        /* 60x mode  */
 518 #define BCR_APD01       0x10000000
 519 #define CONFIG_SYS_BCR_SINGLE           (BCR_APD01|BCR_ETM)     /* 8260 mode */
 520
 521 /*-----------------------------------------------------------------------
 522  * SIUMCR - SIU Module Configuration                             4-31
 523  *-----------------------------------------------------------------------
 524  */
 525 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
 526 #define CONFIG_SYS_SIUMCR_LOW           (SIUMCR_DPPC00)
 527 #define CONFIG_SYS_SIUMCR_HIGH          (SIUMCR_DPPC00 | SIUMCR_ABE)
 528 #else
 529 #define CONFIG_SYS_SIUMCR               (SIUMCR_DPPC00)
 530 #endif
 531
 532 /*-----------------------------------------------------------------------
 533  * SYPCR - System Protection Control                             4-35
 534  * SYPCR can only be written once after reset!
 535  *-----------------------------------------------------------------------
 536  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 537  */
 538 #if defined(CONFIG_WATCHDOG)
 539 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 540                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 541 #else
 542 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 543                          SYPCR_SWRI|SYPCR_SWP)
 544 #endif /* CONFIG_WATCHDOG */
 545
 546 /*-----------------------------------------------------------------------
 547  * TMCNTSC - Time Counter Status and Control                     4-40
 548  *-----------------------------------------------------------------------
 549  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 550  * and enable Time Counter
 551  */
 552 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 553
 554 /*-----------------------------------------------------------------------
 555  * PISCR - Periodic Interrupt Status and Control                 4-42
 556  *-----------------------------------------------------------------------
 557  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 558  * Periodic timer
 559  */
 560 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 561
 562 /*-----------------------------------------------------------------------
 563  * SCCR - System Clock Control                                   9-8
 564  *-----------------------------------------------------------------------
 565  * Ensure DFBRG is Divide by 16
 566  */
 567 #define CONFIG_SYS_SCCR        SCCR_DFBRG01
 568
 569 /*-----------------------------------------------------------------------
 570  * RCCR - RISC Controller Configuration                         13-7
 571  *-----------------------------------------------------------------------
 572  */
 573 #define CONFIG_SYS_RCCR        0
 574
 575 /*
 576  * Init Memory Controller:
 577  *
 578  * Bank Bus     Machine PortSz  Device
 579  * ---- ---     ------- ------  ------
 580  *  0   60x     GPCM    32 bit  FLASH
 581  *  1   60x     SDRAM   64 bit  SDRAM
 582  *  2   60x     UPMB     8 bit  NAND
 583  *  3   60x     UPMC     8 bit  CAN
 584  *
 585  */
 586
 587 /* Initialize SDRAM
 588          */
 589 #undef CONFIG_SYS_INIT_LOCAL_SDRAM              /* No SDRAM on Local Bus */
 590
 591 #define SDRAM_MAX_SIZE  0x20000000      /* max. 512 MB          */
 592
 593 /* Minimum mask to separate preliminary
 594  * address ranges for CS[0:2]
 595  */
 596 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (512<<20)       /* less than 512 MB */
 597
 598 #define CONFIG_SYS_MPTPR       0x4000
 599
 600 /*-----------------------------------------------------------------------------
 601  * Address for Mode Register Set (MRS) command
 602  *-----------------------------------------------------------------------------
 603  * In fact, the address is rather configuration data presented to the SDRAM on
 604  * its address lines. Because the address lines may be mux'ed externally either
 605  * for 8 column or 9 column devices, some bits appear twice in the 8260's
 606  * address:
 607  *
 608  * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
 609  * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
 610  *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
 611  *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
 612  *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
 613  *-----------------------------------------------------------------------------
 614  */
 615 #define CONFIG_SYS_MRS_OFFS     0x00000110
 616
 617 /* Bank 0 - FLASH
 618  */
 619 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 620                          BRx_PS_32                      |\
 621                          BRx_MS_GPCM_P                  |\
 622                          BRx_V)
 623
 624 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 625                          ORxG_CSNT                      |\
 626                          ORxG_ACS_DIV4                  |\
 627                          ORxG_SCY_8_CLK                 |\
 628                          ORxG_TRLX)
 629
 630 /* SDRAM on TQM8272 can have either 8 or 9 columns.
 631  * The number affects configuration values.
 632  */
 633
 634 /* Bank 1 - 60x bus SDRAM
 635  */
 636 #define CONFIG_SYS_PSRT        0x20     /* Low Value */
 637 /* #define CONFIG_SYS_PSRT        0x10   Fast Value */
 638 #define CONFIG_SYS_LSRT        0x20     /* Local Bus */
 639 #ifndef CONFIG_SYS_RAMBOOT
 640 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 641                          BRx_PS_64                      |\
 642                          BRx_MS_SDRAM_P                 |\
 643                          BRx_V)
 644
 645 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1_8COL
 646
 647 /* SDRAM initialization values for 8-column chips
 648  */
 649 #define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 650                          ORxS_BPD_4                     |\
 651                          ORxS_ROWST_PBI1_A7             |\
 652                          ORxS_NUMR_12)
 653
 654 #define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
 655                          PSDMR_SDAM_A15_IS_A5           |\
 656                          PSDMR_BSMA_A12_A14             |\
 657                          PSDMR_SDA10_PBI1_A8            |\
 658                          PSDMR_RFRC_7_CLK               |\
 659                          PSDMR_PRETOACT_2W              |\
 660                          PSDMR_ACTTORW_2W               |\
 661                          PSDMR_LDOTOPRE_1C              |\
 662                          PSDMR_WRC_2C                   |\
 663                          PSDMR_EAMUX                    |\
 664                          PSDMR_BUFCMD                   |\
 665                          PSDMR_CL_2)
 666
 667
 668 /* SDRAM initialization values for 9-column chips
 669  */
 670 #define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 671                          ORxS_BPD_4                     |\
 672                          ORxS_ROWST_PBI1_A5             |\
 673                          ORxS_NUMR_13)
 674
 675 #define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
 676                          PSDMR_SDAM_A16_IS_A5           |\
 677                          PSDMR_BSMA_A12_A14             |\
 678                          PSDMR_SDA10_PBI1_A7            |\
 679                          PSDMR_RFRC_7_CLK               |\
 680                          PSDMR_PRETOACT_2W              |\
 681                          PSDMR_ACTTORW_2W               |\
 682                          PSDMR_LDOTOPRE_1C              |\
 683                          PSDMR_WRC_2C                   |\
 684                          PSDMR_EAMUX                    |\
 685                          PSDMR_BUFCMD                   |\
 686                          PSDMR_CL_2)
 687
 688 #define CONFIG_SYS_OR1_10COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 689                          ORxS_BPD_4                     |\
 690                          ORxS_ROWST_PBI1_A4             |\
 691                          ORxS_NUMR_13)
 692
 693 #define CONFIG_SYS_PSDMR_10COL  (PSDMR_PBI                      |\
 694                          PSDMR_SDAM_A17_IS_A5           |\
 695                          PSDMR_BSMA_A12_A14             |\
 696                          PSDMR_SDA10_PBI1_A4            |\
 697                          PSDMR_RFRC_6_CLK               |\
 698                          PSDMR_PRETOACT_2W              |\
 699                          PSDMR_ACTTORW_2W               |\
 700                          PSDMR_LDOTOPRE_1C              |\
 701                          PSDMR_WRC_2C                   |\
 702                          PSDMR_EAMUX                    |\
 703                          PSDMR_BUFCMD                   |\
 704                          PSDMR_CL_2)
 705
 706 #define PSDMR_RFRC_66MHZ_SINGLE         0x00028000  /* PSDMR[RFRC] at 66 MHz single mode */
 707 #define PSDMR_RFRC_100MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 100 MHz single mode */
 708 #define PSDMR_RFRC_133MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 133 MHz single mode */
 709 #define PSDMR_RFRC_66MHZ_60X            0x00030000  /* PSDMR[RFRC] at 66 MHz 60x mode */
 710 #define PSDMR_RFRC_100MHZ_60X           0x00028000  /* PSDMR[RFRC] at 100 MHz 60x mode */
 711 #define PSDMR_RFRC_DEFAULT              PSDMR_RFRC_133MHZ_SINGLE  /* PSDMR[RFRC] default value */
 712
 713 #define PSDMR_PRETOACT_66MHZ_SINGLE     0x00002000  /* PSDMR[PRETOACT] at 66 MHz single mode */
 714 #define PSDMR_PRETOACT_100MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 100 MHz single mode */
 715 #define PSDMR_PRETOACT_133MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 133 MHz single mode */
 716 #define PSDMR_PRETOACT_66MHZ_60X        0x00001000  /* PSDMR[PRETOACT] at 66 MHz 60x mode */
 717 #define PSDMR_PRETOACT_100MHZ_60X       0x00001000  /* PSDMR[PRETOACT] at 100 MHz 60x mode */
 718 #define PSDMR_PRETOACT_DEFAULT          PSDMR_PRETOACT_133MHZ_SINGLE  /* PSDMR[PRETOACT] default value */
 719
 720 #define PSDMR_WRC_66MHZ_SINGLE          0x00000020  /* PSDMR[WRC] at 66 MHz single mode */
 721 #define PSDMR_WRC_100MHZ_SINGLE         0x00000020  /* PSDMR[WRC] at 100 MHz single mode */
 722 #define PSDMR_WRC_133MHZ_SINGLE         0x00000010  /* PSDMR[WRC] at 133 MHz single mode */
 723 #define PSDMR_WRC_66MHZ_60X             0x00000010  /* PSDMR[WRC] at 66 MHz 60x mode */
 724 #define PSDMR_WRC_100MHZ_60X            0x00000010  /* PSDMR[WRC] at 100 MHz 60x mode */
 725 #define PSDMR_WRC_DEFAULT               PSDMR_WRC_133MHZ_SINGLE  /* PSDMR[WRC] default value */
 726
 727 #define PSDMR_BUFCMD_66MHZ_SINGLE       0x00000000  /* PSDMR[BUFCMD] at 66 MHz single mode */
 728 #define PSDMR_BUFCMD_100MHZ_SINGLE      0x00000000  /* PSDMR[BUFCMD] at 100 MHz single mode */
 729 #define PSDMR_BUFCMD_133MHZ_SINGLE      0x00000004  /* PSDMR[BUFCMD] at 133 MHz single mode */
 730 #define PSDMR_BUFCMD_66MHZ_60X          0x00000000  /* PSDMR[BUFCMD] at 66 MHz 60x mode */
 731 #define PSDMR_BUFCMD_100MHZ_60X         0x00000000  /* PSDMR[BUFCMD] at 100 MHz 60x mode */
 732 #define PSDMR_BUFCMD_DEFAULT            PSDMR_BUFCMD_133MHZ_SINGLE  /* PSDMR[BUFCMD] default value */
 733
 734 #endif /* CONFIG_SYS_RAMBOOT */
 735
 736 #endif  /* __CONFIG_H */