include/configs/TQM8272.h

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC8272_FAMILY   1
  21 #define CONFIG_TQM8272          1
  22
  23 #define CONFIG_SYS_TEXT_BASE    0x40000000
  24
  25 #define CONFIG_GET_CPU_STR_F    1       /* Get the CPU ID STR */
  26 #define CONFIG_BOARD_GET_CPU_CLK_F      1 /* Get the CLKIN from board fct */
  27
  28 #define STK82xx_150             1       /* on a STK82xx.150 */
  29
  30 #define CONFIG_CPM2             1       /* Has a CPM2 */
  31
  32 #define CONFIG_82xx_CONS_SMC1   1       /* console on SMC1              */
  33
  34 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  35
  36 #define CONFIG_BOARD_EARLY_INIT_R       1
  37
  38 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  39 #define CONFIG_BAUDRATE         230400
  40 #else
  41 #define CONFIG_BAUDRATE         115200
  42 #endif
  43
  44 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  45
  46 #undef  CONFIG_BOOTARGS
  47
  48 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  49         "netdev=eth0\0"                                                 \
  50         "consdev=ttyCPM0\0"                                             \
  51         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  52                 "nfsroot=${serverip}:${rootpath}\0"                     \
  53         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  54         "hostname=tqm8272\0"                                            \
  55         "addip=setenv bootargs ${bootargs} "                            \
  56                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  57                 ":${hostname}:${netdev}:off panic=1\0"                  \
  58         "addcons=setenv bootargs ${bootargs} "                          \
  59                 "console=$(consdev),$(baudrate)\0"                      \
  60         "flash_nfs=run nfsargs addip addcons;"                          \
  61                 "bootm ${kernel_addr}\0"                                \
  62         "flash_self=run ramargs addip addcons;"                         \
  63                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  64         "net_nfs=tftp 300000 ${bootfile};"                              \
  65                 "run nfsargs addip addcons;bootm\0"                     \
  66         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
  67         "bootfile=/tftpboot/tqm8272/uImage\0"                           \
  68         "kernel_addr=40080000\0"                                        \
  69         "ramdisk_addr=40100000\0"                                       \
  70         "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0"               \
  71         "update=protect off 40000000 4003ffff;era 40000000 4003ffff;"   \
  72                 "cp.b 300000 40000000 40000;"                           \
  73                 "setenv filesize;saveenv\0"                             \
  74         "cphwib=cp.b 4003fc00 33fc00 400\0"                             \
  75         "upd=run load cphwib update\0"                                  \
  76         ""
  77 #define CONFIG_BOOTCOMMAND      "run flash_self"
  78
  79 #define CONFIG_I2C      1
  80
  81 #if CONFIG_I2C
  82 /* enable I2C and select the hardware/software driver */
  83 #define CONFIG_SYS_I2C
  84 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
  85 #define CONFIG_SYS_I2C_SOFT_SPEED       400000
  86 #define CONFIG_SYS_I2C_SOFT_SLAVE       0x7F
  87 /*
  88  * Software (bit-bang) I2C driver configuration
  89  */
  90 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
  91 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
  92 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
  93 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
  94 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
  95                         else    iop->pdat &= ~0x00010000
  96 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
  97                         else    iop->pdat &= ~0x00020000
  98 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
  99
 100 #define CONFIG_I2C_X
 101
 102 /* EEPROM */
 103 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 104 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 105 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 106 #define CONFIG_SYS_I2C_MULTI_EEPROMS            1       /* more than one eeprom */
 107
 108 /* I2C RTC */
 109 #define CONFIG_RTC_DS1337               /* Use ds1337 rtc via i2c       */
 110 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68              */
 111
 112 /* I2C SYSMON (LM75) */
 113 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 114 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 115 #define CONFIG_SYS_DTT_MAX_TEMP 70
 116 #define CONFIG_SYS_DTT_LOW_TEMP -30
 117 #define CONFIG_SYS_DTT_HYSTERESIS       3
 118
 119 #else
 120 #undef CONFIG_SYS_I2C
 121 #undef CONFIG_HARD_I2C
 122 #undef CONFIG_SYS_I2C_SOFT
 123 #endif
 124
 125 /*
 126  * select serial console configuration
 127  *
 128  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 129  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 130  * for SCC).
 131  *
 132  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 133  * defined elsewhere (for example, on the cogent platform, there are serial
 134  * ports on the motherboard which are used for the serial console - see
 135  * cogent/cma101/serial.[ch]).
 136  */
 137 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
 138 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 139 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
 140 #ifdef CONFIG_82xx_CONS_SMC1
 141 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
 142 #endif
 143 #ifdef CONFIG_82xx_CONS_SMC2
 144 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
 145 #endif
 146
 147 #undef  CONFIG_CONS_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
 148 #define CONFIG_CONS_EXTC_RATE   3686400 /* SMC/SCC ext clk rate in Hz */
 149 #define CONFIG_CONS_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9 */
 150
 151 /*
 152  * select ethernet configuration
 153  *
 154  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 155  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 156  * for FCC)
 157  *
 158  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 159  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 160  *
 161  * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
 162  * X.29 connector, and FCC2 is hardwired to the X.1 connector)
 163  */
 164 #define CONFIG_SYS_FCC_ETHERNET
 165
 166 #if defined(CONFIG_SYS_FCC_ETHERNET)
 167 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 168 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 169 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 170 #define CONFIG_ETHER_INDEX    2         /* which SCC/FCC channel for ethernet */
 171 #else
 172 #define CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 173 #undef  CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 174 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 175 #define CONFIG_ETHER_INDEX    1         /* which SCC/FCC channel for ethernet */
 176 #endif
 177
 178 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
 179
 180 /*
 181  *  - RX clk is CLK11
 182  *  - TX clk is CLK12
 183  */
 184 # define CONFIG_SYS_CMXSCR_VALUE        (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
 185
 186 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 187
 188 /*
 189  * - Rx-CLK is CLK13
 190  * - Tx-CLK is CLK14
 191  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 192  * - Enable Full Duplex in FSMR
 193  */
 194 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 195 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 196 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 197 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
 198
 199 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 200
 201 #define CONFIG_MII                      /* MII PHY management           */
 202 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 203 /*
 204  * GPIO pins used for bit-banged MII communications
 205  */
 206 #define MDIO_PORT       2               /* Port C */
 207 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 208                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 209 #define MDC_DECLARE     MDIO_DECLARE
 210
 211 #if STK82xx_150
 212 #define CONFIG_SYS_MDIO_PIN     0x00008000      /* PC16 */
 213 #define CONFIG_SYS_MDC_PIN      0x00004000      /* PC17 */
 214 #endif
 215
 216 #if STK82xx_100
 217 #define CONFIG_SYS_MDIO_PIN     0x00000002      /* PC30 */
 218 #define CONFIG_SYS_MDC_PIN      0x00000001      /* PC31 */
 219 #endif
 220
 221 #if 1
 222 #define MDIO_ACTIVE     (iop->pdir |=  CONFIG_SYS_MDIO_PIN)
 223 #define MDIO_TRISTATE   (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
 224 #define MDIO_READ       ((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 225
 226 #define MDIO(bit)       if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
 227                         else    iop->pdat &= ~CONFIG_SYS_MDIO_PIN
 228
 229 #define MDC(bit)        if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
 230                         else    iop->pdat &= ~CONFIG_SYS_MDC_PIN
 231 #else
 232 #define MDIO_ACTIVE     ({unsigned long tmp; tmp = iop->pdir; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
 233 #define MDIO_TRISTATE   ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
 234 #define MDIO_READ       ((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 235
 236 #define MDIO(bit)       if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\
 237                         else    {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}
 238
 239 #define MDC(bit)        if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\
 240                         else    {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}
 241 #endif
 242
 243 #define MIIDELAY        udelay(1)
 244
 245
 246 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 247 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
 248
 249 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 250 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 251
 252 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 253
 254 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 255
 256 /*
 257  * BOOTP options
 258  */
 259 #define CONFIG_BOOTP_SUBNETMASK
 260 #define CONFIG_BOOTP_GATEWAY
 261 #define CONFIG_BOOTP_HOSTNAME
 262 #define CONFIG_BOOTP_BOOTPATH
 263 #define CONFIG_BOOTP_BOOTFILESIZE
 264
 265
 266 /*
 267  * Command line configuration.
 268  */
 269 #include <config_cmd_default.h>
 270
 271 #define CONFIG_CMD_I2C
 272 #define CONFIG_CMD_DHCP
 273 #define CONFIG_CMD_MII
 274 #define CONFIG_CMD_NAND
 275 #define CONFIG_CMD_NFS
 276 #define CONFIG_CMD_PCI
 277 #define CONFIG_CMD_PING
 278 #define CONFIG_CMD_SNTP
 279
 280 #if CONFIG_I2C
 281     #define CONFIG_CMD_I2C
 282     #define CONFIG_CMD_DATE
 283     #define CONFIG_CMD_DTT
 284     #define CONFIG_CMD_EEPROM
 285 #endif
 286
 287
 288 /*
 289  * Miscellaneous configurable options
 290  */
 291 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 292
 293 #if 0
 294 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 295 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 296 #endif
 297
 298 #if defined(CONFIG_CMD_KGDB)
 299 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 300 #else
 301 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 302 #endif
 303 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 304 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 305 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 306
 307 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 308 #define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
 309
 310 #define CONFIG_SYS_LOAD_ADDR    0x300000        /* default load address */
 311
 312 #define CONFIG_SYS_RESET_ADDRESS 0x40000104     /* "bad" address                */
 313
 314 /*
 315  * For booting Linux, the board info and command line data
 316  * have to be in the first 8 MB of memory, since this is
 317  * the maximum mapped by the Linux kernel during initialization.
 318  */
 319 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 320
 321 /*-----------------------------------------------------------------------
 322  * CAN stuff
 323  *-----------------------------------------------------------------------
 324  */
 325 #define CONFIG_SYS_CAN_BASE     0x51000000
 326 #define CONFIG_SYS_CAN_SIZE     1
 327 #define CONFIG_SYS_CAN_BR       ((CONFIG_SYS_CAN_BASE & BRx_BA_MSK)     |\
 328                          BRx_PS_8                       |\
 329                          BRx_MS_UPMC                    |\
 330                          BRx_V)
 331
 332 #define CONFIG_SYS_CAN_OR       (MEG_TO_AM(CONFIG_SYS_CAN_SIZE) |\
 333                          ORxU_BI)
 334
 335
 336 /* What should the base address of the main FLASH be and how big is
 337  * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk
 338  * The main FLASH is whichever is connected to *CS0.
 339  */
 340 #define CONFIG_SYS_FLASH0_BASE 0x40000000
 341 #define CONFIG_SYS_FLASH0_SIZE 32       /* 32 MB */
 342
 343 /* Flash bank size (for preliminary settings)
 344  */
 345 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 346
 347 /*-----------------------------------------------------------------------
 348  * FLASH organization
 349  */
 350 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 351 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 352
 353 #define CONFIG_SYS_FLASH_CFI                            /* flash is CFI compat. */
 354 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver*/
 355 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector   */
 356 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash*/
 357
 358 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 359 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 360
 361 #define CONFIG_SYS_UPDATE_FLASH_SIZE
 362
 363 #define CONFIG_ENV_IS_IN_FLASH  1
 364 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x40000)
 365 #define CONFIG_ENV_SIZE         0x20000
 366 #define CONFIG_ENV_SECT_SIZE    0x20000
 367 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
 368 #define CONFIG_ENV_SIZE_REDUND  0x20000
 369
 370 /* Where is the Hardwareinformation Block (from Monitor Sources) */
 371 #define MON_RES_LENGTH          (0x0003FC00)
 372 #define HWIB_INFO_START_ADDR    (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH)
 373 #define HWIB_INFO_LEN           512
 374 #define CIB_INFO_START_ADDR     (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
 375 #define CIB_INFO_LEN            512
 376
 377 #define CONFIG_SYS_HWINFO_OFFSET        0x3fc00 /* offset of HW Info block */
 378 #define CONFIG_SYS_HWINFO_SIZE          0x00000060      /* size   of HW Info block */
 379 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 380
 381 /*-----------------------------------------------------------------------
 382  * NAND-FLASH stuff
 383  *-----------------------------------------------------------------------
 384  */
 385 #if defined(CONFIG_CMD_NAND)
 386
 387 #define CONFIG_SYS_NAND_CS_DIST         0x80
 388 #define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS       0x20
 389 #define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS      0x40
 390
 391 #define CONFIG_SYS_NAND_BR      ((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK)   |\
 392                          BRx_PS_8                       |\
 393                          BRx_MS_UPMB                    |\
 394                          BRx_V)
 395
 396 #define CONFIG_SYS_NAND_OR      (MEG_TO_AM(CONFIG_SYS_NAND_SIZE)        |\
 397                          ORxU_BI                        |\
 398                          ORxU_EHTR_8IDLE)
 399
 400 #define CONFIG_SYS_NAND_SIZE    1
 401 #define CONFIG_SYS_NAND0_BASE 0x50000000
 402 #define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
 403 #define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
 404 #define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
 405
 406 #define CONFIG_SYS_MAX_NAND_DEVICE     4       /* Max number of NAND devices           */
 407
 408 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
 409                              CONFIG_SYS_NAND1_BASE, \
 410                              CONFIG_SYS_NAND2_BASE, \
 411                              CONFIG_SYS_NAND3_BASE, \
 412                            }
 413
 414 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
 415 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
 416 #define WRITE_NAND_UPM(d, adr, off) do \
 417 { \
 418         volatile unsigned char *addr = (unsigned char *) (adr + off); \
 419         WRITE_NAND(d, addr); \
 420 } while(0)
 421
 422 #endif /* CONFIG_CMD_NAND */
 423
 424 #define CONFIG_PCI
 425 #ifdef CONFIG_PCI
 426 #define CONFIG_PCI_INDIRECT_BRIDGE
 427 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
 428 #define CONFIG_PCI_PNP
 429 #define CONFIG_EEPRO100
 430 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 431 #define CONFIG_PCI_SCAN_SHOW
 432 #endif
 433
 434 /*-----------------------------------------------------------------------
 435  * Hard Reset Configuration Words
 436  *
 437  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 438  * defines for the various registers affected by the HRCW e.g. changing
 439  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 440  */
 441 #if 0
 442 #define __HRCW__ALL__           (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 443
 444 #  define CONFIG_SYS_HRCW_MASTER        (__HRCW__ALL__ | HRCW_MODCK_H0111)
 445 #else
 446 #define CONFIG_SYS_HRCW_MASTER  (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
 447 #endif
 448
 449 /* no slaves so just fill with zeros */
 450 #define CONFIG_SYS_HRCW_SLAVE1          0
 451 #define CONFIG_SYS_HRCW_SLAVE2          0
 452 #define CONFIG_SYS_HRCW_SLAVE3          0
 453 #define CONFIG_SYS_HRCW_SLAVE4          0
 454 #define CONFIG_SYS_HRCW_SLAVE5          0
 455 #define CONFIG_SYS_HRCW_SLAVE6          0
 456 #define CONFIG_SYS_HRCW_SLAVE7          0
 457
 458 /*-----------------------------------------------------------------------
 459  * Internal Memory Mapped Register
 460  */
 461 #define CONFIG_SYS_IMMR         0xFFF00000
 462
 463 /*-----------------------------------------------------------------------
 464  * Definitions for initial stack pointer and data area (in DPRAM)
 465  */
 466 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 467 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in DPRAM    */
 468 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 469 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 470
 471 /*-----------------------------------------------------------------------
 472  * Start addresses for the final memory configuration
 473  * (Set up by the startup code)
 474  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 475  */
 476 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 477 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_FLASH0_BASE
 478 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 479 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor */
 480 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 481
 482 /*-----------------------------------------------------------------------
 483  * Cache Configuration
 484  */
 485 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 486 #if defined(CONFIG_CMD_KGDB)
 487 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 488 #endif
 489
 490 /*-----------------------------------------------------------------------
 491  * HIDx - Hardware Implementation-dependent Registers                    2-11
 492  *-----------------------------------------------------------------------
 493  * HID0 also contains cache control - initially enable both caches and
 494  * invalidate contents, then the final state leaves only the instruction
 495  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 496  * but Soft reset does not.
 497  *
 498  * HID1 has only read-only information - nothing to set.
 499  */
 500 #define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 501                                 HID0_IFEM|HID0_ABE)
 502 #define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 503 #define CONFIG_SYS_HID2        0
 504
 505 /*-----------------------------------------------------------------------
 506  * RMR - Reset Mode Register                                     5-5
 507  *-----------------------------------------------------------------------
 508  * turn on Checkstop Reset Enable
 509  */
 510 #define CONFIG_SYS_RMR         RMR_CSRE
 511
 512 /*-----------------------------------------------------------------------
 513  * BCR - Bus Configuration                                       4-25
 514  *-----------------------------------------------------------------------
 515  */
 516 #define CONFIG_SYS_BCR_60x         (BCR_EBM|BCR_NPQM0|BCR_NPQM2)        /* 60x mode  */
 517 #define BCR_APD01       0x10000000
 518 #define CONFIG_SYS_BCR_SINGLE           (BCR_APD01|BCR_ETM)     /* 8260 mode */
 519
 520 /*-----------------------------------------------------------------------
 521  * SIUMCR - SIU Module Configuration                             4-31
 522  *-----------------------------------------------------------------------
 523  */
 524 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
 525 #define CONFIG_SYS_SIUMCR_LOW           (SIUMCR_DPPC00)
 526 #define CONFIG_SYS_SIUMCR_HIGH          (SIUMCR_DPPC00 | SIUMCR_ABE)
 527 #else
 528 #define CONFIG_SYS_SIUMCR               (SIUMCR_DPPC00)
 529 #endif
 530
 531 /*-----------------------------------------------------------------------
 532  * SYPCR - System Protection Control                             4-35
 533  * SYPCR can only be written once after reset!
 534  *-----------------------------------------------------------------------
 535  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 536  */
 537 #if defined(CONFIG_WATCHDOG)
 538 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 539                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 540 #else
 541 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 542                          SYPCR_SWRI|SYPCR_SWP)
 543 #endif /* CONFIG_WATCHDOG */
 544
 545 /*-----------------------------------------------------------------------
 546  * TMCNTSC - Time Counter Status and Control                     4-40
 547  *-----------------------------------------------------------------------
 548  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 549  * and enable Time Counter
 550  */
 551 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 552
 553 /*-----------------------------------------------------------------------
 554  * PISCR - Periodic Interrupt Status and Control                 4-42
 555  *-----------------------------------------------------------------------
 556  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 557  * Periodic timer
 558  */
 559 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 560
 561 /*-----------------------------------------------------------------------
 562  * SCCR - System Clock Control                                   9-8
 563  *-----------------------------------------------------------------------
 564  * Ensure DFBRG is Divide by 16
 565  */
 566 #define CONFIG_SYS_SCCR        SCCR_DFBRG01
 567
 568 /*-----------------------------------------------------------------------
 569  * RCCR - RISC Controller Configuration                         13-7
 570  *-----------------------------------------------------------------------
 571  */
 572 #define CONFIG_SYS_RCCR        0
 573
 574 /*
 575  * Init Memory Controller:
 576  *
 577  * Bank Bus     Machine PortSz  Device
 578  * ---- ---     ------- ------  ------
 579  *  0   60x     GPCM    32 bit  FLASH
 580  *  1   60x     SDRAM   64 bit  SDRAM
 581  *  2   60x     UPMB     8 bit  NAND
 582  *  3   60x     UPMC     8 bit  CAN
 583  *
 584  */
 585
 586 /* Initialize SDRAM
 587          */
 588 #undef CONFIG_SYS_INIT_LOCAL_SDRAM              /* No SDRAM on Local Bus */
 589
 590 #define SDRAM_MAX_SIZE  0x20000000      /* max. 512 MB          */
 591
 592 /* Minimum mask to separate preliminary
 593  * address ranges for CS[0:2]
 594  */
 595 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (512<<20)       /* less than 512 MB */
 596
 597 #define CONFIG_SYS_MPTPR       0x4000
 598
 599 /*-----------------------------------------------------------------------------
 600  * Address for Mode Register Set (MRS) command
 601  *-----------------------------------------------------------------------------
 602  * In fact, the address is rather configuration data presented to the SDRAM on
 603  * its address lines. Because the address lines may be mux'ed externally either
 604  * for 8 column or 9 column devices, some bits appear twice in the 8260's
 605  * address:
 606  *
 607  * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
 608  * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
 609  *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
 610  *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
 611  *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
 612  *-----------------------------------------------------------------------------
 613  */
 614 #define CONFIG_SYS_MRS_OFFS     0x00000110
 615
 616 /* Bank 0 - FLASH
 617  */
 618 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 619                          BRx_PS_32                      |\
 620                          BRx_MS_GPCM_P                  |\
 621                          BRx_V)
 622
 623 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 624                          ORxG_CSNT                      |\
 625                          ORxG_ACS_DIV4                  |\
 626                          ORxG_SCY_8_CLK                 |\
 627                          ORxG_TRLX)
 628
 629 /* SDRAM on TQM8272 can have either 8 or 9 columns.
 630  * The number affects configuration values.
 631  */
 632
 633 /* Bank 1 - 60x bus SDRAM
 634  */
 635 #define CONFIG_SYS_PSRT        0x20     /* Low Value */
 636 /* #define CONFIG_SYS_PSRT        0x10   Fast Value */
 637 #define CONFIG_SYS_LSRT        0x20     /* Local Bus */
 638 #ifndef CONFIG_SYS_RAMBOOT
 639 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 640                          BRx_PS_64                      |\
 641                          BRx_MS_SDRAM_P                 |\
 642                          BRx_V)
 643
 644 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1_8COL
 645
 646 /* SDRAM initialization values for 8-column chips
 647  */
 648 #define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 649                          ORxS_BPD_4                     |\
 650                          ORxS_ROWST_PBI1_A7             |\
 651                          ORxS_NUMR_12)
 652
 653 #define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
 654                          PSDMR_SDAM_A15_IS_A5           |\
 655                          PSDMR_BSMA_A12_A14             |\
 656                          PSDMR_SDA10_PBI1_A8            |\
 657                          PSDMR_RFRC_7_CLK               |\
 658                          PSDMR_PRETOACT_2W              |\
 659                          PSDMR_ACTTORW_2W               |\
 660                          PSDMR_LDOTOPRE_1C              |\
 661                          PSDMR_WRC_2C                   |\
 662                          PSDMR_EAMUX                    |\
 663                          PSDMR_BUFCMD                   |\
 664                          PSDMR_CL_2)
 665
 666
 667 /* SDRAM initialization values for 9-column chips
 668  */
 669 #define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 670                          ORxS_BPD_4                     |\
 671                          ORxS_ROWST_PBI1_A5             |\
 672                          ORxS_NUMR_13)
 673
 674 #define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
 675                          PSDMR_SDAM_A16_IS_A5           |\
 676                          PSDMR_BSMA_A12_A14             |\
 677                          PSDMR_SDA10_PBI1_A7            |\
 678                          PSDMR_RFRC_7_CLK               |\
 679                          PSDMR_PRETOACT_2W              |\
 680                          PSDMR_ACTTORW_2W               |\
 681                          PSDMR_LDOTOPRE_1C              |\
 682                          PSDMR_WRC_2C                   |\
 683                          PSDMR_EAMUX                    |\
 684                          PSDMR_BUFCMD                   |\
 685                          PSDMR_CL_2)
 686
 687 #define CONFIG_SYS_OR1_10COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 688                          ORxS_BPD_4                     |\
 689                          ORxS_ROWST_PBI1_A4             |\
 690                          ORxS_NUMR_13)
 691
 692 #define CONFIG_SYS_PSDMR_10COL  (PSDMR_PBI                      |\
 693                          PSDMR_SDAM_A17_IS_A5           |\
 694                          PSDMR_BSMA_A12_A14             |\
 695                          PSDMR_SDA10_PBI1_A4            |\
 696                          PSDMR_RFRC_6_CLK               |\
 697                          PSDMR_PRETOACT_2W              |\
 698                          PSDMR_ACTTORW_2W               |\
 699                          PSDMR_LDOTOPRE_1C              |\
 700                          PSDMR_WRC_2C                   |\
 701                          PSDMR_EAMUX                    |\
 702                          PSDMR_BUFCMD                   |\
 703                          PSDMR_CL_2)
 704
 705 #define PSDMR_RFRC_66MHZ_SINGLE         0x00028000  /* PSDMR[RFRC] at 66 MHz single mode */
 706 #define PSDMR_RFRC_100MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 100 MHz single mode */
 707 #define PSDMR_RFRC_133MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 133 MHz single mode */
 708 #define PSDMR_RFRC_66MHZ_60X            0x00030000  /* PSDMR[RFRC] at 66 MHz 60x mode */
 709 #define PSDMR_RFRC_100MHZ_60X           0x00028000  /* PSDMR[RFRC] at 100 MHz 60x mode */
 710 #define PSDMR_RFRC_DEFAULT              PSDMR_RFRC_133MHZ_SINGLE  /* PSDMR[RFRC] default value */
 711
 712 #define PSDMR_PRETOACT_66MHZ_SINGLE     0x00002000  /* PSDMR[PRETOACT] at 66 MHz single mode */
 713 #define PSDMR_PRETOACT_100MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 100 MHz single mode */
 714 #define PSDMR_PRETOACT_133MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 133 MHz single mode */
 715 #define PSDMR_PRETOACT_66MHZ_60X        0x00001000  /* PSDMR[PRETOACT] at 66 MHz 60x mode */
 716 #define PSDMR_PRETOACT_100MHZ_60X       0x00001000  /* PSDMR[PRETOACT] at 100 MHz 60x mode */
 717 #define PSDMR_PRETOACT_DEFAULT          PSDMR_PRETOACT_133MHZ_SINGLE  /* PSDMR[PRETOACT] default value */
 718
 719 #define PSDMR_WRC_66MHZ_SINGLE          0x00000020  /* PSDMR[WRC] at 66 MHz single mode */
 720 #define PSDMR_WRC_100MHZ_SINGLE         0x00000020  /* PSDMR[WRC] at 100 MHz single mode */
 721 #define PSDMR_WRC_133MHZ_SINGLE         0x00000010  /* PSDMR[WRC] at 133 MHz single mode */
 722 #define PSDMR_WRC_66MHZ_60X             0x00000010  /* PSDMR[WRC] at 66 MHz 60x mode */
 723 #define PSDMR_WRC_100MHZ_60X            0x00000010  /* PSDMR[WRC] at 100 MHz 60x mode */
 724 #define PSDMR_WRC_DEFAULT               PSDMR_WRC_133MHZ_SINGLE  /* PSDMR[WRC] default value */
 725
 726 #define PSDMR_BUFCMD_66MHZ_SINGLE       0x00000000  /* PSDMR[BUFCMD] at 66 MHz single mode */
 727 #define PSDMR_BUFCMD_100MHZ_SINGLE      0x00000000  /* PSDMR[BUFCMD] at 100 MHz single mode */
 728 #define PSDMR_BUFCMD_133MHZ_SINGLE      0x00000004  /* PSDMR[BUFCMD] at 133 MHz single mode */
 729 #define PSDMR_BUFCMD_66MHZ_60X          0x00000000  /* PSDMR[BUFCMD] at 66 MHz 60x mode */
 730 #define PSDMR_BUFCMD_100MHZ_60X         0x00000000  /* PSDMR[BUFCMD] at 100 MHz 60x mode */
 731 #define PSDMR_BUFCMD_DEFAULT            PSDMR_BUFCMD_133MHZ_SINGLE  /* PSDMR[BUFCMD] default value */
 732
 733 #endif /* CONFIG_SYS_RAMBOOT */
 734
 735 #endif  /* __CONFIG_H */