include/configs/TQM8272.h

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC8260          1       /* This is a MPC8260 CPU                */
  37 #define CONFIG_MPC8272_FAMILY   1
  38 #define CONFIG_TQM8272          1
  39
  40 #define CONFIG_GET_CPU_STR_F    1       /* Get the CPU ID STR */
  41 #define CONFIG_BOARD_GET_CPU_CLK_F      1 /* Get the CLKIN from board fct */
  42
  43 #define STK82xx_150             1       /* on a STK82xx.150 */
  44
  45 #define CONFIG_CPM2             1       /* Has a CPM2 */
  46
  47 #define CONFIG_82xx_CONS_SMC1   1       /* console on SMC1              */
  48
  49 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  50
  51 #define CONFIG_BOARD_EARLY_INIT_R       1
  52
  53 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  54 #define CONFIG_BAUDRATE         230400
  55 #else
  56 #define CONFIG_BAUDRATE         115200
  57 #endif
  58
  59 #define CONFIG_PREBOOT  "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
  60
  61 #undef  CONFIG_BOOTARGS
  62
  63 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  64         "netdev=eth0\0"                                                 \
  65         "consdev=ttyCPM0\0"                                             \
  66         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  67                 "nfsroot=${serverip}:${rootpath}\0"                     \
  68         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  69         "hostname=tqm8272\0"                                            \
  70         "addip=setenv bootargs ${bootargs} "                            \
  71                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  72                 ":${hostname}:${netdev}:off panic=1\0"                  \
  73         "addcons=setenv bootargs ${bootargs} "                          \
  74                 "console=$(consdev),$(baudrate)\0"                      \
  75         "flash_nfs=run nfsargs addip addcons;"                          \
  76                 "bootm ${kernel_addr}\0"                                \
  77         "flash_self=run ramargs addip addcons;"                         \
  78                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  79         "net_nfs=tftp 300000 ${bootfile};"                              \
  80                 "run nfsargs addip addcons;bootm\0"                     \
  81         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
  82         "bootfile=/tftpboot/tqm8272/uImage\0"                           \
  83         "kernel_addr=40080000\0"                                        \
  84         "ramdisk_addr=40100000\0"                                       \
  85         "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0"               \
  86         "update=protect off 40000000 4003ffff;era 40000000 4003ffff;"   \
  87                 "cp.b 300000 40000000 40000;"                           \
  88                 "setenv filesize;saveenv\0"                             \
  89         "cphwib=cp.b 4003fc00 33fc00 400\0"                             \
  90         "upd=run load;run cphwib;run update\0"                          \
  91         ""
  92 #define CONFIG_BOOTCOMMAND      "run flash_self"
  93
  94 #define CONFIG_I2C      1
  95
  96 #if CONFIG_I2C
  97 /* enable I2C and select the hardware/software driver */
  98 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  99 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 100 #define ADD_CMD_I2C             CFG_CMD_I2C     | \
 101                                 CFG_CMD_DATE    |\
 102                                 CFG_CMD_DTT     |\
 103                                 CFG_CMD_EEPROM
 104 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 105 #define CFG_I2C_SLAVE           0x7F
 106
 107 /*
 108  * Software (bit-bang) I2C driver configuration
 109  */
 110 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 111 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 112 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 113 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 114 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 115                         else    iop->pdat &= ~0x00010000
 116 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 117                         else    iop->pdat &= ~0x00020000
 118 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 119
 120 #define CONFIG_I2C_X
 121
 122 /* EEPROM */
 123 #define CFG_I2C_EEPROM_ADDR_LEN 2
 124 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 125 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 126 #define CFG_EEPROM_PAGE_WRITE_ENABLE    /* necessary for the LM75 chip */
 127 #define CFG_I2C_MULTI_EEPROMS           1       /* more than one eeprom */
 128
 129 /* I2C RTC */
 130 #define CONFIG_RTC_DS1337               /* Use ds1337 rtc via i2c       */
 131 #define CFG_I2C_RTC_ADDR        0x68    /* at address 0x68              */
 132
 133 /* I2C SYSMON (LM75) */
 134 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 135 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 136 #define CFG_DTT_MAX_TEMP        70
 137 #define CFG_DTT_LOW_TEMP        -30
 138 #define CFG_DTT_HYSTERESIS      3
 139
 140 #else
 141 #undef CONFIG_HARD_I2C
 142 #undef CONFIG_SOFT_I2C
 143 #define ADD_CMD_I2C             0
 144 #endif
 145
 146 /*
 147  * select serial console configuration
 148  *
 149  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 150  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 151  * for SCC).
 152  *
 153  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 154  * defined elsewhere (for example, on the cogent platform, there are serial
 155  * ports on the motherboard which are used for the serial console - see
 156  * cogent/cma101/serial.[ch]).
 157  */
 158 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
 159 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 160 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
 161 #ifdef CONFIG_82xx_CONS_SMC1
 162 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
 163 #endif
 164 #ifdef CONFIG_82xx_CONS_SMC2
 165 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
 166 #endif
 167
 168 #undef  CONFIG_CONS_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
 169 #define CONFIG_CONS_EXTC_RATE   3686400 /* SMC/SCC ext clk rate in Hz */
 170 #define CONFIG_CONS_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9 */
 171
 172 /*
 173  * select ethernet configuration
 174  *
 175  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 176  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 177  * for FCC)
 178  *
 179  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 180  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 181  * from CONFIG_COMMANDS to remove support for networking.
 182  *
 183  * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
 184  * X.29 connector, and FCC2 is hardwired to the X.1 connector)
 185  */
 186 #define CFG_FCC_ETHERNET
 187
 188 #if defined(CFG_FCC_ETHERNET)
 189 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 190 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 191 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 192 #define CONFIG_ETHER_INDEX    2         /* which SCC/FCC channel for ethernet */
 193 #else
 194 #define CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 195 #undef  CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 196 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 197 #define CONFIG_ETHER_INDEX    1         /* which SCC/FCC channel for ethernet */
 198 #endif
 199
 200 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
 201
 202 /*
 203  *  - RX clk is CLK11
 204  *  - TX clk is CLK12
 205  */
 206 # define CFG_CMXSCR_VALUE       (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
 207
 208 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 209
 210 /*
 211  * - Rx-CLK is CLK13
 212  * - Tx-CLK is CLK14
 213  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 214  * - Enable Full Duplex in FSMR
 215  */
 216 # define CFG_CMXFCR_MASK        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 217 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 218 # define CFG_CPMFCR_RAMTYPE     0
 219 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
 220
 221 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 222
 223 #define CONFIG_MII                      /* MII PHY management           */
 224 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 225 /*
 226  * GPIO pins used for bit-banged MII communications
 227  */
 228 #define MDIO_PORT       2               /* Port C */
 229
 230 #if STK82xx_150
 231 #define CFG_MDIO_PIN    0x00008000      /* PC16 */
 232 #define CFG_MDC_PIN     0x00004000      /* PC17 */
 233 #endif
 234
 235 #if STK82xx_100
 236 #define CFG_MDIO_PIN    0x00000002      /* PC30 */
 237 #define CFG_MDC_PIN     0x00000001      /* PC31 */
 238 #endif
 239
 240 #if 1
 241 #define MDIO_ACTIVE     (iop->pdir |=  CFG_MDIO_PIN)
 242 #define MDIO_TRISTATE   (iop->pdir &= ~CFG_MDIO_PIN)
 243 #define MDIO_READ       ((iop->pdat &  CFG_MDIO_PIN) != 0)
 244
 245 #define MDIO(bit)       if(bit) iop->pdat |=  CFG_MDIO_PIN; \
 246                         else    iop->pdat &= ~CFG_MDIO_PIN
 247
 248 #define MDC(bit)        if(bit) iop->pdat |=  CFG_MDC_PIN; \
 249                         else    iop->pdat &= ~CFG_MDC_PIN
 250 #else
 251 #define MDIO_ACTIVE     ({unsigned long tmp; tmp = iop->pdir; tmp |=  CFG_MDIO_PIN; iop->pdir = tmp;})
 252 #define MDIO_TRISTATE   ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CFG_MDIO_PIN; iop->pdir = tmp;})
 253 #define MDIO_READ       ((iop->pdat &  CFG_MDIO_PIN) != 0)
 254
 255 #define MDIO(bit)       if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CFG_MDIO_PIN; iop->pdat = tmp;}\
 256                         else    {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDIO_PIN; iop->pdat = tmp;}
 257
 258 #define MDC(bit)        if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CFG_MDC_PIN; iop->pdat = tmp;}\
 259                         else    {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDC_PIN; iop->pdat = tmp;}
 260 #endif
 261
 262 #define MIIDELAY        udelay(1)
 263
 264
 265 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 266 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
 267
 268 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 269 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
 270
 271 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 272
 273 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 274
 275 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
 276
 277 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL  | \
 278                                 CFG_CMD_NAND    | \
 279                                 CFG_CMD_DHCP    | \
 280                                 CFG_CMD_PING    | \
 281                                 ADD_CMD_I2C     | \
 282                                 CFG_CMD_NFS     | \
 283                                 CFG_CMD_MII     | \
 284                                 CFG_CMD_PCI     | \
 285                                 CFG_CMD_SNTP    )
 286
 287 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 288 #include <cmd_confdefs.h>
 289
 290 /*
 291  * Miscellaneous configurable options
 292  */
 293 #define CFG_LONGHELP                    /* undef to save memory         */
 294 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 295
 296 #if 0
 297 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 298 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 299 #ifdef  CFG_HUSH_PARSER
 300 #define CFG_PROMPT_HUSH_PS2     "> "
 301 #endif
 302 #endif
 303
 304 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 305 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 306 #else
 307 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 308 #endif
 309 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 310 #define CFG_MAXARGS     16              /* max number of command args   */
 311 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 312
 313 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 314 #define CFG_MEMTEST_END 0x0C00000       /* 4 ... 12 MB in DRAM  */
 315
 316 #define CFG_LOAD_ADDR   0x300000        /* default load address */
 317
 318 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 319
 320 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 321
 322 #define CFG_RESET_ADDRESS 0x40000104    /* "bad" address                */
 323
 324 /*
 325  * For booting Linux, the board info and command line data
 326  * have to be in the first 8 MB of memory, since this is
 327  * the maximum mapped by the Linux kernel during initialization.
 328  */
 329 #define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 330
 331 /*-----------------------------------------------------------------------
 332  * CAN stuff
 333  *-----------------------------------------------------------------------
 334  */
 335 #define CFG_CAN_BASE    0x51000000
 336 #define CFG_CAN_SIZE    1
 337 #define CFG_CAN_BR      ((CFG_CAN_BASE & BRx_BA_MSK)    |\
 338                          BRx_PS_8                       |\
 339                          BRx_MS_UPMC                    |\
 340                          BRx_V)
 341
 342 #define CFG_CAN_OR      (MEG_TO_AM(CFG_CAN_SIZE)        |\
 343                          ORxU_BI)
 344
 345
 346 /* What should the base address of the main FLASH be and how big is
 347  * it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk
 348  * The main FLASH is whichever is connected to *CS0.
 349  */
 350 #define CFG_FLASH0_BASE 0x40000000
 351 #define CFG_FLASH0_SIZE 32      /* 32 MB */
 352
 353 /* Flash bank size (for preliminary settings)
 354  */
 355 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
 356
 357 /*-----------------------------------------------------------------------
 358  * FLASH organization
 359  */
 360 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 361 #define CFG_MAX_FLASH_SECT      128     /* max num of sects on one chip */
 362
 363 #define CFG_FLASH_CFI                           /* flash is CFI compat. */
 364 #define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver*/
 365 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector   */
 366 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash*/
 367
 368 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 369 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 370
 371 #define CFG_UPDATE_FLASH_SIZE
 372
 373 #define CFG_ENV_IS_IN_FLASH     1
 374 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x40000)
 375 #define CFG_ENV_SIZE            0x20000
 376 #define CFG_ENV_SECT_SIZE       0x20000
 377 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SIZE)
 378 #define CFG_ENV_SIZE_REDUND     0x20000
 379
 380 /* Where is the Hardwareinformation Block (from Monitor Sources) */
 381 #define MON_RES_LENGTH          (0x0003FC00)
 382 #define HWIB_INFO_START_ADDR    (CFG_FLASH_BASE + MON_RES_LENGTH)
 383 #define HWIB_INFO_LEN           512
 384 #define CIB_INFO_START_ADDR     (CFG_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
 385 #define CIB_INFO_LEN            512
 386
 387 #define CFG_HWINFO_OFFSET       0x3fc00 /* offset of HW Info block */
 388 #define CFG_HWINFO_SIZE         0x00000060      /* size   of HW Info block */
 389 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 390
 391 /*-----------------------------------------------------------------------
 392  * NAND-FLASH stuff
 393  *-----------------------------------------------------------------------
 394  */
 395 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 396
 397 #define CFG_NAND_CS_DIST                0x80
 398 #define CFG_NAND_UPM_WRITE_CMD_OFS      0x20
 399 #define CFG_NAND_UPM_WRITE_ADDR_OFS     0x40
 400
 401 #define CFG_NAND_BR     ((CFG_NAND0_BASE & BRx_BA_MSK)  |\
 402                          BRx_PS_8                       |\
 403                          BRx_MS_UPMB                    |\
 404                          BRx_V)
 405
 406 #define CFG_NAND_OR     (MEG_TO_AM(CFG_NAND_SIZE)       |\
 407                          ORxU_BI                        |\
 408                          ORxU_EHTR_8IDLE)
 409
 410 #define CFG_NAND_SIZE   1
 411 #define CFG_NAND0_BASE 0x50000000
 412 #define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST)
 413 #define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST)
 414 #define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST)
 415
 416 #define CFG_MAX_NAND_DEVICE     4       /* Max number of NAND devices           */
 417 #define NAND_MAX_CHIPS 1
 418
 419 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
 420                              CFG_NAND1_BASE, \
 421                              CFG_NAND2_BASE, \
 422                              CFG_NAND3_BASE, \
 423                            }
 424
 425 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
 426 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
 427 #define WRITE_NAND_UPM(d, adr, off) do \
 428 { \
 429         volatile unsigned char *addr = (unsigned char *) (adr + off); \
 430         WRITE_NAND(d, addr); \
 431 } while(0)
 432
 433 #endif /* CFG_CMD_NAND */
 434
 435 #define CONFIG_PCI
 436 #ifdef CONFIG_PCI
 437 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
 438 #define CONFIG_PCI_PNP
 439 #define CONFIG_EEPRO100
 440 #define CFG_RX_ETH_BUFFER       8               /* use 8 rx buffer on eepro100  */
 441 #define CONFIG_PCI_SCAN_SHOW
 442 #endif
 443
 444 /*-----------------------------------------------------------------------
 445  * Hard Reset Configuration Words
 446  *
 447  * if you change bits in the HRCW, you must also change the CFG_*
 448  * defines for the various registers affected by the HRCW e.g. changing
 449  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 450  */
 451 #if 0
 452 #define __HRCW__ALL__           (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 453
 454 #  define CFG_HRCW_MASTER       (__HRCW__ALL__ | HRCW_MODCK_H0111)
 455 #else
 456 #define CFG_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
 457 #endif
 458
 459 /* no slaves so just fill with zeros */
 460 #define CFG_HRCW_SLAVE1         0
 461 #define CFG_HRCW_SLAVE2         0
 462 #define CFG_HRCW_SLAVE3         0
 463 #define CFG_HRCW_SLAVE4         0
 464 #define CFG_HRCW_SLAVE5         0
 465 #define CFG_HRCW_SLAVE6         0
 466 #define CFG_HRCW_SLAVE7         0
 467
 468 /*-----------------------------------------------------------------------
 469  * Internal Memory Mapped Register
 470  */
 471 #define CFG_IMMR                0xFFF00000
 472
 473 /*-----------------------------------------------------------------------
 474  * Definitions for initial stack pointer and data area (in DPRAM)
 475  */
 476 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 477 #define CFG_INIT_RAM_END        0x2000  /* End of used area in DPRAM    */
 478 #define CFG_GBL_DATA_SIZE       128 /* size in bytes reserved for initial data*/
 479 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 480 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 481
 482 /*-----------------------------------------------------------------------
 483  * Start addresses for the final memory configuration
 484  * (Set up by the startup code)
 485  * Please note that CFG_SDRAM_BASE _must_ start at 0
 486  */
 487 #define CFG_SDRAM_BASE          0x00000000
 488 #define CFG_FLASH_BASE          CFG_FLASH0_BASE
 489 #define CFG_MONITOR_BASE        TEXT_BASE
 490 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor */
 491 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()*/
 492
 493 /*
 494  * Internal Definitions
 495  *
 496  * Boot Flags
 497  */
 498 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH*/
 499 #define BOOTFLAG_WARM           0x02    /* Software reboot                 */
 500
 501 /*-----------------------------------------------------------------------
 502  * Cache Configuration
 503  */
 504 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 505 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 506 # define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 507 #endif
 508
 509 /*-----------------------------------------------------------------------
 510  * HIDx - Hardware Implementation-dependent Registers                    2-11
 511  *-----------------------------------------------------------------------
 512  * HID0 also contains cache control - initially enable both caches and
 513  * invalidate contents, then the final state leaves only the instruction
 514  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 515  * but Soft reset does not.
 516  *
 517  * HID1 has only read-only information - nothing to set.
 518  */
 519 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 520                                 HID0_IFEM|HID0_ABE)
 521 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 522 #define CFG_HID2        0
 523
 524 /*-----------------------------------------------------------------------
 525  * RMR - Reset Mode Register                                     5-5
 526  *-----------------------------------------------------------------------
 527  * turn on Checkstop Reset Enable
 528  */
 529 #define CFG_RMR         RMR_CSRE
 530
 531 /*-----------------------------------------------------------------------
 532  * BCR - Bus Configuration                                       4-25
 533  *-----------------------------------------------------------------------
 534  */
 535 #define CFG_BCR_60x         (BCR_EBM|BCR_NPQM0|BCR_NPQM2)       /* 60x mode  */
 536 #define BCR_APD01       0x10000000
 537 #define CFG_BCR_SINGLE          (BCR_APD01|BCR_ETM)     /* 8260 mode */
 538
 539 /*-----------------------------------------------------------------------
 540  * SIUMCR - SIU Module Configuration                             4-31
 541  *-----------------------------------------------------------------------
 542  */
 543 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
 544 #define CFG_SIUMCR_LOW          (SIUMCR_DPPC00)
 545 #define CFG_SIUMCR_HIGH         (SIUMCR_DPPC00 | SIUMCR_ABE)
 546 #else
 547 #define CFG_SIUMCR              (SIUMCR_DPPC00)
 548 #endif
 549
 550 /*-----------------------------------------------------------------------
 551  * SYPCR - System Protection Control                             4-35
 552  * SYPCR can only be written once after reset!
 553  *-----------------------------------------------------------------------
 554  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 555  */
 556 #if defined(CONFIG_WATCHDOG)
 557 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 558                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 559 #else
 560 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 561                          SYPCR_SWRI|SYPCR_SWP)
 562 #endif /* CONFIG_WATCHDOG */
 563
 564 /*-----------------------------------------------------------------------
 565  * TMCNTSC - Time Counter Status and Control                     4-40
 566  *-----------------------------------------------------------------------
 567  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 568  * and enable Time Counter
 569  */
 570 #define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 571
 572 /*-----------------------------------------------------------------------
 573  * PISCR - Periodic Interrupt Status and Control                 4-42
 574  *-----------------------------------------------------------------------
 575  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 576  * Periodic timer
 577  */
 578 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 579
 580 /*-----------------------------------------------------------------------
 581  * SCCR - System Clock Control                                   9-8
 582  *-----------------------------------------------------------------------
 583  * Ensure DFBRG is Divide by 16
 584  */
 585 #define CFG_SCCR        SCCR_DFBRG01
 586
 587 /*-----------------------------------------------------------------------
 588  * RCCR - RISC Controller Configuration                         13-7
 589  *-----------------------------------------------------------------------
 590  */
 591 #define CFG_RCCR        0
 592
 593 /*
 594  * Init Memory Controller:
 595  *
 596  * Bank Bus     Machine PortSz  Device
 597  * ---- ---     ------- ------  ------
 598  *  0   60x     GPCM    32 bit  FLASH
 599  *  1   60x     SDRAM   64 bit  SDRAM
 600  *  2   60x     UPMB     8 bit  NAND
 601  *  3   60x     UPMC     8 bit  CAN
 602  *
 603  */
 604
 605 /* Initialize SDRAM
 606          */
 607 #undef CFG_INIT_LOCAL_SDRAM             /* No SDRAM on Local Bus */
 608
 609 #define SDRAM_MAX_SIZE  0x20000000      /* max. 512 MB          */
 610
 611 /* Minimum mask to separate preliminary
 612  * address ranges for CS[0:2]
 613  */
 614 #define CFG_GLOBAL_SDRAM_LIMIT  (512<<20)       /* less than 512 MB */
 615
 616 #define CFG_MPTPR       0x4000
 617
 618 /*-----------------------------------------------------------------------------
 619  * Address for Mode Register Set (MRS) command
 620  *-----------------------------------------------------------------------------
 621  * In fact, the address is rather configuration data presented to the SDRAM on
 622  * its address lines. Because the address lines may be mux'ed externally either
 623  * for 8 column or 9 column devices, some bits appear twice in the 8260's
 624  * address:
 625  *
 626  * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
 627  * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
 628  *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
 629  *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
 630  *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
 631  *-----------------------------------------------------------------------------
 632  */
 633 #define CFG_MRS_OFFS    0x00000110
 634
 635 /* Bank 0 - FLASH
 636  */
 637 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
 638                          BRx_PS_32                      |\
 639                          BRx_MS_GPCM_P                  |\
 640                          BRx_V)
 641
 642 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
 643                          ORxG_CSNT                      |\
 644                          ORxG_ACS_DIV4                  |\
 645                          ORxG_SCY_8_CLK                 |\
 646                          ORxG_TRLX)
 647
 648 /* SDRAM on TQM8272 can have either 8 or 9 columns.
 649  * The number affects configuration values.
 650  */
 651
 652 /* Bank 1 - 60x bus SDRAM
 653  */
 654 #define CFG_PSRT        0x20    /* Low Value */
 655 /* #define CFG_PSRT        0x10  Fast Value */
 656 #define CFG_LSRT        0x20    /* Local Bus */
 657 #ifndef CFG_RAMBOOT
 658 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
 659                          BRx_PS_64                      |\
 660                          BRx_MS_SDRAM_P                 |\
 661                          BRx_V)
 662
 663 #define CFG_OR1_PRELIM  CFG_OR1_8COL
 664
 665 /* SDRAM initialization values for 8-column chips
 666  */
 667 #define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 668                          ORxS_BPD_4                     |\
 669                          ORxS_ROWST_PBI1_A7             |\
 670                          ORxS_NUMR_12)
 671
 672 #define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
 673                          PSDMR_SDAM_A15_IS_A5           |\
 674                          PSDMR_BSMA_A12_A14             |\
 675                          PSDMR_SDA10_PBI1_A8            |\
 676                          PSDMR_RFRC_7_CLK               |\
 677                          PSDMR_PRETOACT_2W              |\
 678                          PSDMR_ACTTORW_2W               |\
 679                          PSDMR_LDOTOPRE_1C              |\
 680                          PSDMR_WRC_2C                   |\
 681                          PSDMR_EAMUX                    |\
 682                          PSDMR_BUFCMD                   |\
 683                          PSDMR_CL_2)
 684
 685
 686 /* SDRAM initialization values for 9-column chips
 687  */
 688 #define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 689                          ORxS_BPD_4                     |\
 690                          ORxS_ROWST_PBI1_A5             |\
 691                          ORxS_NUMR_13)
 692
 693 #define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
 694                          PSDMR_SDAM_A16_IS_A5           |\
 695                          PSDMR_BSMA_A12_A14             |\
 696                          PSDMR_SDA10_PBI1_A7            |\
 697                          PSDMR_RFRC_7_CLK               |\
 698                          PSDMR_PRETOACT_2W              |\
 699                          PSDMR_ACTTORW_2W               |\
 700                          PSDMR_LDOTOPRE_1C              |\
 701                          PSDMR_WRC_2C                   |\
 702                          PSDMR_EAMUX                    |\
 703                          PSDMR_BUFCMD                   |\
 704                          PSDMR_CL_2)
 705
 706 #define CFG_OR1_10COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 707                          ORxS_BPD_4                     |\
 708                          ORxS_ROWST_PBI1_A4             |\
 709                          ORxS_NUMR_13)
 710
 711 #define CFG_PSDMR_10COL  (PSDMR_PBI                      |\
 712                          PSDMR_SDAM_A17_IS_A5           |\
 713                          PSDMR_BSMA_A12_A14             |\
 714                          PSDMR_SDA10_PBI1_A4            |\
 715                          PSDMR_RFRC_6_CLK               |\
 716                          PSDMR_PRETOACT_2W              |\
 717                          PSDMR_ACTTORW_2W               |\
 718                          PSDMR_LDOTOPRE_1C              |\
 719                          PSDMR_WRC_2C                   |\
 720                          PSDMR_EAMUX                    |\
 721                          PSDMR_BUFCMD                   |\
 722                          PSDMR_CL_2)
 723
 724 #define PSDMR_RFRC_66MHZ_SINGLE         0x00028000  /* PSDMR[RFRC] at 66 MHz single mode */
 725 #define PSDMR_RFRC_100MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 100 MHz single mode */
 726 #define PSDMR_RFRC_133MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 133 MHz single mode */
 727 #define PSDMR_RFRC_66MHZ_60X            0x00030000  /* PSDMR[RFRC] at 66 MHz 60x mode */
 728 #define PSDMR_RFRC_100MHZ_60X           0x00028000  /* PSDMR[RFRC] at 100 MHz 60x mode */
 729 #define PSDMR_RFRC_DEFAULT              PSDMR_RFRC_133MHZ_SINGLE  /* PSDMR[RFRC] default value */
 730
 731 #define PSDMR_PRETOACT_66MHZ_SINGLE     0x00002000  /* PSDMR[PRETOACT] at 66 MHz single mode */
 732 #define PSDMR_PRETOACT_100MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 100 MHz single mode */
 733 #define PSDMR_PRETOACT_133MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 133 MHz single mode */
 734 #define PSDMR_PRETOACT_66MHZ_60X        0x00001000  /* PSDMR[PRETOACT] at 66 MHz 60x mode */
 735 #define PSDMR_PRETOACT_100MHZ_60X       0x00001000  /* PSDMR[PRETOACT] at 100 MHz 60x mode */
 736 #define PSDMR_PRETOACT_DEFAULT          PSDMR_PRETOACT_133MHZ_SINGLE  /* PSDMR[PRETOACT] default value */
 737
 738 #define PSDMR_WRC_66MHZ_SINGLE          0x00000020  /* PSDMR[WRC] at 66 MHz single mode */
 739 #define PSDMR_WRC_100MHZ_SINGLE         0x00000020  /* PSDMR[WRC] at 100 MHz single mode */
 740 #define PSDMR_WRC_133MHZ_SINGLE         0x00000010  /* PSDMR[WRC] at 133 MHz single mode */
 741 #define PSDMR_WRC_66MHZ_60X             0x00000010  /* PSDMR[WRC] at 66 MHz 60x mode */
 742 #define PSDMR_WRC_100MHZ_60X            0x00000010  /* PSDMR[WRC] at 100 MHz 60x mode */
 743 #define PSDMR_WRC_DEFAULT               PSDMR_WRC_133MHZ_SINGLE  /* PSDMR[WRC] default value */
 744
 745 #define PSDMR_BUFCMD_66MHZ_SINGLE       0x00000000  /* PSDMR[BUFCMD] at 66 MHz single mode */
 746 #define PSDMR_BUFCMD_100MHZ_SINGLE      0x00000000  /* PSDMR[BUFCMD] at 100 MHz single mode */
 747 #define PSDMR_BUFCMD_133MHZ_SINGLE      0x00000004  /* PSDMR[BUFCMD] at 133 MHz single mode */
 748 #define PSDMR_BUFCMD_66MHZ_60X          0x00000000  /* PSDMR[BUFCMD] at 66 MHz 60x mode */
 749 #define PSDMR_BUFCMD_100MHZ_60X         0x00000000  /* PSDMR[BUFCMD] at 100 MHz 60x mode */
 750 #define PSDMR_BUFCMD_DEFAULT            PSDMR_BUFCMD_133MHZ_SINGLE  /* PSDMR[BUFCMD] default value */
 751
 752 #endif /* CFG_RAMBOOT */
 753
 754 #endif  /* __CONFIG_H */