include/configs/TQM850L.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  37 #define CONFIG_TQM850L          1       /* ...on a TQM8xxL module       */
  38
  39 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  40 #undef  CONFIG_8xx_CONS_SMC2
  41 #undef  CONFIG_8xx_CONS_NONE
  42 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  43
  44 #define CONFIG_BOOTCOUNT_LIMIT
  45
  46 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  47
  48 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  49
  50 #define CONFIG_PREBOOT  "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
  51
  52 #undef  CONFIG_BOOTARGS
  53
  54 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  55         "netdev=eth0\0"                                                 \
  56         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  57                 "nfsroot=${serverip}:${rootpath}\0"                     \
  58         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  59         "addip=setenv bootargs ${bootargs} "                            \
  60                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  61                 ":${hostname}:${netdev}:off panic=1\0"                  \
  62         "flash_nfs=run nfsargs addip;"                                  \
  63                 "bootm ${kernel_addr}\0"                                \
  64         "flash_self=run ramargs addip;"                                 \
  65                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  66         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  67         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  68         "bootfile=/tftpboot/TQM850L/uImage\0"                           \
  69         "kernel_addr=40040000\0"                                        \
  70         "ramdisk_addr=40100000\0"                                       \
  71         ""
  72 #define CONFIG_BOOTCOMMAND      "run flash_self"
  73
  74 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  75 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  76
  77 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  78
  79 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  80
  81 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  82
  83 /*
  84  * BOOTP options
  85  */
  86 #define CONFIG_BOOTP_SUBNETMASK
  87 #define CONFIG_BOOTP_GATEWAY
  88 #define CONFIG_BOOTP_HOSTNAME
  89 #define CONFIG_BOOTP_BOOTPATH
  90 #define CONFIG_BOOTP_BOOTFILESIZE
  91
  92
  93 #define CONFIG_MAC_PARTITION
  94 #define CONFIG_DOS_PARTITION
  95
  96 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  97
  98 /*
  99  * Command line configuration.
 100  */
 101 #include <config_cmd_default.h>
 102
 103 #define CONFIG_CMD_ASKENV
 104 #define CONFIG_CMD_DATE
 105 #define CONFIG_CMD_DHCP
 106 #define CONFIG_CMD_IDE
 107 #define CONFIG_CMD_NFS
 108 #define CONFIG_CMD_SNTP
 109
 110
 111 /*
 112  * Miscellaneous configurable options
 113  */
 114 #define CFG_LONGHELP                    /* undef to save memory         */
 115 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 116
 117 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 118 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 119 #ifdef  CFG_HUSH_PARSER
 120 #define CFG_PROMPT_HUSH_PS2     "> "
 121 #endif
 122
 123 #if defined(CONFIG_CMD_KGDB)
 124 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 125 #else
 126 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 127 #endif
 128 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 129 #define CFG_MAXARGS             16      /* max number of command args   */
 130 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 131
 132 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 133 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 134
 135 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 136
 137 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 138
 139 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 140
 141 /*
 142  * Low Level Configuration Settings
 143  * (address mappings, register initial values, etc.)
 144  * You should know what you are doing if you make changes here.
 145  */
 146 /*-----------------------------------------------------------------------
 147  * Internal Memory Mapped Register
 148  */
 149 #define CFG_IMMR                0xFFF00000
 150
 151 /*-----------------------------------------------------------------------
 152  * Definitions for initial stack pointer and data area (in DPRAM)
 153  */
 154 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 155 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 156 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 157 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 158 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 159
 160 /*-----------------------------------------------------------------------
 161  * Start addresses for the final memory configuration
 162  * (Set up by the startup code)
 163  * Please note that CFG_SDRAM_BASE _must_ start at 0
 164  */
 165 #define CFG_SDRAM_BASE          0x00000000
 166 #define CFG_FLASH_BASE          0x40000000
 167 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 168 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 169 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 170
 171 /*
 172  * For booting Linux, the board info and command line data
 173  * have to be in the first 8 MB of memory, since this is
 174  * the maximum mapped by the Linux kernel during initialization.
 175  */
 176 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 177
 178 /*-----------------------------------------------------------------------
 179  * FLASH organization
 180  */
 181 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 182 #define CFG_MAX_FLASH_SECT      71      /* max number of sectors on one chip    */
 183
 184 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 185 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 186
 187 #define CFG_ENV_IS_IN_FLASH     1
 188 #define CFG_ENV_OFFSET          0x8000  /*   Offset   of Environment Sector     */
 189 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 190
 191 /* Address and size of Redundant Environment Sector     */
 192 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
 193 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 194
 195 /*-----------------------------------------------------------------------
 196  * Hardware Information Block
 197  */
 198 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 199 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 200 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 201
 202 /*-----------------------------------------------------------------------
 203  * Cache Configuration
 204  */
 205 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 206 #if defined(CONFIG_CMD_KGDB)
 207 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 208 #endif
 209
 210 /*-----------------------------------------------------------------------
 211  * SYPCR - System Protection Control                            11-9
 212  * SYPCR can only be written once after reset!
 213  *-----------------------------------------------------------------------
 214  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 215  */
 216 #if defined(CONFIG_WATCHDOG)
 217 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 218                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 219 #else
 220 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 221 #endif
 222
 223 /*-----------------------------------------------------------------------
 224  * SIUMCR - SIU Module Configuration                            11-6
 225  *-----------------------------------------------------------------------
 226  * PCMCIA config., multi-function pin tri-state
 227  */
 228 #ifndef CONFIG_CAN_DRIVER
 229 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 230 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 231 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 232 #endif  /* CONFIG_CAN_DRIVER */
 233
 234 /*-----------------------------------------------------------------------
 235  * TBSCR - Time Base Status and Control                         11-26
 236  *-----------------------------------------------------------------------
 237  * Clear Reference Interrupt Status, Timebase freezing enabled
 238  */
 239 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 240
 241 /*-----------------------------------------------------------------------
 242  * RTCSC - Real-Time Clock Status and Control Register          11-27
 243  *-----------------------------------------------------------------------
 244  */
 245 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 246
 247 /*-----------------------------------------------------------------------
 248  * PISCR - Periodic Interrupt Status and Control                11-31
 249  *-----------------------------------------------------------------------
 250  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 251  */
 252 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 253
 254 /*-----------------------------------------------------------------------
 255  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 256  *-----------------------------------------------------------------------
 257  * Reset PLL lock status sticky bit, timer expired status bit and timer
 258  * interrupt status bit
 259  */
 260 #define CFG_PLPRCR      (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 261
 262 /*-----------------------------------------------------------------------
 263  * SCCR - System Clock and reset Control Register               15-27
 264  *-----------------------------------------------------------------------
 265  * Set clock output, timebase and RTC source and divider,
 266  * power management and some other internal clocks
 267  */
 268 #define SCCR_MASK       SCCR_EBDF11
 269 #define CFG_SCCR        (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 270                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 271                          SCCR_DFALCD00)
 272
 273 /*-----------------------------------------------------------------------
 274  * PCMCIA stuff
 275  *-----------------------------------------------------------------------
 276  *
 277  */
 278 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 279 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 280 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 281 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 282 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 283 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 284 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 285 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 286
 287 /*-----------------------------------------------------------------------
 288  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 289  *-----------------------------------------------------------------------
 290  */
 291
 292 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 293
 294 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 295 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 296 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 297
 298 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 299 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 300
 301 #define CFG_ATA_IDE0_OFFSET     0x0000
 302
 303 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 304
 305 /* Offset for data I/O                  */
 306 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 307
 308 /* Offset for normal register accesses  */
 309 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 310
 311 /* Offset for alternate registers       */
 312 #define CFG_ATA_ALT_OFFSET      0x0100
 313
 314 /*-----------------------------------------------------------------------
 315  *
 316  *-----------------------------------------------------------------------
 317  *
 318  */
 319 #define CFG_DER 0
 320
 321 /*
 322  * Init Memory Controller:
 323  *
 324  * BR0/1 and OR0/1 (FLASH)
 325  */
 326
 327 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 328 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 329
 330 /* used to re-map FLASH both when starting from SRAM or FLASH:
 331  * restrict access enough to keep SRAM working (if any)
 332  * but not too much to meddle with FLASH accesses
 333  */
 334 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 335 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 336
 337 /*
 338  * FLASH timing:
 339  */
 340 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 341                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 342
 343 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 344 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 345 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 346
 347 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 348 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 349 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 350
 351 /*
 352  * BR2/3 and OR2/3 (SDRAM)
 353  *
 354  */
 355 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 356 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 357 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 358
 359 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 360 #define CFG_OR_TIMING_SDRAM     0x00000A00
 361
 362 #define CFG_OR2_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 363 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 364
 365 #ifndef CONFIG_CAN_DRIVER
 366 #define CFG_OR3_PRELIM  CFG_OR2_PRELIM
 367 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 368 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 369 #define CFG_CAN_BASE            0xC0000000      /* CAN mapped at 0xC0000000     */
 370 #define CFG_CAN_OR_AM           0xFFFF8000      /* 32 kB address mask           */
 371 #define CFG_OR3_CAN             (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
 372 #define CFG_BR3_CAN             ((CFG_CAN_BASE & BR_BA_MSK) | \
 373                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 374 #endif  /* CONFIG_CAN_DRIVER */
 375
 376 /*
 377  * Memory Periodic Timer Prescaler
 378  *
 379  * The Divider for PTA (refresh timer) configuration is based on an
 380  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 381  * the number of chip selects (NCS) and the actually needed refresh
 382  * rate is done by setting MPTPR.
 383  *
 384  * PTA is calculated from
 385  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 386  *
 387  *      gclk      CPU clock (not bus clock!)
 388  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 389  *
 390  * 4096  Rows from SDRAM example configuration
 391  * 1000  factor s -> ms
 392  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 393  *    4  Number of refresh cycles per period
 394  *   64  Refresh cycle in ms per number of rows
 395  * --------------------------------------------
 396  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 397  *
 398  * 50 MHz => 50.000.000 / Divider =  98
 399  * 66 Mhz => 66.000.000 / Divider = 129
 400  * 80 Mhz => 80.000.000 / Divider = 156
 401  */
 402
 403 #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
 404 #define CFG_MAMR_PTA    98
 405
 406 /*
 407  * For 16 MBit, refresh rates could be 31.3 us
 408  * (= 64 ms / 2K = 125 / quad bursts).
 409  * For a simpler initialization, 15.6 us is used instead.
 410  *
 411  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 412  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 413  */
 414 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 415 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 416
 417 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 418 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 419 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 420
 421 /*
 422  * MAMR settings for SDRAM
 423  */
 424
 425 /* 8 column SDRAM */
 426 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 427                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 428                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 429 /* 9 column SDRAM */
 430 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 431                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 432                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 433
 434
 435 /*
 436  * Internal Definitions
 437  *
 438  * Boot Flags
 439  */
 440 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 441 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 442
 443 #endif  /* __CONFIG_H */