include/configs/TQM855M.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC855           1       /* This is a MPC855 CPU         */
  37 #define CONFIG_TQM855M          1       /* ...on a TQM8xxM module       */
  38
  39 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  40 #undef  CONFIG_8xx_CONS_SMC2
  41 #undef  CONFIG_8xx_CONS_NONE
  42
  43 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  44
  45 #define CONFIG_BOOTCOUNT_LIMIT
  46
  47 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  48
  49 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  50
  51 #define CONFIG_PREBOOT  "echo;" \
  52         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  53         "echo"
  54
  55 #undef  CONFIG_BOOTARGS
  56
  57 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  58         "netdev=eth0\0"                                                 \
  59         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  60                 "nfsroot=${serverip}:${rootpath}\0"                     \
  61         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  62         "addip=setenv bootargs ${bootargs} "                            \
  63                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  64                 ":${hostname}:${netdev}:off panic=1\0"                  \
  65         "flash_nfs=run nfsargs addip;"                                  \
  66                 "bootm ${kernel_addr}\0"                                \
  67         "flash_self=run ramargs addip;"                                 \
  68                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  69         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  70         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  71         "bootfile=/tftpboot/TQM855M/uImage\0"                           \
  72         "fdt_addr=40080000\0"                                           \
  73         "kernel_addr=400A0000\0"                                        \
  74         "ramdisk_addr=40280000\0"                                       \
  75         ""
  76 #define CONFIG_BOOTCOMMAND      "run flash_self"
  77
  78 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  79 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  80
  81 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  82
  83 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  84
  85 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  86
  87 /* enable I2C and select the hardware/software driver */
  88 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  89 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  90
  91 #define CFG_I2C_SPEED           93000   /* 93 kHz is supposed to work   */
  92 #define CFG_I2C_SLAVE           0xFE
  93
  94 #ifdef CONFIG_SOFT_I2C
  95 /*
  96  * Software (bit-bang) I2C driver configuration
  97  */
  98 #define PB_SCL          0x00000020      /* PB 26 */
  99 #define PB_SDA          0x00000010      /* PB 27 */
 100
 101 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 102 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 103 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 104 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 105 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 106                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 107 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 108                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 109 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 110 #endif  /* CONFIG_SOFT_I2C */
 111
 112 #define CFG_I2C_EEPROM_ADDR     0x50            /* EEPROM AT24C64       */
 113 #define CFG_I2C_EEPROM_ADDR_LEN 2               /* two byte address     */
 114 #if 0
 115 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* takes up to 10 msec  */
 116 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
 117 #define CFG_EEPROM_PAGE_WRITE_BITS      5
 118 #endif
 119
 120 /*
 121  * BOOTP options
 122  */
 123 #define CONFIG_BOOTP_SUBNETMASK
 124 #define CONFIG_BOOTP_GATEWAY
 125 #define CONFIG_BOOTP_HOSTNAME
 126 #define CONFIG_BOOTP_BOOTPATH
 127 #define CONFIG_BOOTP_BOOTFILESIZE
 128
 129
 130 #define CONFIG_MAC_PARTITION
 131 #define CONFIG_DOS_PARTITION
 132
 133 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 134
 135
 136 /*
 137  * Command line configuration.
 138  */
 139 #include <config_cmd_default.h>
 140
 141 #define CONFIG_CMD_ASKENV
 142 #define CONFIG_CMD_DATE
 143 #define CONFIG_CMD_DHCP
 144 #define CONFIG_CMD_EEPROM
 145 #define CONFIG_CMD_IDE
 146 #define CONFIG_CMD_NFS
 147 #define CONFIG_CMD_SNTP
 148
 149
 150 /*
 151  * Miscellaneous configurable options
 152  */
 153 #define CFG_LONGHELP                    /* undef to save memory         */
 154 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 155
 156 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 157 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 158 #ifdef  CFG_HUSH_PARSER
 159 #define CFG_PROMPT_HUSH_PS2     "> "
 160 #endif
 161
 162 #if defined(CONFIG_CMD_KGDB)
 163 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 164 #else
 165 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 166 #endif
 167 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 168 #define CFG_MAXARGS             16      /* max number of command args   */
 169 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 170
 171 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 172 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 173
 174 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 175
 176 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 177
 178 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 179
 180 /*
 181  * Low Level Configuration Settings
 182  * (address mappings, register initial values, etc.)
 183  * You should know what you are doing if you make changes here.
 184  */
 185 /*-----------------------------------------------------------------------
 186  * Internal Memory Mapped Register
 187  */
 188 #define CFG_IMMR                0xFFF00000
 189
 190 /*-----------------------------------------------------------------------
 191  * Definitions for initial stack pointer and data area (in DPRAM)
 192  */
 193 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 194 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 195 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 196 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 197 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 198
 199 /*-----------------------------------------------------------------------
 200  * Start addresses for the final memory configuration
 201  * (Set up by the startup code)
 202  * Please note that CFG_SDRAM_BASE _must_ start at 0
 203  */
 204 #define CFG_SDRAM_BASE          0x00000000
 205 #define CFG_FLASH_BASE          0x40000000
 206 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 207 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 208 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 209
 210 /*
 211  * For booting Linux, the board info and command line data
 212  * have to be in the first 8 MB of memory, since this is
 213  * the maximum mapped by the Linux kernel during initialization.
 214  */
 215 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 216
 217 /*-----------------------------------------------------------------------
 218  * FLASH organization
 219  */
 220 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 221 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 222
 223 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 224 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 225
 226 #define CFG_ENV_IS_IN_FLASH     1
 227 #define CFG_ENV_OFFSET          0x40000 /*   Offset   of Environment Sector     */
 228 #define CFG_ENV_SIZE            0x08000 /* Total Size of Environment Sector     */
 229 #define CFG_ENV_SECT_SIZE       0x20000 /* Total Size of Environment Sector     */
 230
 231 /* Address and size of Redundant Environment Sector     */
 232 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
 233 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 234
 235 /*-----------------------------------------------------------------------
 236  * Hardware Information Block
 237  */
 238 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 239 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 240 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 241
 242 /*-----------------------------------------------------------------------
 243  * Cache Configuration
 244  */
 245 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 246 #if defined(CONFIG_CMD_KGDB)
 247 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 248 #endif
 249
 250 /*-----------------------------------------------------------------------
 251  * SYPCR - System Protection Control                            11-9
 252  * SYPCR can only be written once after reset!
 253  *-----------------------------------------------------------------------
 254  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 255  */
 256 #if defined(CONFIG_WATCHDOG)
 257 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 258                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 259 #else
 260 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 261 #endif
 262
 263 /*-----------------------------------------------------------------------
 264  * SIUMCR - SIU Module Configuration                            11-6
 265  *-----------------------------------------------------------------------
 266  * PCMCIA config., multi-function pin tri-state
 267  */
 268 #ifndef CONFIG_CAN_DRIVER
 269 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 270 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 271 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 272 #endif  /* CONFIG_CAN_DRIVER */
 273
 274 /*-----------------------------------------------------------------------
 275  * TBSCR - Time Base Status and Control                         11-26
 276  *-----------------------------------------------------------------------
 277  * Clear Reference Interrupt Status, Timebase freezing enabled
 278  */
 279 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 280
 281 /*-----------------------------------------------------------------------
 282  * RTCSC - Real-Time Clock Status and Control Register          11-27
 283  *-----------------------------------------------------------------------
 284  */
 285 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 286
 287 /*-----------------------------------------------------------------------
 288  * PISCR - Periodic Interrupt Status and Control                11-31
 289  *-----------------------------------------------------------------------
 290  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 291  */
 292 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 293
 294 /*-----------------------------------------------------------------------
 295  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 296  *-----------------------------------------------------------------------
 297  * Reset PLL lock status sticky bit, timer expired status bit and timer
 298  * interrupt status bit
 299  */
 300 #define CFG_PLPRCR      (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 301
 302 /*-----------------------------------------------------------------------
 303  * SCCR - System Clock and reset Control Register               15-27
 304  *-----------------------------------------------------------------------
 305  * Set clock output, timebase and RTC source and divider,
 306  * power management and some other internal clocks
 307  */
 308 #define SCCR_MASK       SCCR_EBDF11
 309 #define CFG_SCCR        (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 310                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 311                          SCCR_DFALCD00)
 312
 313 /*-----------------------------------------------------------------------
 314  * PCMCIA stuff
 315  *-----------------------------------------------------------------------
 316  *
 317  */
 318 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 319 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 320 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 321 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 322 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 323 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 324 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 325 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 326
 327 /*-----------------------------------------------------------------------
 328  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 329  *-----------------------------------------------------------------------
 330  */
 331
 332 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 333
 334 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 335 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 336 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 337
 338 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 339 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 340
 341 #define CFG_ATA_IDE0_OFFSET     0x0000
 342
 343 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 344
 345 /* Offset for data I/O                  */
 346 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 347
 348 /* Offset for normal register accesses  */
 349 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 350
 351 /* Offset for alternate registers       */
 352 #define CFG_ATA_ALT_OFFSET      0x0100
 353
 354 /*-----------------------------------------------------------------------
 355  *
 356  *-----------------------------------------------------------------------
 357  *
 358  */
 359 #define CFG_DER 0
 360
 361 /*
 362  * Init Memory Controller:
 363  *
 364  * BR0/1 and OR0/1 (FLASH)
 365  */
 366
 367 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 368 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 369
 370 /* used to re-map FLASH both when starting from SRAM or FLASH:
 371  * restrict access enough to keep SRAM working (if any)
 372  * but not too much to meddle with FLASH accesses
 373  */
 374 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 375 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 376
 377 /*
 378  * FLASH timing:
 379  */
 380 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 381                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 382
 383 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 384 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 385 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 386
 387 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 388 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 389 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 390
 391 /*
 392  * BR2/3 and OR2/3 (SDRAM)
 393  *
 394  */
 395 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 396 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 397 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 398
 399 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 400 #define CFG_OR_TIMING_SDRAM     0x00000A00
 401
 402 #define CFG_OR2_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 403 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 404
 405 #ifndef CONFIG_CAN_DRIVER
 406 #define CFG_OR3_PRELIM  CFG_OR2_PRELIM
 407 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 408 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 409 #define CFG_CAN_BASE            0xC0000000      /* CAN mapped at 0xC0000000     */
 410 #define CFG_CAN_OR_AM           0xFFFF8000      /* 32 kB address mask           */
 411 #define CFG_OR3_CAN             (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
 412 #define CFG_BR3_CAN             ((CFG_CAN_BASE & BR_BA_MSK) | \
 413                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 414 #endif  /* CONFIG_CAN_DRIVER */
 415
 416 /*
 417  * Memory Periodic Timer Prescaler
 418  *
 419  * The Divider for PTA (refresh timer) configuration is based on an
 420  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 421  * the number of chip selects (NCS) and the actually needed refresh
 422  * rate is done by setting MPTPR.
 423  *
 424  * PTA is calculated from
 425  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 426  *
 427  *      gclk      CPU clock (not bus clock!)
 428  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 429  *
 430  * 4096  Rows from SDRAM example configuration
 431  * 1000  factor s -> ms
 432  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 433  *    4  Number of refresh cycles per period
 434  *   64  Refresh cycle in ms per number of rows
 435  * --------------------------------------------
 436  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 437  *
 438  * 50 MHz => 50.000.000 / Divider =  98
 439  * 66 Mhz => 66.000.000 / Divider = 129
 440  * 80 Mhz => 80.000.000 / Divider = 156
 441  */
 442
 443 #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
 444 #define CFG_MAMR_PTA    98
 445
 446 /*
 447  * For 16 MBit, refresh rates could be 31.3 us
 448  * (= 64 ms / 2K = 125 / quad bursts).
 449  * For a simpler initialization, 15.6 us is used instead.
 450  *
 451  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 452  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 453  */
 454 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 455 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 456
 457 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 458 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 459 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 460
 461 /*
 462  * MAMR settings for SDRAM
 463  */
 464
 465 /* 8 column SDRAM */
 466 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 467                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 468                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 469 /* 9 column SDRAM */
 470 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 471                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 472                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 473
 474
 475 /*
 476  * Internal Definitions
 477  *
 478  * Boot Flags
 479  */
 480 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 481 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 482
 483 #define CONFIG_SCC1_ENET
 484 #define CONFIG_FEC_ENET
 485 #define CONFIG_ETHPRIME         "SCC ETHERNET"
 486
 487 #endif  /* __CONFIG_H */