include/configs/TQM85xx.h

   1 /*
   2  * (C) Copyright 2007
   3  * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
   4  *
   5  * (C) Copyright 2005
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * Wolfgang Denk <wd@denx.de>
   9  * Copyright 2004 Freescale Semiconductor.
  10  * (C) Copyright 2002,2003 Motorola,Inc.
  11  * Xianghua Xiao <X.Xiao@motorola.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 /*
  33  * TQM85xx (8560/40/55/41/48) board configuration file
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_BOOKE            1       /* BOOKE                        */
  41 #define CONFIG_E500             1       /* BOOKE e500 family            */
  42 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41             */
  43
  44 #if defined(CONFIG_TQM8548_BE)
  45 #define CONFIG_TQM8548
  46 #endif
  47
  48 #define CONFIG_PCI
  49 #define CONFIG_PCI1                     /* PCI/PCI-X controller         */
  50 #ifdef CONFIG_TQM8548
  51 #define CONFIG_PCIE1                    /* PCI Express interface        */
  52 #endif
  53
  54 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code     */
  55 #define CONFIG_PCIX_CHECK               /* PCIX olny works at 66 MHz    */
  56 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata       */
  57
  58 #define CONFIG_TSEC_ENET                /* tsec ethernet support        */
  59
  60 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  61
  62  /*
  63  * Configuration for big NOR Flashes
  64  *
  65  * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
  66  * Please be aware, that this changes the whole memory map (new CCSRBAR
  67  * address, etc). You have to use an adapted Linux kernel or FDT blob
  68  * if this option is set.
  69  */
  70 #undef CONFIG_TQM_BIGFLASH
  71
  72 /*
  73  * NAND flash support (disabled by default)
  74  *
  75  * Warning: NAND support will likely increase the U-Boot image size
  76  * to more than 256 KB. Please adjust TEXT_BASE if necessary.
  77  */
  78 #ifdef CONFIG_TQM8548_BE
  79 #define CONFIG_NAND
  80 #endif
  81
  82 /*
  83  * MPC8540 and MPC8548 don't have CPM module
  84  */
  85 #if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
  86 #define CONFIG_CPM2             1       /* has CPM2                     */
  87 #endif
  88
  89 #define CONFIG_FSL_LAW          1       /* Use common FSL init code     */
  90
  91 #ifdef CONFIG_TQM8548_BE
  92 #define CONFIG_CAN_DRIVER               /* CAN Driver support           */
  93 #endif
  94
  95 /*
  96  * sysclk for MPC85xx
  97  *
  98  * Two valid values are:
  99  *    33333333
 100  *    66666666
 101  *
 102  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 103  * is likely the desired value here, so that is now the default.
 104  * The board, however, can run at 66MHz.  In any event, this value
 105  * must match the settings of some switches.  Details can be found
 106  * in the README.mpc85xxads.
 107  */
 108
 109 #ifndef CONFIG_SYS_CLK_FREQ
 110 #define CONFIG_SYS_CLK_FREQ     33333333
 111 #endif
 112
 113 /*
 114  * These can be toggled for performance analysis, otherwise use default.
 115  */
 116 #define CONFIG_L2_CACHE                 /* toggle L2 cache              */
 117 #define CONFIG_BTB                      /* toggle branch predition      */
 118
 119 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions      */
 120
 121 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time      */
 122 #define CONFIG_SYS_MEMTEST_START        0x00000000
 123 #define CONFIG_SYS_MEMTEST_END          0x10000000
 124
 125 /*
 126  * Base addresses -- Note these are effective addresses where the
 127  * actual resources get mapped (not physical addresses)
 128  */
 129 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xFF700000      /* CCSRBAR Default      */
 130 #ifdef CONFIG_TQM_BIGFLASH
 131 #define CONFIG_SYS_CCSRBAR              0xA0000000      /* relocated CCSRBAR    */
 132 #else /* !CONFIG_TQM_BIGFLASH */
 133 #define CONFIG_SYS_CCSRBAR              0xE0000000      /* relocated CCSRBAR    */
 134 #endif /* CONFIG_TQM_BIGFLASH */
 135 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
 136 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR    */
 137
 138 #define CONFIG_SYS_PCI1_ADDR            (CONFIG_SYS_CCSRBAR + 0x8000)
 139 #define CONFIG_SYS_PCI2_ADDR            (CONFIG_SYS_CCSRBAR + 0x9000)
 140 #define CONFIG_SYS_PCIE1_ADDR           (CONFIG_SYS_CCSRBAR + 0xa000)
 141
 142 /*
 143  * DDR Setup
 144  */
 145 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory */
 146 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 147
 148 #define CONFIG_NUM_DDR_CONTROLLERS      1
 149 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 150 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 151
 152 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
 153 /* TQM8540 & 8560 need DLL-override */
 154 #define CONFIG_DDR_DLL                          /* DLL fix needed       */
 155 #define CONFIG_DDR_DEFAULT_CL   25              /* CAS latency 2,5      */
 156 #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
 157
 158 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
 159     defined(CONFIG_TQM8548)
 160 #define CONFIG_DDR_DEFAULT_CL   30              /* CAS latency 3        */
 161 #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
 162
 163 /*
 164  * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM
 165  * series while new boards have 'N' type Flashes from the S29GLxxxN
 166  * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB.
 167  */
 168 #ifdef CONFIG_TQM8548
 169 #define CONFIG_TQM_FLASH_N_TYPE
 170 #endif /* CONFIG_TQM8548 */
 171
 172 /*
 173  * Flash on the Local Bus
 174  */
 175 #ifdef CONFIG_TQM_BIGFLASH
 176 #define CONFIG_SYS_FLASH0               0xE0000000
 177 #define CONFIG_SYS_FLASH1               0xC0000000
 178 #else /* !CONFIG_TQM_BIGFLASH */
 179 #define CONFIG_SYS_FLASH0               0xFC000000
 180 #define CONFIG_SYS_FLASH1               0xF8000000
 181 #endif /* CONFIG_TQM_BIGFLASH */
 182 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 183
 184 #define CONFIG_SYS_LBC_FLASH_BASE       CONFIG_SYS_FLASH1       /* Localbus flash start */
 185 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_LBC_FLASH_BASE  /* start of FLASH    */
 186
 187 /* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
 188  *
 189  * Note: According to timing specifications external addr latch delay
 190  * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
 191  *
 192  * For other Local Bus Clocks see following table:
 193  *
 194  * Clock/MHz   CONFIG_SYS_ORx_PRELIM
 195  * 166         0x.....CA5
 196  * 133         0x.....C85
 197  * 100         0x.....C65
 198  *  83         0x.....FA2
 199  *  66         0x.....C82
 200  *  50         0x.....C60
 201  *  42         0x.....040
 202  *  33         0x.....030
 203  *  25         0x.....020
 204  *
 205  */
 206 #ifdef CONFIG_TQM_BIGFLASH
 207 #define CONFIG_SYS_BR0_PRELIM           0xE0001801      /* port size 32bit      */
 208 #define CONFIG_SYS_OR0_PRELIM           0xE0000040      /* 512MB Flash          */
 209 #define CONFIG_SYS_BR1_PRELIM           0xC0001801      /* port size 32bit      */
 210 #define CONFIG_SYS_OR1_PRELIM           0xE0000040      /* 512MB Flash          */
 211 #else /* !CONFIG_TQM_BIGFLASH */
 212 #define CONFIG_SYS_BR0_PRELIM           0xfc001801      /* port size 32bit      */
 213 #define CONFIG_SYS_OR0_PRELIM           0xfc000040      /* 64MB Flash           */
 214 #define CONFIG_SYS_BR1_PRELIM           0xf8001801      /* port size 32bit      */
 215 #define CONFIG_SYS_OR1_PRELIM           0xfc000040      /* 64MB Flash           */
 216 #endif /* CONFIG_TQM_BIGFLASH */
 217
 218 #define CONFIG_SYS_FLASH_CFI                    /* flash is CFI compat.         */
 219 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 220 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector   */
 221 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash*/
 222 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1 /* speed up output to Flash   */
 223
 224 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks              */
 225 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device           */
 226 #undef  CONFIG_SYS_FLASH_CHECKSUM
 227 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms)     */
 228 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms)     */
 229
 230 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor     */
 231
 232 /*
 233  * Note: when changing the Local Bus clock divider you have to
 234  * change the timing values in CONFIG_SYS_ORx_PRELIM.
 235  *
 236  * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
 237  * LCRR[16:17] EADC  : External address delay cycles. It should be set to 2
 238  *                     for Local Bus Clock > 83.3 MHz.
 239  */
 240 #define CONFIG_SYS_LBC_LCRR             0x00030008      /* LB clock ratio reg   */
 241 #define CONFIG_SYS_LBC_LBCR             0x00000000      /* LB config reg        */
 242 #define CONFIG_SYS_LBC_LSRT             0x20000000      /* LB sdram refresh timer */
 243 #define CONFIG_SYS_LBC_MRTPR            0x20000000      /* LB refresh timer presc.*/
 244
 245 #define CONFIG_SYS_INIT_RAM_LOCK        1
 246 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_CCSRBAR \
 247                                  + 0x04010000)  /* Initial RAM address  */
 248 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End used area in RAM */
 249
 250 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data       */
 251 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 252 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 253
 254 #define CONFIG_SYS_MONITOR_LEN          (~TEXT_BASE + 1)/* Reserved for Monitor */
 255 #define CONFIG_SYS_MALLOC_LEN           (384 * 1024)    /* Reserved for malloc  */
 256
 257 /* Serial Port */
 258 #if defined(CONFIG_TQM8560)
 259
 260 #define CONFIG_CONS_ON_SCC      /* define if console on SCC             */
 261 #undef  CONFIG_CONS_NONE        /* define if console on something else  */
 262 #define CONFIG_CONS_INDEX       1 /* which serial channel for console   */
 263
 264 #else /* !CONFIG_TQM8560 */
 265
 266 #define CONFIG_CONS_INDEX     1
 267 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 268 #define CONFIG_SYS_NS16550
 269 #define CONFIG_SYS_NS16550_SERIAL
 270 #define CONFIG_SYS_NS16550_REG_SIZE     1
 271 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 272
 273 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 274 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 275
 276 /* PS/2 Keyboard */
 277 #define CONFIG_PS2KBD                   /* AT-PS/2 Keyboard             */
 278 #define CONFIG_PS2MULT                  /* .. on PS/2 Multiplexer       */
 279 #define CONFIG_PS2SERIAL        2       /* .. on DUART2                 */
 280 #define CONFIG_PS2MULT_DELAY    (CONFIG_SYS_HZ/2)       /* Initial delay        */
 281 #define CONFIG_BOARD_EARLY_INIT_R       1
 282
 283 #endif /* CONFIG_TQM8560 */
 284
 285 #define CONFIG_BAUDRATE         115200
 286
 287 #define CONFIG_SYS_BAUDRATE_TABLE       \
 288         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 289
 290 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 291 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 292 #ifdef  CONFIG_SYS_HUSH_PARSER
 293 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 294 #endif
 295
 296 /* pass open firmware flat tree */
 297 #define CONFIG_OF_LIBFDT                1
 298 #define CONFIG_OF_BOARD_SETUP           1
 299 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 300
 301 /* CAN */
 302 #define CONFIG_SYS_CAN_BASE             (CONFIG_SYS_CCSRBAR \
 303                                  + 0x03000000)  /* CAN base address     */
 304 #ifdef CONFIG_CAN_DRIVER
 305 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 KiB address mask  */
 306 #define CONFIG_SYS_OR2_CAN              (CONFIG_SYS_CAN_OR_AM | OR_UPM_BI)
 307 #define CONFIG_SYS_BR2_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA) | \
 308                                  BR_PS_8 | BR_MS_UPMC | BR_V)
 309 #endif /* CONFIG_CAN_DRIVER */
 310
 311 /*
 312  * I2C
 313  */
 314 #define CONFIG_FSL_I2C                  /* Use FSL common I2C driver    */
 315 #define CONFIG_HARD_I2C                 /* I2C with hardware support    */
 316 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 317 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 318 #define CONFIG_SYS_I2C_SLAVE            0x7F
 319 #define CONFIG_SYS_I2C_NOPROBES {0x48}  /* Don't probe these addrs      */
 320 #define CONFIG_SYS_I2C_OFFSET           0x3000
 321
 322 /* I2C RTC */
 323 #define CONFIG_RTC_DS1337               /* Use ds1337 rtc via i2c       */
 324 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68              */
 325
 326 /* I2C EEPROM */
 327 /*
 328  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
 329  */
 330 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x             */
 331 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 332 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* =32 Bytes per write  */
 333 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 334 #define CONFIG_SYS_I2C_MULTI_EEPROMS            1       /* more than one eeprom */
 335
 336 /* I2C SYSMON (LM75) */
 337 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 338 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 339 #define CONFIG_SYS_DTT_MAX_TEMP 70
 340 #define CONFIG_SYS_DTT_LOW_TEMP -30
 341 #define CONFIG_SYS_DTT_HYSTERESIS       3
 342
 343 #ifndef CONFIG_PCIE1
 344 /* RapidIO MMU */
 345 #ifdef CONFIG_TQM_BIGFLASH
 346 #define CONFIG_SYS_RIO_MEM_BASE 0xb0000000      /* base address         */
 347 #define CONFIG_SYS_RIO_MEM_SIZE 0x10000000      /* 256M                 */
 348 #else /* !CONFIG_TQM_BIGFLASH */
 349 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000      /* base address         */
 350 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 512M                 */
 351 #endif /* CONFIG_TQM_BIGFLASH */
 352 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
 353 #endif /* CONFIG_PCIE1 */
 354
 355 /* NAND FLASH */
 356 #ifdef CONFIG_NAND
 357
 358 #undef CONFIG_NAND_LEGACY
 359
 360 #define CONFIG_NAND_FSL_UPM     1
 361
 362 #define CONFIG_MTD_NAND_ECC_JFFS2       1       /* use JFFS2 ECC        */
 363
 364 /* address distance between chip selects */
 365 #define CONFIG_SYS_NAND_SELECT_DEVICE   1
 366 #define CONFIG_SYS_NAND_CS_DIST 0x200
 367
 368 #define CONFIG_SYS_NAND_SIZE            0x8000
 369 #define CONFIG_SYS_NAND0_BASE           (CONFIG_SYS_CCSRBAR + 0x03010000)
 370 #define CONFIG_SYS_NAND1_BASE           (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
 371 #define CONFIG_SYS_NAND2_BASE           (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
 372 #define CONFIG_SYS_NAND3_BASE           (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
 373
 374 #define CONFIG_SYS_MAX_NAND_DEVICE     2        /* Max number of NAND devices   */
 375
 376 #if (CONFIG_SYS_MAX_NAND_DEVICE == 1)
 377 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
 378 #elif (CONFIG_SYS_MAX_NAND_DEVICE == 2)
 379 #define CONFIG_SYS_NAND_QUIET_TEST      1
 380 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
 381                              CONFIG_SYS_NAND1_BASE, \
 382 }
 383 #elif (CONFIG_SYS_MAX_NAND_DEVICE == 4)
 384 #define CONFIG_SYS_NAND_QUIET_TEST      1
 385 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
 386                              CONFIG_SYS_NAND1_BASE, \
 387                              CONFIG_SYS_NAND2_BASE, \
 388                              CONFIG_SYS_NAND3_BASE, \
 389 }
 390 #endif
 391
 392 /* CS3 for NAND Flash */
 393 #define CONFIG_SYS_BR3_PRELIM           ((CONFIG_SYS_NAND0_BASE & BR_BA) | BR_PS_8 | \
 394                                  BR_MS_UPMB | BR_V)
 395 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
 396
 397 #define NAND_BIG_DELAY_US       25      /* max tR for Samsung devices   */
 398
 399 #endif /* CONFIG_NAND */
 400
 401 /*
 402  * General PCI
 403  * Addresses are mapped 1-1.
 404  */
 405 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 406 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 407 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M                 */
 408 #define CONFIG_SYS_PCI1_IO_BASE (CONFIG_SYS_CCSRBAR + 0x02000000)
 409 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
 410 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000       /*  16M                 */
 411
 412 #ifdef CONFIG_PCIE1
 413 /*
 414  * General PCI express
 415  * Addresses are mapped 1-1.
 416  */
 417 #ifdef CONFIG_TQM_BIGFLASH
 418 #define CONFIG_SYS_PCIE1_MEM_BASE       0xb0000000
 419 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 512M                 */
 420 #define CONFIG_SYS_PCIE1_IO_BASE        0xaf000000
 421 #else /* !CONFIG_TQM_BIGFLASH */
 422 #define CONFIG_SYS_PCIE1_MEM_BASE       0xc0000000
 423 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M                 */
 424 #define CONFIG_SYS_PCIE1_IO_BASE        0xef000000
 425 #endif /* CONFIG_TQM_BIGFLASH */
 426 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BASE
 427 #define CONFIG_SYS_PCIE1_IO_PHYS        CONFIG_SYS_PCIE1_IO_BASE
 428 #define CONFIG_SYS_PCIE1_IO_SIZE        0x1000000       /* 16M                  */
 429 #endif /* CONFIG_PCIE1 */
 430
 431 #if defined(CONFIG_PCI)
 432
 433 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 434
 435 #define CONFIG_EEPRO100
 436 #undef CONFIG_TULIP
 437
 438 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup  */
 439 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola                     */
 440
 441 #endif /* CONFIG_PCI */
 442
 443 #define CONFIG_NET_MULTI        1
 444
 445 #define CONFIG_MII              1       /* MII PHY management           */
 446 #define CONFIG_TSEC1    1
 447 #define CONFIG_TSEC1_NAME       "TSEC0"
 448 #define CONFIG_TSEC2    1
 449 #define CONFIG_TSEC2_NAME       "TSEC1"
 450 #define TSEC1_PHY_ADDR          2
 451 #define TSEC2_PHY_ADDR          1
 452 #define TSEC1_PHYIDX            0
 453 #define TSEC2_PHYIDX            0
 454 #define TSEC1_FLAGS             TSEC_GIGABIT
 455 #define TSEC2_FLAGS             TSEC_GIGABIT
 456 #define FEC_PHY_ADDR            3
 457 #define FEC_PHYIDX              0
 458 #define FEC_FLAGS               0
 459 #define CONFIG_HAS_ETH0
 460 #define CONFIG_HAS_ETH1
 461 #define CONFIG_HAS_ETH2
 462
 463 #ifdef CONFIG_TQM8548
 464 /*
 465  * TQM8548 has 4 ethernet ports. 4 ETSEC's.
 466  *
 467  * On the STK85xx Starterkit the ETSEC3/4 ports are on an
 468  * additional adapter (AIO) between module and Starterkit.
 469  */
 470 #define CONFIG_TSEC3    1
 471 #define CONFIG_TSEC3_NAME       "TSEC2"
 472 #define CONFIG_TSEC4    1
 473 #define CONFIG_TSEC4_NAME       "TSEC3"
 474 #define TSEC3_PHY_ADDR          4
 475 #define TSEC4_PHY_ADDR          5
 476 #define TSEC3_PHYIDX            0
 477 #define TSEC4_PHYIDX            0
 478 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 479 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 480 #define CONFIG_HAS_ETH3
 481 #define CONFIG_HAS_ETH4
 482 #endif  /* CONFIG_TQM8548 */
 483
 484 /* Options are TSEC[0-1], FEC */
 485 #define CONFIG_ETHPRIME         "TSEC0"
 486
 487 #if defined(CONFIG_TQM8540)
 488 /*
 489  * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
 490  * The FEC port is connected on the same signals as the FCC3 port
 491  * of the TQM8560 to the baseboard (STK85xx Starterkit).
 492  *
 493  * On the STK85xx Starterkit the X47/X50 jumper has to be set to
 494  * a - d (X50.2 - 3) to enable the FEC port.
 495  */
 496 #define CONFIG_MPC85XX_FEC      1
 497 #define CONFIG_MPC85XX_FEC_NAME "FEC"
 498 #endif
 499
 500 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
 501 /*
 502  * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
 503  * can be used at once, since only one FCC port is available on the STK85xx
 504  * Starterkit.
 505  *
 506  * To use this port you have to configure U-Boot to use the FCC port 1...2
 507  * and set the X47/X50 jumper to:
 508  * FCC1: a - b (X47.2 - X50.2)
 509  * FCC2: a - c (X50.2 - 1)
 510  */
 511 #define CONFIG_ETHER_ON_FCC
 512 #define CONFIG_ETHER_INDEX    1 /* FCC channel for ethernet     */
 513 #endif
 514
 515 #if defined(CONFIG_TQM8560)
 516 /*
 517  * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
 518  * can be used at once, since only one FCC port is available on the STK85xx
 519  * Starterkit.
 520  *
 521  * To use this port you have to configure U-Boot to use the FCC port 1...3
 522  * and set the X47/X50 jumper to:
 523  * FCC1: a - b (X47.2 - X50.2)
 524  * FCC2: a - c (X50.2 - 1)
 525  * FCC3: a - d (X50.2 - 3)
 526  */
 527 #define CONFIG_ETHER_ON_FCC
 528 #define CONFIG_ETHER_INDEX    3 /* FCC channel for ethernet     */
 529 #endif
 530
 531 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
 532 #define CONFIG_ETHER_ON_FCC1
 533 #define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
 534                                  CMXFCR_TF1CS_MSK)
 535 #define CONFIG_SYS_CMXFCR_VALUE1        (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
 536 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 537 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 538 #endif
 539
 540 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 541 #define CONFIG_ETHER_ON_FCC2
 542 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
 543                                  CMXFCR_TF2CS_MSK)
 544 #define CONFIG_SYS_CMXFCR_VALUE2        (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
 545 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 546 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 547 #endif
 548
 549 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 550 #define CONFIG_ETHER_ON_FCC3
 551 #define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
 552                                  CMXFCR_TF3CS_MSK)
 553 #define CONFIG_SYS_CMXFCR_VALUE3        (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
 554 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 555 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 556 #endif
 557
 558 /*
 559  * Environment
 560  */
 561 #define CONFIG_ENV_IS_IN_FLASH  1
 562
 563 #ifdef CONFIG_TQM_FLASH_N_TYPE
 564 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K (one sector) for env    */
 565 #else /* !CONFIG_TQM_FLASH_N_TYPE */
 566 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) for env    */
 567 #endif /* CONFIG_TQM_FLASH_N_TYPE */
 568 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 569 #define CONFIG_ENV_SIZE         0x2000
 570 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 571 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 572
 573 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 574 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 575
 576 #define CONFIG_TIMESTAMP        /* Print image info with ts     */
 577
 578 /*
 579  * BOOTP options
 580  */
 581 #define CONFIG_BOOTP_BOOTFILESIZE
 582 #define CONFIG_BOOTP_BOOTPATH
 583 #define CONFIG_BOOTP_GATEWAY
 584 #define CONFIG_BOOTP_HOSTNAME
 585
 586 #ifdef CONFIG_NAND
 587 /*
 588  * Use NAND-FLash as JFFS2 device
 589  */
 590 #define CONFIG_CMD_NAND
 591 #define CONFIG_CMD_JFFS2
 592
 593 #define CONFIG_JFFS2_NAND       1
 594
 595 #ifdef CONFIG_JFFS2_CMDLINE
 596 #define MTDIDS_DEFAULT          "nand0=TQM85xx-nand"
 597 #define MTDPARTS_DEFAULT        "mtdparts=TQM85xx-nand:-"
 598 #else
 599 #define CONFIG_JFFS2_DEV        "nand0" /* NAND device jffs2 lives on   */
 600 #define CONFIG_JFFS2_PART_OFFSET 0      /* start of jffs2 partition     */
 601 #define CONFIG_JFFS2_PART_SIZE  0x200000 /* size of jffs2 partition     */
 602 #endif /* CONFIG_JFFS2_CMDLINE */
 603
 604 #endif /* CONFIG_NAND */
 605
 606 /*
 607  * Command line configuration.
 608  */
 609 #include <config_cmd_default.h>
 610
 611 #define CONFIG_CMD_PING
 612 #define CONFIG_CMD_I2C
 613 #define CONFIG_CMD_DHCP
 614 #define CONFIG_CMD_NFS
 615 #define CONFIG_CMD_SNTP
 616 #define CONFIG_CMD_DATE
 617 #define CONFIG_CMD_EEPROM
 618 #define CONFIG_CMD_DTT
 619 #define CONFIG_CMD_MII
 620
 621 #if defined(CONFIG_PCI)
 622 #define CONFIG_CMD_PCI
 623 #endif
 624
 625 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 626
 627 /*
 628  * Miscellaneous configurable options
 629  */
 630 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 631 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address         */
 632 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 633
 634 #if defined(CONFIG_CMD_KGDB)
 635 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 636 #else
 637 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 638 #endif
 639
 640 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 641                          sizeof(CONFIG_SYS_PROMPT) + 16)   /* Print Buf Size    */
 642 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 643 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 644 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks  */
 645
 646 /*
 647  * For booting Linux, the board info and command line data
 648  * have to be in the first 8 MB of memory, since this is
 649  * the maximum mapped by the Linux kernel during initialization.
 650  */
 651 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux */
 652
 653 /*
 654  * Internal Definitions
 655  *
 656  * Boot Flags
 657  */
 658 #define BOOTFLAG_COLD   0x01            /* Power-On: Boot from FLASH    */
 659 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 660
 661 #if defined(CONFIG_CMD_KGDB)
 662 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port*/
 663 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use     */
 664 #endif
 665
 666 #define CONFIG_LOADADDR  200000         /* default addr for tftp & bootm*/
 667
 668 #define CONFIG_BOOTDELAY 5              /* -1 disables auto-boot        */
 669
 670 #define CONFIG_PREBOOT  "echo;" \
 671         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 672         "echo"
 673
 674 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 675
 676
 677 /*
 678  * Setup some board specific values for the default environment variables
 679  */
 680 #ifdef CONFIG_CPM2
 681 #define CONFIG_ENV_CONSDEV              "consdev=ttyCPM0\0"
 682 #else
 683 #define CONFIG_ENV_CONSDEV              "consdev=ttyS0\0"
 684 #endif
 685 #define CONFIG_ENV_FDT_FILE     "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
 686                                 MK_STR(CONFIG_HOSTNAME)".dtb\0"
 687 #define CONFIG_ENV_BOOTFILE     "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
 688 #define CONFIG_ENV_UBOOT                "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
 689                                 "uboot_addr="MK_STR(TEXT_BASE)"\0"
 690
 691 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 692         CONFIG_ENV_BOOTFILE                                             \
 693         CONFIG_ENV_FDT_FILE                                             \
 694         CONFIG_ENV_CONSDEV                                                      \
 695         "netdev=eth0\0"                                                 \
 696         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 697                 "nfsroot=$serverip:$rootpath\0"                         \
 698         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 699         "addip=setenv bootargs $bootargs "                              \
 700                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 701                 ":$hostname:$netdev:off panic=1\0"                      \
 702         "addcons=setenv bootargs $bootargs "                            \
 703                 "console=$consdev,$baudrate\0"                          \
 704         "flash_nfs=run nfsargs addip addcons;"                          \
 705                 "bootm $kernel_addr - $fdt_addr\0"                      \
 706         "flash_self=run ramargs addip addcons;"                         \
 707                 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0"          \
 708         "net_nfs=tftp $kernel_addr_r $bootfile;"                        \
 709                 "tftp $fdt_addr_r $fdt_file;"                           \
 710                 "run nfsargs addip addcons;"                            \
 711                 "bootm $kernel_addr_r - $fdt_addr_r\0"                  \
 712         "rootpath=/opt/eldk/ppc_85xx\0"                                 \
 713         "fdt_addr_r=900000\0"                                           \
 714         "kernel_addr_r=1000000\0"                                       \
 715         "fdt_addr=ffec0000\0"                                           \
 716         "kernel_addr=ffd00000\0"                                        \
 717         "ramdisk_addr=ff800000\0"                                       \
 718         CONFIG_ENV_UBOOT                                                        \
 719         "load=tftp 100000 $uboot\0"                                     \
 720         "update=protect off $uboot_addr +$filesize;"                    \
 721                 "erase $uboot_addr +$filesize;"                         \
 722                 "cp.b 100000 $uboot_addr $filesize;"                    \
 723                 "setenv filesize;saveenv\0"                             \
 724         "upd=run load update\0"                                         \
 725         ""
 726 #define CONFIG_BOOTCOMMAND      "run flash_self"
 727
 728 #endif /* __CONFIG_H */