include/configs/TQM85xx.h

   1 /*
   2  * (C) Copyright 2007
   3  * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
   4  *
   5  * (C) Copyright 2005
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * Wolfgang Denk <wd@denx.de>
   9  * Copyright 2004 Freescale Semiconductor.
  10  * (C) Copyright 2002,2003 Motorola,Inc.
  11  * Xianghua Xiao <X.Xiao@motorola.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 /*
  33  * TQM85xx (8560/40/55/41/48) board configuration file
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_BOOKE            1       /* BOOKE                        */
  41 #define CONFIG_E500             1       /* BOOKE e500 family            */
  42 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41             */
  43
  44 #define CONFIG_PCI
  45 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code     */
  46 #define CONFIG_PCIX_CHECK               /* PCIX olny works at 66 MHz    */
  47 #ifdef CONFIG_TQM8548
  48 #define CONFIG_PCI1
  49 #define CONFIG_PCIE1
  50 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata       */
  51 #endif
  52
  53 #define CONFIG_TSEC_ENET                /* tsec ethernet support        */
  54
  55 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  56
  57  /*
  58  * Configuration for big NOR Flashes
  59  *
  60  * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
  61  * Please be aware, that this changes the whole memory map (new CCSRBAR
  62  * address, etc). You have to use an adapted Linux kernel or FDT blob
  63  * if this option is set.
  64  */
  65 #undef CONFIG_TQM_BIGFLASH
  66
  67 /*
  68  * NAND flash support (disabled by default)
  69  *
  70  * Warning: NAND support will likely increase the U-Boot image size
  71  * to more than 256 KB. Please adjust TEXT_BASE if necessary.
  72  */
  73 #undef CONFIG_NAND
  74
  75 /*
  76  * MPC8540 and MPC8548 don't have CPM module
  77  */
  78 #if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
  79 #define CONFIG_CPM2             1       /* has CPM2                     */
  80 #endif
  81
  82 #define CONFIG_FSL_LAW          1       /* Use common FSL init code     */
  83
  84 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support           */
  85
  86 /*
  87  * sysclk for MPC85xx
  88  *
  89  * Two valid values are:
  90  *    33333333
  91  *    66666666
  92  *
  93  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  94  * is likely the desired value here, so that is now the default.
  95  * The board, however, can run at 66MHz.  In any event, this value
  96  * must match the settings of some switches.  Details can be found
  97  * in the README.mpc85xxads.
  98  */
  99
 100 #ifndef CONFIG_SYS_CLK_FREQ
 101 #define CONFIG_SYS_CLK_FREQ     33333333
 102 #endif
 103
 104 /*
 105  * These can be toggled for performance analysis, otherwise use default.
 106  */
 107 #define CONFIG_L2_CACHE                 /* toggle L2 cache              */
 108 #define CONFIG_BTB                      /* toggle branch predition      */
 109
 110 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions      */
 111
 112 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time      */
 113 #define CONFIG_SYS_MEMTEST_START        0x00000000
 114 #define CONFIG_SYS_MEMTEST_END          0x10000000
 115
 116 /*
 117  * Base addresses -- Note these are effective addresses where the
 118  * actual resources get mapped (not physical addresses)
 119  */
 120 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xFF700000      /* CCSRBAR Default      */
 121 #ifdef CONFIG_TQM_BIGFLASH
 122 #define CONFIG_SYS_CCSRBAR              0xA0000000      /* relocated CCSRBAR    */
 123 #else /* !CONFIG_TQM_BIGFLASH */
 124 #define CONFIG_SYS_CCSRBAR              0xE0000000      /* relocated CCSRBAR    */
 125 #endif /* CONFIG_TQM_BIGFLASH */
 126 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
 127 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR    */
 128
 129 #define CONFIG_SYS_PCI1_ADDR            (CONFIG_SYS_CCSRBAR + 0x8000)
 130 #define CONFIG_SYS_PCI2_ADDR            (CONFIG_SYS_CCSRBAR + 0x9000)
 131 #define CONFIG_SYS_PCIE1_ADDR           (CONFIG_SYS_CCSRBAR + 0xa000)
 132
 133 /*
 134  * DDR Setup
 135  */
 136 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory */
 137 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 138
 139 #define CONFIG_NUM_DDR_CONTROLLERS      1
 140 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 141 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 142
 143 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
 144 /* TQM8540 & 8560 need DLL-override */
 145 #define CONFIG_DDR_DLL                          /* DLL fix needed       */
 146 #define CONFIG_DDR_DEFAULT_CL   25              /* CAS latency 2,5      */
 147 #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
 148
 149 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
 150     defined(CONFIG_TQM8548)
 151 #define CONFIG_DDR_DEFAULT_CL   30              /* CAS latency 3        */
 152 #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
 153
 154 /*
 155  * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM
 156  * series while new boards have 'N' type Flashes from the S29GLxxxN
 157  * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB.
 158  */
 159 #ifdef CONFIG_TQM8548
 160 #define CONFIG_TQM_FLASH_N_TYPE
 161 #endif /* CONFIG_TQM8548 */
 162
 163 /*
 164  * Flash on the Local Bus
 165  */
 166 #ifdef CONFIG_TQM_BIGFLASH
 167 #define CONFIG_SYS_FLASH0               0xE0000000
 168 #define CONFIG_SYS_FLASH1               0xC0000000
 169 #else /* !CONFIG_TQM_BIGFLASH */
 170 #define CONFIG_SYS_FLASH0               0xFC000000
 171 #define CONFIG_SYS_FLASH1               0xF8000000
 172 #endif /* CONFIG_TQM_BIGFLASH */
 173 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 174
 175 #define CONFIG_SYS_LBC_FLASH_BASE       CONFIG_SYS_FLASH1       /* Localbus flash start */
 176 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_LBC_FLASH_BASE  /* start of FLASH    */
 177
 178 /* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
 179  *
 180  * Note: According to timing specifications external addr latch delay
 181  * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
 182  *
 183  * For other Local Bus Clocks see following table:
 184  *
 185  * Clock/MHz   CONFIG_SYS_ORx_PRELIM
 186  * 166         0x.....CA5
 187  * 133         0x.....C85
 188  * 100         0x.....C65
 189  *  83         0x.....FA2
 190  *  66         0x.....C82
 191  *  50         0x.....C60
 192  *  42         0x.....040
 193  *  33         0x.....030
 194  *  25         0x.....020
 195  *
 196  */
 197 #ifdef CONFIG_TQM_BIGFLASH
 198 #define CONFIG_SYS_BR0_PRELIM           0xE0001801      /* port size 32bit      */
 199 #define CONFIG_SYS_OR0_PRELIM           0xE0000040      /* 512MB Flash          */
 200 #define CONFIG_SYS_BR1_PRELIM           0xC0001801      /* port size 32bit      */
 201 #define CONFIG_SYS_OR1_PRELIM           0xE0000040      /* 512MB Flash          */
 202 #else /* !CONFIG_TQM_BIGFLASH */
 203 #define CONFIG_SYS_BR0_PRELIM           0xfc001801      /* port size 32bit      */
 204 #define CONFIG_SYS_OR0_PRELIM           0xfc000040      /* 64MB Flash           */
 205 #define CONFIG_SYS_BR1_PRELIM           0xf8001801      /* port size 32bit      */
 206 #define CONFIG_SYS_OR1_PRELIM           0xfc000040      /* 64MB Flash           */
 207 #endif /* CONFIG_TQM_BIGFLASH */
 208
 209 #define CONFIG_SYS_FLASH_CFI                    /* flash is CFI compat.         */
 210 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 211 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector   */
 212 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash*/
 213 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1 /* speed up output to Flash   */
 214
 215 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks              */
 216 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device           */
 217 #undef  CONFIG_SYS_FLASH_CHECKSUM
 218 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms)     */
 219 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms)     */
 220
 221 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor     */
 222
 223 /*
 224  * Note: when changing the Local Bus clock divider you have to
 225  * change the timing values in CONFIG_SYS_ORx_PRELIM.
 226  *
 227  * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
 228  * LCRR[16:17] EADC  : External address delay cycles. It should be set to 2
 229  *                     for Local Bus Clock > 83.3 MHz.
 230  */
 231 #define CONFIG_SYS_LBC_LCRR             0x00030008      /* LB clock ratio reg   */
 232 #define CONFIG_SYS_LBC_LBCR             0x00000000      /* LB config reg        */
 233 #define CONFIG_SYS_LBC_LSRT             0x20000000      /* LB sdram refresh timer */
 234 #define CONFIG_SYS_LBC_MRTPR            0x20000000      /* LB refresh timer presc.*/
 235
 236 #define CONFIG_SYS_INIT_RAM_LOCK        1
 237 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_CCSRBAR \
 238                                  + 0x04010000)  /* Initial RAM address  */
 239 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End used area in RAM */
 240
 241 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data       */
 242 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 243 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 244
 245 #define CONFIG_SYS_MONITOR_LEN          (~TEXT_BASE + 1)/* Reserved for Monitor */
 246 #define CONFIG_SYS_MALLOC_LEN           (384 * 1024)    /* Reserved for malloc  */
 247
 248 /* Serial Port */
 249 #if defined(CONFIG_TQM8560)
 250
 251 #define CONFIG_CONS_ON_SCC      /* define if console on SCC             */
 252 #undef  CONFIG_CONS_NONE        /* define if console on something else  */
 253 #define CONFIG_CONS_INDEX       1 /* which serial channel for console   */
 254
 255 #else /* !CONFIG_TQM8560 */
 256
 257 #define CONFIG_CONS_INDEX     1
 258 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 259 #define CONFIG_SYS_NS16550
 260 #define CONFIG_SYS_NS16550_SERIAL
 261 #define CONFIG_SYS_NS16550_REG_SIZE     1
 262 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 263
 264 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 265 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 266
 267 /* PS/2 Keyboard */
 268 #define CONFIG_PS2KBD                   /* AT-PS/2 Keyboard             */
 269 #define CONFIG_PS2MULT                  /* .. on PS/2 Multiplexer       */
 270 #define CONFIG_PS2SERIAL        2       /* .. on DUART2                 */
 271 #define CONFIG_PS2MULT_DELAY    (CONFIG_SYS_HZ/2)       /* Initial delay        */
 272 #define CONFIG_BOARD_EARLY_INIT_R       1
 273
 274 #endif /* CONFIG_TQM8560 */
 275
 276 #define CONFIG_BAUDRATE         115200
 277
 278 #define CONFIG_SYS_BAUDRATE_TABLE       \
 279         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 280
 281 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 282 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 283 #ifdef  CONFIG_SYS_HUSH_PARSER
 284 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 285 #endif
 286
 287 /* pass open firmware flat tree */
 288 #define CONFIG_OF_LIBFDT                1
 289 #define CONFIG_OF_BOARD_SETUP           1
 290 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 291
 292 /* CAN */
 293 #define CONFIG_SYS_CAN_BASE             (CONFIG_SYS_CCSRBAR \
 294                                  + 0x03000000)  /* CAN base address     */
 295 #ifdef CONFIG_CAN_DRIVER
 296 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 KiB address mask  */
 297 #define CONFIG_SYS_OR2_CAN              (CONFIG_SYS_CAN_OR_AM | OR_UPM_BI)
 298 #define CONFIG_SYS_BR2_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA) | \
 299                                  BR_PS_8 | BR_MS_UPMC | BR_V)
 300 #endif /* CONFIG_CAN_DRIVER */
 301
 302 /*
 303  * I2C
 304  */
 305 #define CONFIG_FSL_I2C                  /* Use FSL common I2C driver    */
 306 #define CONFIG_HARD_I2C                 /* I2C with hardware support    */
 307 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 308 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 309 #define CONFIG_SYS_I2C_SLAVE            0x7F
 310 #define CONFIG_SYS_I2C_NOPROBES {0x48}  /* Don't probe these addrs      */
 311 #define CONFIG_SYS_I2C_OFFSET           0x3000
 312
 313 /* I2C RTC */
 314 #define CONFIG_RTC_DS1337               /* Use ds1337 rtc via i2c       */
 315 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68              */
 316
 317 /* I2C EEPROM */
 318 /*
 319  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
 320  */
 321 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x             */
 322 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 323 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* =32 Bytes per write  */
 324 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 325 #define CONFIG_SYS_I2C_MULTI_EEPROMS            1       /* more than one eeprom */
 326
 327 /* I2C SYSMON (LM75) */
 328 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 329 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 330 #define CONFIG_SYS_DTT_MAX_TEMP 70
 331 #define CONFIG_SYS_DTT_LOW_TEMP -30
 332 #define CONFIG_SYS_DTT_HYSTERESIS       3
 333
 334 #ifndef CONFIG_PCIE1
 335 /* RapidIO MMU */
 336 #ifdef CONFIG_TQM_BIGFLASH
 337 #define CONFIG_SYS_RIO_MEM_BASE 0xb0000000      /* base address         */
 338 #define CONFIG_SYS_RIO_MEM_SIZE 0x10000000      /* 256M                 */
 339 #else /* !CONFIG_TQM_BIGFLASH */
 340 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000      /* base address         */
 341 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 512M                 */
 342 #endif /* CONFIG_TQM_BIGFLASH */
 343 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
 344 #endif /* CONFIG_PCIE1 */
 345
 346 /* NAND FLASH */
 347 #ifdef CONFIG_NAND
 348
 349 #undef CONFIG_NAND_LEGACY
 350
 351 #define CONFIG_NAND_FSL_UPM     1
 352
 353 #define CONFIG_MTD_NAND_ECC_JFFS2       1       /* use JFFS2 ECC        */
 354
 355 /* address distance between chip selects */
 356 #define CONFIG_SYS_NAND_SELECT_DEVICE   1
 357 #define CONFIG_SYS_NAND_CS_DIST 0x200
 358
 359 #define CONFIG_SYS_NAND_SIZE            0x8000
 360 #define CONFIG_SYS_NAND0_BASE           (CONFIG_SYS_CCSRBAR + 0x03010000)
 361 #define CONFIG_SYS_NAND1_BASE           (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
 362 #define CONFIG_SYS_NAND2_BASE           (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
 363 #define CONFIG_SYS_NAND3_BASE           (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
 364
 365 #define CONFIG_SYS_MAX_NAND_DEVICE     2        /* Max number of NAND devices   */
 366 #define NAND_MAX_CHIPS          1
 367
 368 #if (CONFIG_SYS_MAX_NAND_DEVICE == 1)
 369 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
 370 #elif (CONFIG_SYS_MAX_NAND_DEVICE == 2)
 371 #define CONFIG_SYS_NAND_QUIET_TEST      1
 372 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
 373                              CONFIG_SYS_NAND1_BASE, \
 374 }
 375 #elif (CONFIG_SYS_MAX_NAND_DEVICE == 4)
 376 #define CONFIG_SYS_NAND_QUIET_TEST      1
 377 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
 378                              CONFIG_SYS_NAND1_BASE, \
 379                              CONFIG_SYS_NAND2_BASE, \
 380                              CONFIG_SYS_NAND3_BASE, \
 381 }
 382 #endif
 383
 384 /* CS3 for NAND Flash */
 385 #define CONFIG_SYS_BR3_PRELIM           ((CONFIG_SYS_NAND0_BASE & BR_BA) | BR_PS_8 | \
 386                                  BR_MS_UPMB | BR_V)
 387 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
 388
 389 #define NAND_BIG_DELAY_US       25      /* max tR for Samsung devices   */
 390
 391 #endif /* CONFIG_NAND */
 392
 393 /*
 394  * General PCI
 395  * Addresses are mapped 1-1.
 396  */
 397 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 398 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 399 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M                 */
 400 #define CONFIG_SYS_PCI1_IO_BASE (CONFIG_SYS_CCSRBAR + 0x02000000)
 401 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
 402 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000       /*  16M                 */
 403
 404 #ifdef CONFIG_PCIE1
 405 /*
 406  * General PCI express
 407  * Addresses are mapped 1-1.
 408  */
 409 #ifdef CONFIG_TQM_BIGFLASH
 410 #define CONFIG_SYS_PCIE1_MEM_BASE       0xb0000000
 411 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 512M                 */
 412 #define CONFIG_SYS_PCIE1_IO_BASE        0xaf000000
 413 #else /* !CONFIG_TQM_BIGFLASH */
 414 #define CONFIG_SYS_PCIE1_MEM_BASE       0xc0000000
 415 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M                 */
 416 #define CONFIG_SYS_PCIE1_IO_BASE        0xef000000
 417 #endif /* CONFIG_TQM_BIGFLASH */
 418 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BASE
 419 #define CONFIG_SYS_PCIE1_IO_PHYS        CONFIG_SYS_PCIE1_IO_BASE
 420 #define CONFIG_SYS_PCIE1_IO_SIZE        0x1000000       /* 16M                  */
 421 #endif /* CONFIG_PCIE1 */
 422
 423 #if defined(CONFIG_PCI)
 424
 425 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 426
 427 #define CONFIG_EEPRO100
 428 #undef CONFIG_TULIP
 429
 430 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup  */
 431 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola                     */
 432
 433 #endif /* CONFIG_PCI */
 434
 435 #define CONFIG_NET_MULTI        1
 436
 437 #define CONFIG_MII              1       /* MII PHY management           */
 438 #define CONFIG_TSEC1    1
 439 #define CONFIG_TSEC1_NAME       "TSEC0"
 440 #define CONFIG_TSEC2    1
 441 #define CONFIG_TSEC2_NAME       "TSEC1"
 442 #define TSEC1_PHY_ADDR          2
 443 #define TSEC2_PHY_ADDR          1
 444 #define TSEC1_PHYIDX            0
 445 #define TSEC2_PHYIDX            0
 446 #define TSEC1_FLAGS             TSEC_GIGABIT
 447 #define TSEC2_FLAGS             TSEC_GIGABIT
 448 #define FEC_PHY_ADDR            3
 449 #define FEC_PHYIDX              0
 450 #define FEC_FLAGS               0
 451 #define CONFIG_HAS_ETH0
 452 #define CONFIG_HAS_ETH1
 453 #define CONFIG_HAS_ETH2
 454
 455 #ifdef CONFIG_TQM8548
 456 /*
 457  * TQM8548 has 4 ethernet ports. 4 ETSEC's.
 458  *
 459  * On the STK85xx Starterkit the ETSEC3/4 ports are on an
 460  * additional adapter (AIO) between module and Starterkit.
 461  */
 462 #define CONFIG_TSEC3    1
 463 #define CONFIG_TSEC3_NAME       "TSEC2"
 464 #define CONFIG_TSEC4    1
 465 #define CONFIG_TSEC4_NAME       "TSEC3"
 466 #define TSEC3_PHY_ADDR          4
 467 #define TSEC4_PHY_ADDR          5
 468 #define TSEC3_PHYIDX            0
 469 #define TSEC4_PHYIDX            0
 470 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 471 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 472 #define CONFIG_HAS_ETH3
 473 #define CONFIG_HAS_ETH4
 474 #endif  /* CONFIG_TQM8548 */
 475
 476 /* Options are TSEC[0-1], FEC */
 477 #define CONFIG_ETHPRIME         "TSEC0"
 478
 479 #if defined(CONFIG_TQM8540)
 480 /*
 481  * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
 482  * The FEC port is connected on the same signals as the FCC3 port
 483  * of the TQM8560 to the baseboard (STK85xx Starterkit).
 484  *
 485  * On the STK85xx Starterkit the X47/X50 jumper has to be set to
 486  * a - d (X50.2 - 3) to enable the FEC port.
 487  */
 488 #define CONFIG_MPC85XX_FEC      1
 489 #define CONFIG_MPC85XX_FEC_NAME "FEC"
 490 #endif
 491
 492 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
 493 /*
 494  * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
 495  * can be used at once, since only one FCC port is available on the STK85xx
 496  * Starterkit.
 497  *
 498  * To use this port you have to configure U-Boot to use the FCC port 1...2
 499  * and set the X47/X50 jumper to:
 500  * FCC1: a - b (X47.2 - X50.2)
 501  * FCC2: a - c (X50.2 - 1)
 502  */
 503 #define CONFIG_ETHER_ON_FCC
 504 #define CONFIG_ETHER_INDEX    1 /* FCC channel for ethernet     */
 505 #endif
 506
 507 #if defined(CONFIG_TQM8560)
 508 /*
 509  * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
 510  * can be used at once, since only one FCC port is available on the STK85xx
 511  * Starterkit.
 512  *
 513  * To use this port you have to configure U-Boot to use the FCC port 1...3
 514  * and set the X47/X50 jumper to:
 515  * FCC1: a - b (X47.2 - X50.2)
 516  * FCC2: a - c (X50.2 - 1)
 517  * FCC3: a - d (X50.2 - 3)
 518  */
 519 #define CONFIG_ETHER_ON_FCC
 520 #define CONFIG_ETHER_INDEX    3 /* FCC channel for ethernet     */
 521 #endif
 522
 523 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
 524 #define CONFIG_ETHER_ON_FCC1
 525 #define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
 526                                  CMXFCR_TF1CS_MSK)
 527 #define CONFIG_SYS_CMXFCR_VALUE1        (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
 528 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 529 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 530 #endif
 531
 532 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 533 #define CONFIG_ETHER_ON_FCC2
 534 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
 535                                  CMXFCR_TF2CS_MSK)
 536 #define CONFIG_SYS_CMXFCR_VALUE2        (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
 537 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 538 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 539 #endif
 540
 541 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 542 #define CONFIG_ETHER_ON_FCC3
 543 #define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
 544                                  CMXFCR_TF3CS_MSK)
 545 #define CONFIG_SYS_CMXFCR_VALUE3        (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
 546 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 547 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 548 #endif
 549
 550 /*
 551  * Environment
 552  */
 553 #define CONFIG_ENV_IS_IN_FLASH  1
 554
 555 #ifdef CONFIG_TQM_FLASH_N_TYPE
 556 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K (one sector) for env    */
 557 #else /* !CONFIG_TQM_FLASH_N_TYPE */
 558 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) for env    */
 559 #endif /* CONFIG_TQM_FLASH_N_TYPE */
 560 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 561 #define CONFIG_ENV_SIZE         0x2000
 562 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 563 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 564
 565 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 566 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 567
 568 #define CONFIG_TIMESTAMP        /* Print image info with ts     */
 569
 570 /*
 571  * BOOTP options
 572  */
 573 #define CONFIG_BOOTP_BOOTFILESIZE
 574 #define CONFIG_BOOTP_BOOTPATH
 575 #define CONFIG_BOOTP_GATEWAY
 576 #define CONFIG_BOOTP_HOSTNAME
 577
 578 #ifdef CONFIG_NAND
 579 /*
 580  * Use NAND-FLash as JFFS2 device
 581  */
 582 #define CONFIG_CMD_NAND
 583 #define CONFIG_CMD_JFFS2
 584
 585 #define CONFIG_JFFS2_NAND       1
 586
 587 #ifdef CONFIG_JFFS2_CMDLINE
 588 #define MTDIDS_DEFAULT          "nand0=TQM85xx-nand"
 589 #define MTDPARTS_DEFAULT        "mtdparts=TQM85xx-nand:-"
 590 #else
 591 #define CONFIG_JFFS2_DEV        "nand0" /* NAND device jffs2 lives on   */
 592 #define CONFIG_JFFS2_PART_OFFSET 0      /* start of jffs2 partition     */
 593 #define CONFIG_JFFS2_PART_SIZE  0x200000 /* size of jffs2 partition     */
 594 #endif /* CONFIG_JFFS2_CMDLINE */
 595
 596 #endif /* CONFIG_NAND */
 597
 598 /*
 599  * Command line configuration.
 600  */
 601 #include <config_cmd_default.h>
 602
 603 #define CONFIG_CMD_PING
 604 #define CONFIG_CMD_I2C
 605 #define CONFIG_CMD_DHCP
 606 #define CONFIG_CMD_NFS
 607 #define CONFIG_CMD_SNTP
 608 #define CONFIG_CMD_DATE
 609 #define CONFIG_CMD_EEPROM
 610 #define CONFIG_CMD_DTT
 611 #define CONFIG_CMD_MII
 612
 613 #if defined(CONFIG_PCI)
 614 #define CONFIG_CMD_PCI
 615 #endif
 616
 617 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 618
 619 /*
 620  * Miscellaneous configurable options
 621  */
 622 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 623 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address         */
 624 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 625
 626 #if defined(CONFIG_CMD_KGDB)
 627 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 628 #else
 629 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 630 #endif
 631
 632 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 633                          sizeof(CONFIG_SYS_PROMPT) + 16)   /* Print Buf Size    */
 634 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 635 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 636 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks  */
 637
 638 /*
 639  * For booting Linux, the board info and command line data
 640  * have to be in the first 8 MB of memory, since this is
 641  * the maximum mapped by the Linux kernel during initialization.
 642  */
 643 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux */
 644
 645 /*
 646  * Internal Definitions
 647  *
 648  * Boot Flags
 649  */
 650 #define BOOTFLAG_COLD   0x01            /* Power-On: Boot from FLASH    */
 651 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 652
 653 #if defined(CONFIG_CMD_KGDB)
 654 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port*/
 655 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use     */
 656 #endif
 657
 658 #define CONFIG_LOADADDR  200000         /* default addr for tftp & bootm*/
 659
 660 #define CONFIG_BOOTDELAY 5              /* -1 disables auto-boot        */
 661
 662 #define CONFIG_PREBOOT  "echo;" \
 663         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 664         "echo"
 665
 666 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 667
 668
 669 /*
 670  * Setup some board specific values for the default environment variables
 671  */
 672 #ifdef CONFIG_CPM2
 673 #define CONFIG_ENV_CONSDEV              "consdev=ttyCPM0\0"
 674 #else
 675 #define CONFIG_ENV_CONSDEV              "consdev=ttyS0\0"
 676 #endif
 677 #define CONFIG_ENV_FDT_FILE     "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
 678                                 MK_STR(CONFIG_HOSTNAME)".dtb\0"
 679 #define CONFIG_ENV_BOOTFILE     "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
 680 #define CONFIG_ENV_UBOOT                "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
 681                                 "uboot_addr="MK_STR(TEXT_BASE)"\0"
 682
 683 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 684         CONFIG_ENV_BOOTFILE                                             \
 685         CONFIG_ENV_FDT_FILE                                             \
 686         CONFIG_ENV_CONSDEV                                                      \
 687         "netdev=eth0\0"                                                 \
 688         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 689                 "nfsroot=$serverip:$rootpath\0"                         \
 690         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 691         "addip=setenv bootargs $bootargs "                              \
 692                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 693                 ":$hostname:$netdev:off panic=1\0"                      \
 694         "addcons=setenv bootargs $bootargs "                            \
 695                 "console=$consdev,$baudrate\0"                          \
 696         "flash_nfs=run nfsargs addip addcons;"                          \
 697                 "bootm $kernel_addr - $fdt_addr\0"                      \
 698         "flash_self=run ramargs addip addcons;"                         \
 699                 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0"          \
 700         "net_nfs=tftp $kernel_addr_r $bootfile;"                        \
 701                 "tftp $fdt_addr_r $fdt_file;"                           \
 702                 "run nfsargs addip addcons;"                            \
 703                 "bootm $kernel_addr_r - $fdt_addr_r\0"                  \
 704         "rootpath=/opt/eldk/ppc_85xx\0"                                 \
 705         "fdt_addr_r=900000\0"                                           \
 706         "kernel_addr_r=1000000\0"                                       \
 707         "fdt_addr=ffec0000\0"                                           \
 708         "kernel_addr=ffd00000\0"                                        \
 709         "ramdisk_addr=ff800000\0"                                       \
 710         CONFIG_ENV_UBOOT                                                        \
 711         "load=tftp 100000 $uboot\0"                                     \
 712         "update=protect off $uboot_addr +$filesize;"                    \
 713                 "erase $uboot_addr +$filesize;"                         \
 714                 "cp.b 100000 $uboot_addr $filesize;"                    \
 715                 "setenv filesize;saveenv\0"                             \
 716         "upd=run load update\0"                                         \
 717         ""
 718 #define CONFIG_BOOTCOMMAND      "run flash_self"
 719
 720 #endif /* __CONFIG_H */