include/configs/TQM85xx.h

   1 /*
   2  * (C) Copyright 2007
   3  * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
   4  *
   5  * (C) Copyright 2005
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * Wolfgang Denk <wd@denx.de>
   9  * Copyright 2004 Freescale Semiconductor.
  10  * (C) Copyright 2002,2003 Motorola,Inc.
  11  * Xianghua Xiao <X.Xiao@motorola.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 /*
  33  * TQM85xx (8560/40/55/41/48) board configuration file
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_BOOKE            1       /* BOOKE                        */
  41 #define CONFIG_E500             1       /* BOOKE e500 family            */
  42 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41             */
  43
  44 #define CONFIG_PCI
  45 #define CONFIG_TSEC_ENET                /* tsec ethernet support        */
  46
  47 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  48
  49 /*
  50  * MPC8540 and MPC8548 don't have CPM module
  51  */
  52 #if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
  53 #define CONFIG_CPM2             1       /* has CPM2                     */
  54 #endif
  55
  56 #define CONFIG_FSL_LAW          1       /* Use common FSL init code     */
  57
  58 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support           */
  59
  60 /*
  61  * sysclk for MPC85xx
  62  *
  63  * Two valid values are:
  64  *    33333333
  65  *    66666666
  66  *
  67  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  68  * is likely the desired value here, so that is now the default.
  69  * The board, however, can run at 66MHz.  In any event, this value
  70  * must match the settings of some switches.  Details can be found
  71  * in the README.mpc85xxads.
  72  */
  73
  74 #ifndef CONFIG_SYS_CLK_FREQ
  75 #define CONFIG_SYS_CLK_FREQ     33333333
  76 #endif
  77
  78 /*
  79  * These can be toggled for performance analysis, otherwise use default.
  80  */
  81 #define CONFIG_L2_CACHE                 /* toggle L2 cache              */
  82 #define CONFIG_BTB                      /* toggle branch predition      */
  83 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming        */
  84
  85 #define CFG_INIT_DBCR DBCR_IDM          /* Enable Debug Exceptions      */
  86
  87 #undef  CFG_DRAM_TEST                   /* memory test, takes time      */
  88 #define CFG_MEMTEST_START       0x00000000
  89 #define CFG_MEMTEST_END         0x10000000
  90
  91 /*
  92  * Base addresses -- Note these are effective addresses where the
  93  * actual resources get mapped (not physical addresses)
  94  */
  95 #define CFG_CCSRBAR_DEFAULT     0xFF700000      /* CCSRBAR Default      */
  96 #define CFG_CCSRBAR             0xE0000000      /* relocated CCSRBAR    */
  97 #define CFG_CCSRBAR_PHYS        CFG_CCSRBAR     /* physical addr of CCSRBAR */
  98 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR   */
  99
 100 /*
 101  * DDR Setup
 102  */
 103 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory */
 104 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 105
 106 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
 107 /* TQM8540 & 8560 need DLL-override */
 108 #define CONFIG_DDR_DLL                          /* DLL fix needed       */
 109 #define CONFIG_DDR_DEFAULT_CL   25              /* CAS latency 2,5      */
 110 #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
 111
 112 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
 113     defined(CONFIG_TQM8548)
 114 #define CONFIG_DDR_DEFAULT_CL   30              /* CAS latency 3        */
 115 #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
 116
 117 /*
 118  * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM
 119  * series while new boards have 'N' type Flashes from the S29GLxxxN
 120  * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB.
 121  */
 122 #ifdef CONFIG_TQM8548
 123 #define CONFIG_TQM_FLASH_N_TYPE
 124 #endif /* CONFIG_TQM8548 */
 125
 126 /*
 127  * Flash on the Local Bus
 128  */
 129 #define CFG_FLASH0              0xFC000000
 130 #define CFG_FLASH1              0xF8000000
 131 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH1, CFG_FLASH0 }
 132
 133 #define CFG_LBC_FLASH_BASE      CFG_FLASH1      /* Localbus flash start */
 134 #define CFG_FLASH_BASE          CFG_LBC_FLASH_BASE  /* start of FLASH   */
 135
 136 /* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
 137  *
 138  * Note: According to timing specifications external addr latch delay
 139  * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
 140  *
 141  * For other Local Bus Clocks see following table:
 142  *
 143  * Clock/MHz   CFG_ORx_PRELIM
 144  * 166         0x.....CA5
 145  * 133         0x.....C85
 146  * 100         0x.....C65
 147  *  83         0x.....FA2
 148  *  66         0x.....C82
 149  *  50         0x.....C60
 150  *  42         0x.....040
 151  *  33         0x.....030
 152  *  25         0x.....020
 153  *
 154  */
 155 #define CFG_BR0_PRELIM          0xfc001801      /* port size 32bit      */
 156 #define CFG_OR0_PRELIM          0xfc000040      /* 64MB Flash           */
 157 #define CFG_BR1_PRELIM          0xf8001801      /* port size 32bit      */
 158 #define CFG_OR1_PRELIM          0xfc000040      /* 64MB Flash           */
 159
 160 #define CFG_FLASH_CFI                   /* flash is CFI compat.         */
 161 #define CFG_FLASH_CFI_DRIVER            /* Use common CFI driver        */
 162 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector   */
 163 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash*/
 164 #define CFG_FLASH_USE_BUFFER_WRITE      1 /* speed up output to Flash   */
 165
 166 #define CFG_MAX_FLASH_BANKS     2       /* number of banks              */
 167 #define CFG_MAX_FLASH_SECT      512     /* sectors per device           */
 168 #undef  CFG_FLASH_CHECKSUM
 169 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms)     */
 170 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms)     */
 171
 172 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor     */
 173
 174 /*
 175  * Note: when changing the Local Bus clock divider you have to
 176  * change the timing values in CFG_ORx_PRELIM.
 177  *
 178  * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
 179  * LCRR[16:17] EADC  : External address delay cycles. It should be set to 2
 180  *                     for Local Bus Clock > 83.3 MHz.
 181  */
 182 #define CFG_LBC_LCRR            0x00030008      /* LB clock ratio reg   */
 183 #define CFG_LBC_LBCR            0x00000000      /* LB config reg        */
 184 #define CFG_LBC_LSRT            0x20000000      /* LB sdram refresh timer */
 185 #define CFG_LBC_MRTPR           0x20000000      /* LB refresh timer presc.*/
 186
 187 #define CONFIG_L1_INIT_RAM
 188 #define CFG_INIT_RAM_LOCK       1
 189 #define CFG_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address  */
 190 #define CFG_INIT_RAM_END        0x4000          /* End used area in RAM */
 191
 192 #define CFG_GBL_DATA_SIZE       128     /* num bytes initial data       */
 193 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 194 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 195
 196 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256kB for Mon */
 197 #define CFG_MALLOC_LEN          (256 * 1024)    /* Reserved for malloc  */
 198
 199 /* Serial Port */
 200 #if defined(CONFIG_TQM8560)
 201
 202 #define CONFIG_CONS_ON_SCC      /* define if console on SCC             */
 203 #undef  CONFIG_CONS_NONE        /* define if console on something else  */
 204 #define CONFIG_CONS_INDEX       1 /* which serial channel for console   */
 205
 206 #else /* !CONFIG_TQM8560 */
 207
 208 #define CONFIG_CONS_INDEX     1
 209 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 210 #define CFG_NS16550
 211 #define CFG_NS16550_SERIAL
 212 #define CFG_NS16550_REG_SIZE    1
 213 #define CFG_NS16550_CLK         get_bus_freq(0)
 214
 215 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 216 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 217
 218 /* PS/2 Keyboard */
 219 #define CONFIG_PS2KBD                   /* AT-PS/2 Keyboard             */
 220 #define CONFIG_PS2MULT                  /* .. on PS/2 Multiplexer       */
 221 #define CONFIG_PS2SERIAL        2       /* .. on DUART2                 */
 222 #define CONFIG_PS2MULT_DELAY    (CFG_HZ/2)      /* Initial delay        */
 223 #define CONFIG_BOARD_EARLY_INIT_R       1
 224
 225 #endif /* CONFIG_TQM8560 */
 226
 227 #define CONFIG_BAUDRATE         115200
 228
 229 #define CFG_BAUDRATE_TABLE      \
 230         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 231
 232 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 233 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 234 #ifdef  CFG_HUSH_PARSER
 235 #define CFG_PROMPT_HUSH_PS2     "> "
 236 #endif
 237
 238 /* pass open firmware flat tree */
 239 #define CONFIG_OF_LIBFDT                1
 240 #define CONFIG_OF_BOARD_SETUP           1
 241 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 242
 243 /* CAN */
 244 #ifdef CONFIG_CAN_DRIVER
 245 #define CFG_CAN_BASE            0xE3000000      /* CAN base address     */
 246 #define CFG_CAN_OR_AM           0xFFFF8000      /* 32 KiB address mask  */
 247 #define CFG_OR2_CAN             (CFG_CAN_OR_AM | OR_UPM_BI)
 248 #define CFG_BR2_CAN             ((CFG_CAN_BASE & BR_BA) | \
 249                                  BR_PS_8 | BR_MS_UPMC | BR_V)
 250 #endif /* CONFIG_CAN_DRIVER */
 251
 252 /*
 253  * I2C
 254  */
 255 #define CONFIG_FSL_I2C                  /* Use FSL common I2C driver    */
 256 #define CONFIG_HARD_I2C                 /* I2C with hardware support    */
 257 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 258 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 259 #define CFG_I2C_SLAVE           0x7F
 260 #define CFG_I2C_NOPROBES        {0x48}  /* Don't probe these addrs      */
 261 #define CFG_I2C_OFFSET          0x3000
 262
 263 /* I2C RTC */
 264 #define CONFIG_RTC_DS1337               /* Use ds1337 rtc via i2c       */
 265 #define CFG_I2C_RTC_ADDR        0x68    /* at address 0x68              */
 266
 267 /* I2C EEPROM */
 268 /*
 269  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
 270  */
 271 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x             */
 272 #define CFG_I2C_EEPROM_ADDR_LEN         2
 273 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write  */
 274 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 275 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 276 #define CFG_I2C_MULTI_EEPROMS           1       /* more than one eeprom */
 277
 278 /* I2C SYSMON (LM75) */
 279 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 280 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 281 #define CFG_DTT_MAX_TEMP        70
 282 #define CFG_DTT_LOW_TEMP        -30
 283 #define CFG_DTT_HYSTERESIS      3
 284
 285 /* RapidIO MMU */
 286 #define CFG_RIO_MEM_BASE        0xc0000000      /* base address         */
 287 #define CFG_RIO_MEM_PHYS        CFG_RIO_MEM_BASE
 288 #define CFG_RIO_MEM_SIZE        0x20000000      /* 128M                 */
 289
 290 /*
 291  * General PCI
 292  * Addresses are mapped 1-1.
 293  */
 294 #define CFG_PCI1_MEM_BASE       0x80000000
 295 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 296 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M                 */
 297 #define CFG_PCI1_IO_BASE        0xe2000000
 298 #define CFG_PCI1_IO_PHYS        CFG_PCI1_IO_BASE
 299 #define CFG_PCI1_IO_SIZE        0x1000000       /*  16M                 */
 300
 301 #if defined(CONFIG_PCI)
 302
 303 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 304
 305 #define CONFIG_EEPRO100
 306 #undef CONFIG_TULIP
 307
 308 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup  */
 309 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola                     */
 310
 311 #endif /* CONFIG_PCI */
 312
 313 #define CONFIG_NET_MULTI        1
 314
 315 #define CONFIG_MII              1       /* MII PHY management           */
 316 #define CONFIG_TSEC1    1
 317 #define CONFIG_TSEC1_NAME       "TSEC0"
 318 #define CONFIG_TSEC2    1
 319 #define CONFIG_TSEC2_NAME       "TSEC1"
 320 #define TSEC1_PHY_ADDR          2
 321 #define TSEC2_PHY_ADDR          1
 322 #define TSEC1_PHYIDX            0
 323 #define TSEC2_PHYIDX            0
 324 #define TSEC1_FLAGS             TSEC_GIGABIT
 325 #define TSEC2_FLAGS             TSEC_GIGABIT
 326 #define FEC_PHY_ADDR            3
 327 #define FEC_PHYIDX              0
 328 #define FEC_FLAGS               0
 329 #define CONFIG_HAS_ETH0
 330 #define CONFIG_HAS_ETH1
 331 #define CONFIG_HAS_ETH2
 332
 333 #ifdef CONFIG_TQM8548
 334 /*
 335  * TQM8548 has 4 ethernet ports. 4 ETSEC's.
 336  *
 337  * On the STK85xx Starterkit the ETSEC3/4 ports are on an
 338  * additional adapter (AIO) between module and Starterkit.
 339  */
 340 #define CONFIG_TSEC3    1
 341 #define CONFIG_TSEC3_NAME       "TSEC2"
 342 #define CONFIG_TSEC4    1
 343 #define CONFIG_TSEC4_NAME       "TSEC3"
 344 #define TSEC3_PHY_ADDR          4
 345 #define TSEC4_PHY_ADDR          5
 346 #define TSEC3_PHYIDX            0
 347 #define TSEC4_PHYIDX            0
 348 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 349 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 350 #define CONFIG_HAS_ETH3
 351 #define CONFIG_HAS_ETH4
 352 #endif  /* CONFIG_TQM8548 */
 353
 354 /* Options are TSEC[0-1], FEC */
 355 #define CONFIG_ETHPRIME         "TSEC0"
 356
 357 #if defined(CONFIG_TQM8540)
 358 /*
 359  * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
 360  * The FEC port is connected on the same signals as the FCC3 port
 361  * of the TQM8560 to the baseboard (STK85xx Starterkit).
 362  *
 363  * On the STK85xx Starterkit the X47/X50 jumper has to be set to
 364  * a - d (X50.2 - 3) to enable the FEC port.
 365  */
 366 #define CONFIG_MPC85XX_FEC      1
 367 #define CONFIG_MPC85XX_FEC_NAME "FEC"
 368 #endif
 369
 370 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
 371 /*
 372  * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
 373  * can be used at once, since only one FCC port is available on the STK85xx
 374  * Starterkit.
 375  *
 376  * To use this port you have to configure U-Boot to use the FCC port 1...2
 377  * and set the X47/X50 jumper to:
 378  * FCC1: a - b (X47.2 - X50.2)
 379  * FCC2: a - c (X50.2 - 1)
 380  */
 381 #define CONFIG_ETHER_ON_FCC
 382 #define CONFIG_ETHER_INDEX    1 /* FCC channel for ethernet     */
 383 #endif
 384
 385 #if defined(CONFIG_TQM8560)
 386 /*
 387  * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
 388  * can be used at once, since only one FCC port is available on the STK85xx
 389  * Starterkit.
 390  *
 391  * To use this port you have to configure U-Boot to use the FCC port 1...3
 392  * and set the X47/X50 jumper to:
 393  * FCC1: a - b (X47.2 - X50.2)
 394  * FCC2: a - c (X50.2 - 1)
 395  * FCC3: a - d (X50.2 - 3)
 396  */
 397 #define CONFIG_ETHER_ON_FCC
 398 #define CONFIG_ETHER_INDEX    3 /* FCC channel for ethernet     */
 399 #endif
 400
 401 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
 402 #define CONFIG_ETHER_ON_FCC1
 403 #define CFG_CMXFCR_MASK1        (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
 404                                  CMXFCR_TF1CS_MSK)
 405 #define CFG_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
 406 #define CFG_CPMFCR_RAMTYPE      0
 407 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 408 #endif
 409
 410 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 411 #define CONFIG_ETHER_ON_FCC2
 412 #define CFG_CMXFCR_MASK2        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
 413                                  CMXFCR_TF2CS_MSK)
 414 #define CFG_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
 415 #define CFG_CPMFCR_RAMTYPE      0
 416 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 417 #endif
 418
 419 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 420 #define CONFIG_ETHER_ON_FCC3
 421 #define CFG_CMXFCR_MASK3        (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
 422                                  CMXFCR_TF3CS_MSK)
 423 #define CFG_CMXFCR_VALUE3       (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
 424 #define CFG_CPMFCR_RAMTYPE      0
 425 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 426 #endif
 427
 428 /*
 429  * Environment
 430  */
 431 #define CFG_ENV_IS_IN_FLASH     1
 432
 433 #ifdef CONFIG_TQM_FLASH_N_TYPE
 434 #define CFG_ENV_SECT_SIZE       0x40000 /* 256K (one sector) for env    */
 435 #else /* !CONFIG_TQM_FLASH_N_TYPE */
 436 #define CFG_ENV_SECT_SIZE       0x20000 /* 128K (one sector) for env    */
 437 #endif /* CONFIG_TQM_FLASH_N_TYPE */
 438 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
 439 #define CFG_ENV_SIZE            0x2000
 440 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
 441 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 442
 443 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 444 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 445
 446 #define CONFIG_TIMESTAMP        /* Print image info with ts     */
 447
 448 /*
 449  * BOOTP options
 450  */
 451 #define CONFIG_BOOTP_BOOTFILESIZE
 452 #define CONFIG_BOOTP_BOOTPATH
 453 #define CONFIG_BOOTP_GATEWAY
 454 #define CONFIG_BOOTP_HOSTNAME
 455
 456 /*
 457  * Command line configuration.
 458  */
 459 #include <config_cmd_default.h>
 460
 461 #define CONFIG_CMD_PING
 462 #define CONFIG_CMD_I2C
 463 #define CONFIG_CMD_DHCP
 464 #define CONFIG_CMD_NFS
 465 #define CONFIG_CMD_SNTP
 466 #define CONFIG_CMD_DATE
 467 #define CONFIG_CMD_EEPROM
 468 #define CONFIG_CMD_DTT
 469 #define CONFIG_CMD_MII
 470
 471 #if defined(CONFIG_PCI)
 472 #define CONFIG_CMD_PCI
 473 #endif
 474
 475 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 476
 477 /*
 478  * Miscellaneous configurable options
 479  */
 480 #define CFG_LONGHELP                    /* undef to save memory         */
 481 #define CFG_LOAD_ADDR   0x2000000       /* default load address         */
 482 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 483
 484 #if defined(CONFIG_CMD_KGDB)
 485 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 486 #else
 487 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 488 #endif
 489
 490 #define CFG_PBSIZE      (CFG_CBSIZE + \
 491                          sizeof(CFG_PROMPT) + 16)   /* Print Buf Size   */
 492 #define CFG_MAXARGS     16              /* max number of command args   */
 493 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 494 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks  */
 495
 496 /*
 497  * For booting Linux, the board info and command line data
 498  * have to be in the first 8 MB of memory, since this is
 499  * the maximum mapped by the Linux kernel during initialization.
 500  */
 501 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux */
 502
 503 /*
 504  * Internal Definitions
 505  *
 506  * Boot Flags
 507  */
 508 #define BOOTFLAG_COLD   0x01            /* Power-On: Boot from FLASH    */
 509 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 510
 511 #if defined(CONFIG_CMD_KGDB)
 512 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port*/
 513 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use     */
 514 #endif
 515
 516 #define CONFIG_LOADADDR  200000         /* default addr for tftp & bootm*/
 517
 518 #define CONFIG_BOOTDELAY 5              /* -1 disables auto-boot        */
 519
 520 #define CONFIG_PREBOOT  "echo;" \
 521         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 522         "echo"
 523
 524 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 525
 526
 527 /*
 528  * Setup some board specific values for the default environment variables
 529  */
 530 #ifdef CONFIG_CPM2
 531 #define CFG_ENV_CONSDEV         "consdev=ttyCPM0\0"
 532 #else
 533 #define CFG_ENV_CONSDEV         "consdev=ttyS0\0"
 534 #endif
 535 #define CFG_ENV_FDT_FILE        "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
 536                                 MK_STR(CONFIG_HOSTNAME)".dtb\0"
 537 #define CFG_ENV_BOOTFILE        "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
 538 #define CFG_ENV_UBOOT           "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
 539                                 "uboot_addr="MK_STR(TEXT_BASE)"\0"
 540
 541 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 542         CFG_ENV_BOOTFILE                                                \
 543         CFG_ENV_FDT_FILE                                                \
 544         CFG_ENV_CONSDEV                                                 \
 545         "netdev=eth0\0"                                                 \
 546         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 547                 "nfsroot=$serverip:$rootpath\0"                         \
 548         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 549         "addip=setenv bootargs $bootargs "                              \
 550                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 551                 ":$hostname:$netdev:off panic=1\0"                      \
 552         "addcons=setenv bootargs $bootargs "                            \
 553                 "console=$consdev,$baudrate\0"                          \
 554         "flash_nfs=run nfsargs addip addcons;"                          \
 555                 "bootm $kernel_addr - $fdt_addr\0"                      \
 556         "flash_self=run ramargs addip addcons;"                         \
 557                 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0"          \
 558         "net_nfs=tftp $kernel_addr_r $bootfile;"                        \
 559                 "tftp $fdt_addr_r $fdt_file;"                           \
 560                 "run nfsargs addip addcons;"                            \
 561                 "bootm $kernel_addr_r - $fdt_addr_r\0"                  \
 562         "rootpath=/opt/eldk/ppc_85xx\0"                                 \
 563         "fdt_addr_r=900000\0"                                           \
 564         "kernel_addr_r=1000000\0"                                       \
 565         "fdt_addr=ffec0000\0"                                           \
 566         "kernel_addr=ffd00000\0"                                        \
 567         "ramdisk_addr=ff800000\0"                                       \
 568         CFG_ENV_UBOOT                                                   \
 569         "load=tftp 100000 $uboot\0"                                     \
 570         "update=protect off $uboot_addr +$filesize;"                    \
 571                 "erase $uboot_addr +$filesize;"                         \
 572                 "cp.b 100000 $uboot_addr $filesize;"                    \
 573                 "setenv filesize;saveenv\0"                             \
 574         "upd=run load update\0"                                         \
 575         ""
 576 #define CONFIG_BOOTCOMMAND      "run flash_self"
 577
 578 #endif /* __CONFIG_H */