include/configs/TQM85xx.h

   1 /*
   2  * (C) Copyright 2007
   3  * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
   4  *
   5  * (C) Copyright 2005
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * Wolfgang Denk <wd@denx.de>
   9  * Copyright 2004 Freescale Semiconductor.
  10  * (C) Copyright 2002,2003 Motorola,Inc.
  11  * Xianghua Xiao <X.Xiao@motorola.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 /*
  33  * TQM85xx (8560/40/55/41/48) board configuration file
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_BOOKE            1       /* BOOKE                        */
  41 #define CONFIG_E500             1       /* BOOKE e500 family            */
  42 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41             */
  43
  44 #if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
  45 #define CONFIG_TQM8548
  46 #endif
  47
  48 #define CONFIG_PCI
  49 #ifndef CONFIG_TQM8548_AG
  50 #define CONFIG_PCI1                     /* PCI/PCI-X controller         */
  51 #endif
  52 #ifdef CONFIG_TQM8548
  53 #define CONFIG_PCIE1                    /* PCI Express interface        */
  54 #endif
  55
  56 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code     */
  57 #define CONFIG_PCIX_CHECK               /* PCIX olny works at 66 MHz    */
  58 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata       */
  59
  60 #define CONFIG_TSEC_ENET                /* tsec ethernet support        */
  61
  62 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  63
  64  /*
  65  * Configuration for big NOR Flashes
  66  *
  67  * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
  68  * Please be aware, that this changes the whole memory map (new CCSRBAR
  69  * address, etc). You have to use an adapted Linux kernel or FDT blob
  70  * if this option is set.
  71  */
  72 #undef CONFIG_TQM_BIGFLASH
  73
  74 /*
  75  * NAND flash support (disabled by default)
  76  *
  77  * Warning: NAND support will likely increase the U-Boot image size
  78  * to more than 256 KB. Please adjust TEXT_BASE if necessary.
  79  */
  80 #ifdef CONFIG_TQM8548_BE
  81 #define CONFIG_NAND
  82 #endif
  83
  84 /*
  85  * MPC8540 and MPC8548 don't have CPM module
  86  */
  87 #if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
  88 #define CONFIG_CPM2             1       /* has CPM2                     */
  89 #endif
  90
  91 #define CONFIG_FSL_LAW          1       /* Use common FSL init code     */
  92
  93 #if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
  94 #define CONFIG_CAN_DRIVER               /* CAN Driver support           */
  95 #endif
  96
  97 /*
  98  * sysclk for MPC85xx
  99  *
 100  * Two valid values are:
 101  *    33333333
 102  *    66666666
 103  *
 104  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 105  * is likely the desired value here, so that is now the default.
 106  * The board, however, can run at 66MHz.  In any event, this value
 107  * must match the settings of some switches.  Details can be found
 108  * in the README.mpc85xxads.
 109  */
 110
 111 #ifndef CONFIG_SYS_CLK_FREQ
 112 #define CONFIG_SYS_CLK_FREQ     33333333
 113 #endif
 114
 115 /*
 116  * These can be toggled for performance analysis, otherwise use default.
 117  */
 118 #define CONFIG_L2_CACHE                 /* toggle L2 cache              */
 119 #define CONFIG_BTB                      /* toggle branch predition      */
 120
 121 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions      */
 122
 123 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time      */
 124 #define CONFIG_SYS_MEMTEST_START        0x00000000
 125 #define CONFIG_SYS_MEMTEST_END          0x10000000
 126
 127 /*
 128  * Base addresses -- Note these are effective addresses where the
 129  * actual resources get mapped (not physical addresses)
 130  */
 131 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xFF700000      /* CCSRBAR Default      */
 132 #ifdef CONFIG_TQM_BIGFLASH
 133 #define CONFIG_SYS_CCSRBAR              0xA0000000      /* relocated CCSRBAR    */
 134 #else /* !CONFIG_TQM_BIGFLASH */
 135 #define CONFIG_SYS_CCSRBAR              0xE0000000      /* relocated CCSRBAR    */
 136 #endif /* CONFIG_TQM_BIGFLASH */
 137 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
 138 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR    */
 139
 140 #define CONFIG_SYS_PCI1_ADDR            (CONFIG_SYS_CCSRBAR + 0x8000)
 141 #define CONFIG_SYS_PCI2_ADDR            (CONFIG_SYS_CCSRBAR + 0x9000)
 142 #define CONFIG_SYS_PCIE1_ADDR           (CONFIG_SYS_CCSRBAR + 0xa000)
 143
 144 /*
 145  * DDR Setup
 146  */
 147 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory */
 148 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 149 #ifdef CONFIG_TQM8548_AG
 150 #define CONFIG_VERY_BIG_RAM
 151 #endif
 152
 153 #define CONFIG_NUM_DDR_CONTROLLERS      1
 154 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 155 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 156
 157 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
 158 /* TQM8540 & 8560 need DLL-override */
 159 #define CONFIG_DDR_DLL                          /* DLL fix needed       */
 160 #define CONFIG_DDR_DEFAULT_CL   25              /* CAS latency 2,5      */
 161 #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
 162
 163 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
 164     defined(CONFIG_TQM8548)
 165 #define CONFIG_DDR_DEFAULT_CL   30              /* CAS latency 3        */
 166 #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
 167
 168 /*
 169  * Flash on the Local Bus
 170  */
 171 #ifdef CONFIG_TQM_BIGFLASH
 172 #define CONFIG_SYS_FLASH0               0xE0000000
 173 #define CONFIG_SYS_FLASH1               0xC0000000
 174 #else /* !CONFIG_TQM_BIGFLASH */
 175 #define CONFIG_SYS_FLASH0               0xFC000000
 176 #define CONFIG_SYS_FLASH1               0xF8000000
 177 #endif /* CONFIG_TQM_BIGFLASH */
 178 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 179
 180 #define CONFIG_SYS_LBC_FLASH_BASE       CONFIG_SYS_FLASH1       /* Localbus flash start */
 181 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_LBC_FLASH_BASE  /* start of FLASH    */
 182
 183 /* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
 184  *
 185  * Note: According to timing specifications external addr latch delay
 186  * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
 187  *
 188  * For other Local Bus Clocks see following table:
 189  *
 190  * Clock/MHz   CONFIG_SYS_ORx_PRELIM
 191  * 166         0x.....CA5
 192  * 133         0x.....C85
 193  * 100         0x.....C65
 194  *  83         0x.....FA2
 195  *  66         0x.....C82
 196  *  50         0x.....C60
 197  *  42         0x.....040
 198  *  33         0x.....030
 199  *  25         0x.....020
 200  *
 201  */
 202 #ifdef CONFIG_TQM_BIGFLASH
 203 #define CONFIG_SYS_BR0_PRELIM           0xE0001801      /* port size 32bit      */
 204 #define CONFIG_SYS_OR0_PRELIM           0xE0000040      /* 512MB Flash          */
 205 #define CONFIG_SYS_BR1_PRELIM           0xC0001801      /* port size 32bit      */
 206 #define CONFIG_SYS_OR1_PRELIM           0xE0000040      /* 512MB Flash          */
 207 #else /* !CONFIG_TQM_BIGFLASH */
 208 #define CONFIG_SYS_BR0_PRELIM           0xfc001801      /* port size 32bit      */
 209 #define CONFIG_SYS_OR0_PRELIM           0xfc000040      /* 64MB Flash           */
 210 #define CONFIG_SYS_BR1_PRELIM           0xf8001801      /* port size 32bit      */
 211 #define CONFIG_SYS_OR1_PRELIM           0xfc000040      /* 64MB Flash           */
 212 #endif /* CONFIG_TQM_BIGFLASH */
 213
 214 #define CONFIG_SYS_FLASH_CFI                    /* flash is CFI compat.         */
 215 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 216 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector   */
 217 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash*/
 218 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1 /* speed up output to Flash   */
 219
 220 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks              */
 221 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device           */
 222 #undef  CONFIG_SYS_FLASH_CHECKSUM
 223 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms)     */
 224 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms)     */
 225
 226 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor     */
 227
 228 /*
 229  * Note: when changing the Local Bus clock divider you have to
 230  * change the timing values in CONFIG_SYS_ORx_PRELIM.
 231  *
 232  * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
 233  * LCRR[16:17] EADC  : External address delay cycles. It should be set to 2
 234  *                     for Local Bus Clock > 83.3 MHz.
 235  */
 236 #define CONFIG_SYS_LBC_LCRR             0x00030008      /* LB clock ratio reg   */
 237 #define CONFIG_SYS_LBC_LBCR             0x00000000      /* LB config reg        */
 238 #define CONFIG_SYS_LBC_LSRT             0x20000000      /* LB sdram refresh timer */
 239 #define CONFIG_SYS_LBC_MRTPR            0x20000000      /* LB refresh timer presc.*/
 240
 241 #define CONFIG_SYS_INIT_RAM_LOCK        1
 242 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_CCSRBAR \
 243                                  + 0x04010000)  /* Initial RAM address  */
 244 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End used area in RAM */
 245
 246 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* num bytes initial data       */
 247 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 248 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 249
 250 #define CONFIG_SYS_MONITOR_LEN          (~TEXT_BASE + 1)/* Reserved for Monitor */
 251 #define CONFIG_SYS_MALLOC_LEN           (384 * 1024)    /* Reserved for malloc  */
 252
 253 /* Serial Port */
 254 #if defined(CONFIG_TQM8560)
 255
 256 #define CONFIG_CONS_ON_SCC      /* define if console on SCC             */
 257 #undef  CONFIG_CONS_NONE        /* define if console on something else  */
 258 #define CONFIG_CONS_INDEX       1 /* which serial channel for console   */
 259
 260 #else /* !CONFIG_TQM8560 */
 261
 262 #define CONFIG_CONS_INDEX     1
 263 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 264 #define CONFIG_SYS_NS16550
 265 #define CONFIG_SYS_NS16550_SERIAL
 266 #define CONFIG_SYS_NS16550_REG_SIZE     1
 267 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 268
 269 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 270 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 271
 272 /* PS/2 Keyboard */
 273 #define CONFIG_PS2KBD                   /* AT-PS/2 Keyboard             */
 274 #define CONFIG_PS2MULT                  /* .. on PS/2 Multiplexer       */
 275 #define CONFIG_PS2SERIAL        2       /* .. on DUART2                 */
 276 #define CONFIG_PS2MULT_DELAY    (CONFIG_SYS_HZ/2)       /* Initial delay        */
 277 #define CONFIG_BOARD_EARLY_INIT_R       1
 278
 279 #endif /* CONFIG_TQM8560 */
 280
 281 #define CONFIG_BAUDRATE         115200
 282
 283 #define CONFIG_SYS_BAUDRATE_TABLE       \
 284         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 285
 286 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 287 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 288 #ifdef  CONFIG_SYS_HUSH_PARSER
 289 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 290 #endif
 291
 292 /* pass open firmware flat tree */
 293 #define CONFIG_OF_LIBFDT                1
 294 #define CONFIG_OF_BOARD_SETUP           1
 295 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 296
 297 /* CAN */
 298 #define CONFIG_SYS_CAN_BASE             (CONFIG_SYS_CCSRBAR \
 299                                  + 0x03000000)  /* CAN base address     */
 300 #ifdef CONFIG_CAN_DRIVER
 301 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 KiB address mask  */
 302 #define CONFIG_SYS_OR2_CAN              (CONFIG_SYS_CAN_OR_AM | OR_UPM_BI)
 303 #define CONFIG_SYS_BR2_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA) | \
 304                                  BR_PS_8 | BR_MS_UPMC | BR_V)
 305 #endif /* CONFIG_CAN_DRIVER */
 306
 307 /*
 308  * I2C
 309  */
 310 #define CONFIG_FSL_I2C                  /* Use FSL common I2C driver    */
 311 #define CONFIG_HARD_I2C                 /* I2C with hardware support    */
 312 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 313 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 314 #define CONFIG_SYS_I2C_SLAVE            0x7F
 315 #define CONFIG_SYS_I2C_NOPROBES {0x48}  /* Don't probe these addrs      */
 316 #define CONFIG_SYS_I2C_OFFSET           0x3000
 317
 318 /* I2C RTC */
 319 #define CONFIG_RTC_DS1337               /* Use ds1337 rtc via i2c       */
 320 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68              */
 321
 322 /* I2C EEPROM */
 323 /*
 324  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
 325  */
 326 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x             */
 327 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 328 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* =32 Bytes per write  */
 329 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 330 #define CONFIG_SYS_I2C_MULTI_EEPROMS            1       /* more than one eeprom */
 331
 332 /* I2C SYSMON (LM75) */
 333 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 334 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 335 #define CONFIG_SYS_DTT_MAX_TEMP 70
 336 #define CONFIG_SYS_DTT_LOW_TEMP -30
 337 #define CONFIG_SYS_DTT_HYSTERESIS       3
 338
 339 #ifndef CONFIG_PCIE1
 340 /* RapidIO MMU */
 341 #ifdef CONFIG_TQM_BIGFLASH
 342 #define CONFIG_SYS_RIO_MEM_BASE 0xb0000000      /* base address         */
 343 #define CONFIG_SYS_RIO_MEM_SIZE 0x10000000      /* 256M                 */
 344 #else /* !CONFIG_TQM_BIGFLASH */
 345 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000      /* base address         */
 346 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 512M                 */
 347 #endif /* CONFIG_TQM_BIGFLASH */
 348 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
 349 #endif /* CONFIG_PCIE1 */
 350
 351 /* NAND FLASH */
 352 #ifdef CONFIG_NAND
 353
 354 #undef CONFIG_NAND_LEGACY
 355
 356 #define CONFIG_NAND_FSL_UPM     1
 357
 358 #define CONFIG_MTD_NAND_ECC_JFFS2       1       /* use JFFS2 ECC        */
 359
 360 /* address distance between chip selects */
 361 #define CONFIG_SYS_NAND_SELECT_DEVICE   1
 362 #define CONFIG_SYS_NAND_CS_DIST 0x200
 363
 364 #define CONFIG_SYS_NAND_SIZE            0x8000
 365 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_CCSRBAR + 0x03010000)
 366
 367 #define CONFIG_SYS_MAX_NAND_DEVICE      1       /* Max number of NAND devices   */
 368 #define CONFIG_SYS_NAND_MAX_CHIPS       2       /* Number of chips per device   */
 369
 370 /* CS3 for NAND Flash */
 371 #define CONFIG_SYS_BR3_PRELIM           ((CONFIG_SYS_NAND_BASE & BR_BA) | \
 372                                          BR_PS_8 | BR_MS_UPMB | BR_V)
 373 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
 374
 375 #define NAND_BIG_DELAY_US               25      /* max tR for Samsung devices   */
 376
 377 #define CONFIG_SYS_64BIT_VSPRINTF               /* needed for nand_util.c */
 378
 379 #endif /* CONFIG_NAND */
 380
 381 /*
 382  * General PCI
 383  * Addresses are mapped 1-1.
 384  */
 385 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 386 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 387 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M                 */
 388 #define CONFIG_SYS_PCI1_IO_BASE (CONFIG_SYS_CCSRBAR + 0x02000000)
 389 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
 390 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000       /*  16M                 */
 391
 392 #ifdef CONFIG_PCIE1
 393 /*
 394  * General PCI express
 395  * Addresses are mapped 1-1.
 396  */
 397 #ifdef CONFIG_TQM_BIGFLASH
 398 #define CONFIG_SYS_PCIE1_MEM_BASE       0xb0000000
 399 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 512M                 */
 400 #define CONFIG_SYS_PCIE1_IO_BASE        0xaf000000
 401 #else /* !CONFIG_TQM_BIGFLASH */
 402 #define CONFIG_SYS_PCIE1_MEM_BASE       0xc0000000
 403 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M                 */
 404 #define CONFIG_SYS_PCIE1_IO_BASE        0xef000000
 405 #endif /* CONFIG_TQM_BIGFLASH */
 406 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BASE
 407 #define CONFIG_SYS_PCIE1_IO_PHYS        CONFIG_SYS_PCIE1_IO_BASE
 408 #define CONFIG_SYS_PCIE1_IO_SIZE        0x1000000       /* 16M                  */
 409 #endif /* CONFIG_PCIE1 */
 410
 411 #if defined(CONFIG_PCI)
 412
 413 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 414
 415 #define CONFIG_EEPRO100
 416 #undef CONFIG_TULIP
 417
 418 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup  */
 419 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola                     */
 420
 421 #endif /* CONFIG_PCI */
 422
 423 #define CONFIG_NET_MULTI        1
 424
 425 #define CONFIG_MII              1       /* MII PHY management           */
 426 #define CONFIG_TSEC1    1
 427 #define CONFIG_TSEC1_NAME       "TSEC0"
 428 #define CONFIG_TSEC2    1
 429 #define CONFIG_TSEC2_NAME       "TSEC1"
 430 #define TSEC1_PHY_ADDR          2
 431 #define TSEC2_PHY_ADDR          1
 432 #define TSEC1_PHYIDX            0
 433 #define TSEC2_PHYIDX            0
 434 #define TSEC1_FLAGS             TSEC_GIGABIT
 435 #define TSEC2_FLAGS             TSEC_GIGABIT
 436 #define FEC_PHY_ADDR            3
 437 #define FEC_PHYIDX              0
 438 #define FEC_FLAGS               0
 439 #define CONFIG_HAS_ETH0
 440 #define CONFIG_HAS_ETH1
 441 #define CONFIG_HAS_ETH2
 442
 443 #ifdef CONFIG_TQM8548
 444 /*
 445  * TQM8548 has 4 ethernet ports. 4 ETSEC's.
 446  *
 447  * On the STK85xx Starterkit the ETSEC3/4 ports are on an
 448  * additional adapter (AIO) between module and Starterkit.
 449  */
 450 #define CONFIG_TSEC3    1
 451 #define CONFIG_TSEC3_NAME       "TSEC2"
 452 #define CONFIG_TSEC4    1
 453 #define CONFIG_TSEC4_NAME       "TSEC3"
 454 #define TSEC3_PHY_ADDR          4
 455 #define TSEC4_PHY_ADDR          5
 456 #define TSEC3_PHYIDX            0
 457 #define TSEC4_PHYIDX            0
 458 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 459 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 460 #define CONFIG_HAS_ETH3
 461 #define CONFIG_HAS_ETH4
 462 #endif  /* CONFIG_TQM8548 */
 463
 464 /* Options are TSEC[0-1], FEC */
 465 #define CONFIG_ETHPRIME         "TSEC0"
 466
 467 #if defined(CONFIG_TQM8540)
 468 /*
 469  * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
 470  * The FEC port is connected on the same signals as the FCC3 port
 471  * of the TQM8560 to the baseboard (STK85xx Starterkit).
 472  *
 473  * On the STK85xx Starterkit the X47/X50 jumper has to be set to
 474  * a - d (X50.2 - 3) to enable the FEC port.
 475  */
 476 #define CONFIG_MPC85XX_FEC      1
 477 #define CONFIG_MPC85XX_FEC_NAME "FEC"
 478 #endif
 479
 480 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
 481 /*
 482  * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
 483  * can be used at once, since only one FCC port is available on the STK85xx
 484  * Starterkit.
 485  *
 486  * To use this port you have to configure U-Boot to use the FCC port 1...2
 487  * and set the X47/X50 jumper to:
 488  * FCC1: a - b (X47.2 - X50.2)
 489  * FCC2: a - c (X50.2 - 1)
 490  */
 491 #define CONFIG_ETHER_ON_FCC
 492 #define CONFIG_ETHER_INDEX    1 /* FCC channel for ethernet     */
 493 #endif
 494
 495 #if defined(CONFIG_TQM8560)
 496 /*
 497  * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
 498  * can be used at once, since only one FCC port is available on the STK85xx
 499  * Starterkit.
 500  *
 501  * To use this port you have to configure U-Boot to use the FCC port 1...3
 502  * and set the X47/X50 jumper to:
 503  * FCC1: a - b (X47.2 - X50.2)
 504  * FCC2: a - c (X50.2 - 1)
 505  * FCC3: a - d (X50.2 - 3)
 506  */
 507 #define CONFIG_ETHER_ON_FCC
 508 #define CONFIG_ETHER_INDEX    3 /* FCC channel for ethernet     */
 509 #endif
 510
 511 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
 512 #define CONFIG_ETHER_ON_FCC1
 513 #define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
 514                                  CMXFCR_TF1CS_MSK)
 515 #define CONFIG_SYS_CMXFCR_VALUE1        (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
 516 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 517 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 518 #endif
 519
 520 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 521 #define CONFIG_ETHER_ON_FCC2
 522 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
 523                                  CMXFCR_TF2CS_MSK)
 524 #define CONFIG_SYS_CMXFCR_VALUE2        (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
 525 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 526 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 527 #endif
 528
 529 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 530 #define CONFIG_ETHER_ON_FCC3
 531 #define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
 532                                  CMXFCR_TF3CS_MSK)
 533 #define CONFIG_SYS_CMXFCR_VALUE3        (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
 534 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 535 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 536 #endif
 537
 538 /*
 539  * Environment
 540  */
 541 #define CONFIG_ENV_IS_IN_FLASH  1
 542
 543 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K (one sector) for env    */
 544 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 545 #define CONFIG_ENV_SIZE         0x2000
 546 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 547 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 548
 549 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 550 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 551
 552 #define CONFIG_TIMESTAMP        /* Print image info with ts     */
 553
 554 /*
 555  * BOOTP options
 556  */
 557 #define CONFIG_BOOTP_BOOTFILESIZE
 558 #define CONFIG_BOOTP_BOOTPATH
 559 #define CONFIG_BOOTP_GATEWAY
 560 #define CONFIG_BOOTP_HOSTNAME
 561
 562 #ifdef CONFIG_NAND
 563 /*
 564  * Use NAND-FLash as JFFS2 device
 565  */
 566 #define CONFIG_CMD_NAND
 567 #define CONFIG_CMD_JFFS2
 568
 569 #define CONFIG_JFFS2_NAND       1
 570
 571 #ifdef CONFIG_CMD_MTDPARTS
 572 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 573 #define CONFIG_FLASH_CFI_MTD
 574 #define MTDIDS_DEFAULT          "nand0=TQM85xx-nand"
 575 #define MTDPARTS_DEFAULT        "mtdparts=TQM85xx-nand:-"
 576 #else
 577 #define CONFIG_JFFS2_DEV        "nand0" /* NAND device jffs2 lives on   */
 578 #define CONFIG_JFFS2_PART_OFFSET 0      /* start of jffs2 partition     */
 579 #define CONFIG_JFFS2_PART_SIZE  0x200000 /* size of jffs2 partition     */
 580 #endif /* CONFIG_CMD_MTDPARTS */
 581
 582 #endif /* CONFIG_NAND */
 583
 584 /*
 585  * Command line configuration.
 586  */
 587 #include <config_cmd_default.h>
 588
 589 #define CONFIG_CMD_PING
 590 #define CONFIG_CMD_I2C
 591 #define CONFIG_CMD_DHCP
 592 #define CONFIG_CMD_NFS
 593 #define CONFIG_CMD_SNTP
 594 #ifndef CONFIG_TQM8548_AG
 595 #define CONFIG_CMD_DATE
 596 #endif
 597 #define CONFIG_CMD_EEPROM
 598 #define CONFIG_CMD_DTT
 599 #define CONFIG_CMD_MII
 600
 601 #if defined(CONFIG_PCI)
 602 #define CONFIG_CMD_PCI
 603 #endif
 604
 605 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 606
 607 /*
 608  * Miscellaneous configurable options
 609  */
 610 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 611 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address         */
 612 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 613
 614 #if defined(CONFIG_CMD_KGDB)
 615 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 616 #else
 617 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 618 #endif
 619
 620 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 621                          sizeof(CONFIG_SYS_PROMPT) + 16)   /* Print Buf Size    */
 622 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 623 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 624 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks  */
 625
 626 /*
 627  * For booting Linux, the board info and command line data
 628  * have to be in the first 8 MB of memory, since this is
 629  * the maximum mapped by the Linux kernel during initialization.
 630  */
 631 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux */
 632
 633 /*
 634  * Internal Definitions
 635  *
 636  * Boot Flags
 637  */
 638 #define BOOTFLAG_COLD   0x01            /* Power-On: Boot from FLASH    */
 639 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 640
 641 #if defined(CONFIG_CMD_KGDB)
 642 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port*/
 643 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use     */
 644 #endif
 645
 646 #define CONFIG_LOADADDR  200000         /* default addr for tftp & bootm*/
 647
 648 #define CONFIG_BOOTDELAY 5              /* -1 disables auto-boot        */
 649
 650 #define CONFIG_PREBOOT  "echo;" \
 651         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 652         "echo"
 653
 654 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 655
 656
 657 /*
 658  * Setup some board specific values for the default environment variables
 659  */
 660 #ifdef CONFIG_CPM2
 661 #define CONFIG_ENV_CONSDEV              "consdev=ttyCPM0\0"
 662 #else
 663 #define CONFIG_ENV_CONSDEV              "consdev=ttyS0\0"
 664 #endif
 665 #define CONFIG_ENV_FDT_FILE     "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
 666                                 MK_STR(CONFIG_HOSTNAME)".dtb\0"
 667 #define CONFIG_ENV_BOOTFILE     "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
 668 #define CONFIG_ENV_UBOOT                "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
 669                                 "uboot_addr="MK_STR(TEXT_BASE)"\0"
 670
 671 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 672         CONFIG_ENV_BOOTFILE                                             \
 673         CONFIG_ENV_FDT_FILE                                             \
 674         CONFIG_ENV_CONSDEV                                              \
 675         "netdev=eth0\0"                                                 \
 676         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 677                 "nfsroot=$serverip:$rootpath\0"                         \
 678         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 679         "addip=setenv bootargs $bootargs "                              \
 680                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 681                 ":$hostname:$netdev:off panic=1\0"                      \
 682         "addcons=setenv bootargs $bootargs "                            \
 683                 "console=$consdev,$baudrate\0"                          \
 684         "flash_nfs=run nfsargs addip addcons;"                          \
 685                 "bootm $kernel_addr - $fdt_addr\0"                      \
 686         "flash_self=run ramargs addip addcons;"                         \
 687                 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0"          \
 688         "net_nfs=tftp $kernel_addr_r $bootfile;"                        \
 689                 "tftp $fdt_addr_r $fdt_file;"                           \
 690                 "run nfsargs addip addcons;"                            \
 691                 "bootm $kernel_addr_r - $fdt_addr_r\0"                  \
 692         "rootpath=/opt/eldk/ppc_85xx\0"                                 \
 693         "fdt_addr_r=900000\0"                                           \
 694         "kernel_addr_r=1000000\0"                                       \
 695         "fdt_addr=ffec0000\0"                                           \
 696         "kernel_addr=ffd00000\0"                                        \
 697         "ramdisk_addr=ff800000\0"                                       \
 698         CONFIG_ENV_UBOOT                                                \
 699         "load=tftp 100000 $uboot\0"                                     \
 700         "update=protect off $uboot_addr +$filesize;"                    \
 701                 "erase $uboot_addr +$filesize;"                         \
 702                 "cp.b 100000 $uboot_addr $filesize"                     \
 703         "upd=run load update\0"                                         \
 704         ""
 705 #define CONFIG_BOOTCOMMAND      "run flash_self"
 706
 707 #endif /* __CONFIG_H */