include/configs/TQM85xx.h

   1 /*
   2  * (C) Copyright 2007
   3  * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
   4  *
   5  * (C) Copyright 2005
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * Wolfgang Denk <wd@denx.de>
   9  * Copyright 2004 Freescale Semiconductor.
  10  * (C) Copyright 2002,2003 Motorola,Inc.
  11  * Xianghua Xiao <X.Xiao@motorola.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 /*
  33  * TQM85xx (8560/40/55/41/48) board configuration file
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_BOOKE            1       /* BOOKE                        */
  41 #define CONFIG_E500             1       /* BOOKE e500 family            */
  42 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41             */
  43
  44 #define CONFIG_PCI
  45 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code     */
  46 #define CONFIG_PCIX_CHECK               /* PCIX olny works at 66 MHz    */
  47 #ifdef CONFIG_TQM8548
  48 #define CONFIG_PCI1
  49 #define CONFIG_PCIE1
  50 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata       */
  51 #endif
  52
  53 #define CONFIG_TSEC_ENET                /* tsec ethernet support        */
  54
  55 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  56
  57  /*
  58  * Configuration for big NOR Flashes
  59  *
  60  * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
  61  * Please be aware, that this changes the whole memory map (new CCSRBAR
  62  * address, etc). You have to use an adapted Linux kernel or FDT blob
  63  * if this option is set.
  64  */
  65 #undef CONFIG_TQM_BIGFLASH
  66
  67 /*
  68  * NAND flash support (disabled by default)
  69  *
  70  * Warning: NAND support will likely increase the U-Boot image size
  71  * to more than 256 KB. Please adjust TEXT_BASE if necessary.
  72  */
  73 #undef CONFIG_NAND
  74
  75 /*
  76  * MPC8540 and MPC8548 don't have CPM module
  77  */
  78 #if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
  79 #define CONFIG_CPM2             1       /* has CPM2                     */
  80 #endif
  81
  82 #define CONFIG_FSL_LAW          1       /* Use common FSL init code     */
  83
  84 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support           */
  85
  86 /*
  87  * sysclk for MPC85xx
  88  *
  89  * Two valid values are:
  90  *    33333333
  91  *    66666666
  92  *
  93  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  94  * is likely the desired value here, so that is now the default.
  95  * The board, however, can run at 66MHz.  In any event, this value
  96  * must match the settings of some switches.  Details can be found
  97  * in the README.mpc85xxads.
  98  */
  99
 100 #ifndef CONFIG_SYS_CLK_FREQ
 101 #define CONFIG_SYS_CLK_FREQ     33333333
 102 #endif
 103
 104 /*
 105  * These can be toggled for performance analysis, otherwise use default.
 106  */
 107 #define CONFIG_L2_CACHE                 /* toggle L2 cache              */
 108 #define CONFIG_BTB                      /* toggle branch predition      */
 109 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming        */
 110
 111 #define CFG_INIT_DBCR DBCR_IDM          /* Enable Debug Exceptions      */
 112
 113 #undef  CFG_DRAM_TEST                   /* memory test, takes time      */
 114 #define CFG_MEMTEST_START       0x00000000
 115 #define CFG_MEMTEST_END         0x10000000
 116
 117 /*
 118  * Base addresses -- Note these are effective addresses where the
 119  * actual resources get mapped (not physical addresses)
 120  */
 121 #define CFG_CCSRBAR_DEFAULT     0xFF700000      /* CCSRBAR Default      */
 122 #ifdef CONFIG_TQM_BIGFLASH
 123 #define CFG_CCSRBAR             0xA0000000      /* relocated CCSRBAR    */
 124 #else /* !CONFIG_TQM_BIGFLASH */
 125 #define CFG_CCSRBAR             0xE0000000      /* relocated CCSRBAR    */
 126 #endif /* CONFIG_TQM_BIGFLASH */
 127 #define CFG_CCSRBAR_PHYS        CFG_CCSRBAR     /* physical addr of CCSRBAR */
 128 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR   */
 129
 130 #define CFG_PCI1_ADDR           (CFG_CCSRBAR + 0x8000)
 131 #define CFG_PCI2_ADDR           (CFG_CCSRBAR + 0x9000)
 132 #define CFG_PCIE1_ADDR          (CFG_CCSRBAR + 0xa000)
 133
 134 /*
 135  * DDR Setup
 136  */
 137 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory */
 138 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 139
 140 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
 141 /* TQM8540 & 8560 need DLL-override */
 142 #define CONFIG_DDR_DLL                          /* DLL fix needed       */
 143 #define CONFIG_DDR_DEFAULT_CL   25              /* CAS latency 2,5      */
 144 #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
 145
 146 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
 147     defined(CONFIG_TQM8548)
 148 #define CONFIG_DDR_DEFAULT_CL   30              /* CAS latency 3        */
 149 #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
 150
 151 /*
 152  * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM
 153  * series while new boards have 'N' type Flashes from the S29GLxxxN
 154  * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB.
 155  */
 156 #ifdef CONFIG_TQM8548
 157 #define CONFIG_TQM_FLASH_N_TYPE
 158 #endif /* CONFIG_TQM8548 */
 159
 160 /*
 161  * Flash on the Local Bus
 162  */
 163 #ifdef CONFIG_TQM_BIGFLASH
 164 #define CFG_FLASH0              0xE0000000
 165 #define CFG_FLASH1              0xC0000000
 166 #else /* !CONFIG_TQM_BIGFLASH */
 167 #define CFG_FLASH0              0xFC000000
 168 #define CFG_FLASH1              0xF8000000
 169 #endif /* CONFIG_TQM_BIGFLASH */
 170 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH1, CFG_FLASH0 }
 171
 172 #define CFG_LBC_FLASH_BASE      CFG_FLASH1      /* Localbus flash start */
 173 #define CFG_FLASH_BASE          CFG_LBC_FLASH_BASE  /* start of FLASH   */
 174
 175 /* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
 176  *
 177  * Note: According to timing specifications external addr latch delay
 178  * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
 179  *
 180  * For other Local Bus Clocks see following table:
 181  *
 182  * Clock/MHz   CFG_ORx_PRELIM
 183  * 166         0x.....CA5
 184  * 133         0x.....C85
 185  * 100         0x.....C65
 186  *  83         0x.....FA2
 187  *  66         0x.....C82
 188  *  50         0x.....C60
 189  *  42         0x.....040
 190  *  33         0x.....030
 191  *  25         0x.....020
 192  *
 193  */
 194 #ifdef CONFIG_TQM_BIGFLASH
 195 #define CFG_BR0_PRELIM          0xE0001801      /* port size 32bit      */
 196 #define CFG_OR0_PRELIM          0xE0000040      /* 512MB Flash          */
 197 #define CFG_BR1_PRELIM          0xC0001801      /* port size 32bit      */
 198 #define CFG_OR1_PRELIM          0xE0000040      /* 512MB Flash          */
 199 #else /* !CONFIG_TQM_BIGFLASH */
 200 #define CFG_BR0_PRELIM          0xfc001801      /* port size 32bit      */
 201 #define CFG_OR0_PRELIM          0xfc000040      /* 64MB Flash           */
 202 #define CFG_BR1_PRELIM          0xf8001801      /* port size 32bit      */
 203 #define CFG_OR1_PRELIM          0xfc000040      /* 64MB Flash           */
 204 #endif /* CONFIG_TQM_BIGFLASH */
 205
 206 #define CFG_FLASH_CFI                   /* flash is CFI compat.         */
 207 #define CFG_FLASH_CFI_DRIVER            /* Use common CFI driver        */
 208 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector   */
 209 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash*/
 210 #define CFG_FLASH_USE_BUFFER_WRITE      1 /* speed up output to Flash   */
 211
 212 #define CFG_MAX_FLASH_BANKS     2       /* number of banks              */
 213 #define CFG_MAX_FLASH_SECT      512     /* sectors per device           */
 214 #undef  CFG_FLASH_CHECKSUM
 215 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms)     */
 216 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms)     */
 217
 218 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor     */
 219
 220 /*
 221  * Note: when changing the Local Bus clock divider you have to
 222  * change the timing values in CFG_ORx_PRELIM.
 223  *
 224  * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
 225  * LCRR[16:17] EADC  : External address delay cycles. It should be set to 2
 226  *                     for Local Bus Clock > 83.3 MHz.
 227  */
 228 #define CFG_LBC_LCRR            0x00030008      /* LB clock ratio reg   */
 229 #define CFG_LBC_LBCR            0x00000000      /* LB config reg        */
 230 #define CFG_LBC_LSRT            0x20000000      /* LB sdram refresh timer */
 231 #define CFG_LBC_MRTPR           0x20000000      /* LB refresh timer presc.*/
 232
 233 #define CONFIG_L1_INIT_RAM
 234 #define CFG_INIT_RAM_LOCK       1
 235 #define CFG_INIT_RAM_ADDR       (CFG_CCSRBAR \
 236                                  + 0x04010000)  /* Initial RAM address  */
 237 #define CFG_INIT_RAM_END        0x4000          /* End used area in RAM */
 238
 239 #define CFG_GBL_DATA_SIZE       128     /* num bytes initial data       */
 240 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 241 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 242
 243 #define CFG_MONITOR_LEN         (~TEXT_BASE + 1)/* Reserved for Monitor */
 244 #define CFG_MALLOC_LEN          (384 * 1024)    /* Reserved for malloc  */
 245
 246 /* Serial Port */
 247 #if defined(CONFIG_TQM8560)
 248
 249 #define CONFIG_CONS_ON_SCC      /* define if console on SCC             */
 250 #undef  CONFIG_CONS_NONE        /* define if console on something else  */
 251 #define CONFIG_CONS_INDEX       1 /* which serial channel for console   */
 252
 253 #else /* !CONFIG_TQM8560 */
 254
 255 #define CONFIG_CONS_INDEX     1
 256 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 257 #define CFG_NS16550
 258 #define CFG_NS16550_SERIAL
 259 #define CFG_NS16550_REG_SIZE    1
 260 #define CFG_NS16550_CLK         get_bus_freq(0)
 261
 262 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 263 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 264
 265 /* PS/2 Keyboard */
 266 #define CONFIG_PS2KBD                   /* AT-PS/2 Keyboard             */
 267 #define CONFIG_PS2MULT                  /* .. on PS/2 Multiplexer       */
 268 #define CONFIG_PS2SERIAL        2       /* .. on DUART2                 */
 269 #define CONFIG_PS2MULT_DELAY    (CFG_HZ/2)      /* Initial delay        */
 270 #define CONFIG_BOARD_EARLY_INIT_R       1
 271
 272 #endif /* CONFIG_TQM8560 */
 273
 274 #define CONFIG_BAUDRATE         115200
 275
 276 #define CFG_BAUDRATE_TABLE      \
 277         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 278
 279 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 280 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 281 #ifdef  CFG_HUSH_PARSER
 282 #define CFG_PROMPT_HUSH_PS2     "> "
 283 #endif
 284
 285 /* pass open firmware flat tree */
 286 #define CONFIG_OF_LIBFDT                1
 287 #define CONFIG_OF_BOARD_SETUP           1
 288 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 289
 290 /* CAN */
 291 #define CFG_CAN_BASE            (CFG_CCSRBAR \
 292                                  + 0x03000000)  /* CAN base address     */
 293 #ifdef CONFIG_CAN_DRIVER
 294 #define CFG_CAN_OR_AM           0xFFFF8000      /* 32 KiB address mask  */
 295 #define CFG_OR2_CAN             (CFG_CAN_OR_AM | OR_UPM_BI)
 296 #define CFG_BR2_CAN             ((CFG_CAN_BASE & BR_BA) | \
 297                                  BR_PS_8 | BR_MS_UPMC | BR_V)
 298 #endif /* CONFIG_CAN_DRIVER */
 299
 300 /*
 301  * I2C
 302  */
 303 #define CONFIG_FSL_I2C                  /* Use FSL common I2C driver    */
 304 #define CONFIG_HARD_I2C                 /* I2C with hardware support    */
 305 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 306 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 307 #define CFG_I2C_SLAVE           0x7F
 308 #define CFG_I2C_NOPROBES        {0x48}  /* Don't probe these addrs      */
 309 #define CFG_I2C_OFFSET          0x3000
 310
 311 /* I2C RTC */
 312 #define CONFIG_RTC_DS1337               /* Use ds1337 rtc via i2c       */
 313 #define CFG_I2C_RTC_ADDR        0x68    /* at address 0x68              */
 314
 315 /* I2C EEPROM */
 316 /*
 317  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
 318  */
 319 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x             */
 320 #define CFG_I2C_EEPROM_ADDR_LEN         2
 321 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write  */
 322 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 323 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 324 #define CFG_I2C_MULTI_EEPROMS           1       /* more than one eeprom */
 325
 326 /* I2C SYSMON (LM75) */
 327 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 328 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 329 #define CFG_DTT_MAX_TEMP        70
 330 #define CFG_DTT_LOW_TEMP        -30
 331 #define CFG_DTT_HYSTERESIS      3
 332
 333 #ifndef CONFIG_PCIE1
 334 /* RapidIO MMU */
 335 #ifdef CONFIG_TQM_BIGFLASH
 336 #define CFG_RIO_MEM_BASE        0xb0000000      /* base address         */
 337 #define CFG_RIO_MEM_SIZE        0x10000000      /* 256M                 */
 338 #else /* !CONFIG_TQM_BIGFLASH */
 339 #define CFG_RIO_MEM_BASE        0xc0000000      /* base address         */
 340 #define CFG_RIO_MEM_SIZE        0x20000000      /* 512M                 */
 341 #endif /* CONFIG_TQM_BIGFLASH */
 342 #define CFG_RIO_MEM_PHYS        CFG_RIO_MEM_BASE
 343 #endif /* CONFIG_PCIE1 */
 344
 345 /* NAND FLASH */
 346 #ifdef CONFIG_NAND
 347
 348 #undef CFG_NAND_LEGACY
 349
 350 #define CONFIG_NAND_FSL_UPM     1
 351
 352 #define CONFIG_MTD_NAND_ECC_JFFS2       1       /* use JFFS2 ECC        */
 353
 354 /* address distance between chip selects */
 355 #define CFG_NAND_SELECT_DEVICE  1
 356 #define CFG_NAND_CS_DIST        0x200
 357
 358 #define CFG_NAND_SIZE           0x8000
 359 #define CFG_NAND0_BASE          (CFG_CCSRBAR + 0x03010000)
 360 #define CFG_NAND1_BASE          (CFG_NAND0_BASE + CFG_NAND_CS_DIST)
 361 #define CFG_NAND2_BASE          (CFG_NAND1_BASE + CFG_NAND_CS_DIST)
 362 #define CFG_NAND3_BASE          (CFG_NAND2_BASE + CFG_NAND_CS_DIST)
 363
 364 #define CFG_MAX_NAND_DEVICE     2       /* Max number of NAND devices   */
 365 #define NAND_MAX_CHIPS          1
 366
 367 #if (CFG_MAX_NAND_DEVICE == 1)
 368 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
 369 #elif (CFG_MAX_NAND_DEVICE == 2)
 370 #define CFG_NAND_QUIET_TEST     1
 371 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
 372                              CFG_NAND1_BASE, \
 373 }
 374 #elif (CFG_MAX_NAND_DEVICE == 4)
 375 #define CFG_NAND_QUIET_TEST     1
 376 #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \
 377                              CFG_NAND1_BASE, \
 378                              CFG_NAND2_BASE, \
 379                              CFG_NAND3_BASE, \
 380 }
 381 #endif
 382
 383 /* CS3 for NAND Flash */
 384 #define CFG_BR3_PRELIM          ((CFG_NAND0_BASE & BR_BA) | BR_PS_8 | \
 385                                  BR_MS_UPMB | BR_V)
 386 #define CFG_OR3_PRELIM          (P2SZ_TO_AM(CFG_NAND_SIZE) | OR_UPM_BI)
 387
 388 #define NAND_BIG_DELAY_US       25      /* max tR for Samsung devices   */
 389
 390 #endif /* CONFIG_NAND */
 391
 392 /*
 393  * General PCI
 394  * Addresses are mapped 1-1.
 395  */
 396 #define CFG_PCI1_MEM_BASE       0x80000000
 397 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 398 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M                 */
 399 #define CFG_PCI1_IO_BASE        (CFG_CCSRBAR + 0x02000000)
 400 #define CFG_PCI1_IO_PHYS        CFG_PCI1_IO_BASE
 401 #define CFG_PCI1_IO_SIZE        0x1000000       /*  16M                 */
 402
 403 /* PCI view of System Memory */
 404 #define CFG_PCI_MEMORY_BUS      0x00000000
 405 #define CFG_PCI_MEMORY_PHYS     0x00000000
 406 #define CFG_PCI_MEMORY_SIZE     0x80000000
 407
 408 #ifdef CONFIG_PCIE1
 409 /*
 410  * General PCI express
 411  * Addresses are mapped 1-1.
 412  */
 413 #ifdef CONFIG_TQM_BIGFLASH
 414 #define CFG_PCIE1_MEM_BASE      0xb0000000
 415 #define CFG_PCIE1_MEM_SIZE      0x10000000      /* 512M                 */
 416 #define CFG_PCIE1_IO_BASE       0xaf000000
 417 #else /* !CONFIG_TQM_BIGFLASH */
 418 #define CFG_PCIE1_MEM_BASE      0xc0000000
 419 #define CFG_PCIE1_MEM_SIZE      0x20000000      /* 512M                 */
 420 #define CFG_PCIE1_IO_BASE       0xef000000
 421 #endif /* CONFIG_TQM_BIGFLASH */
 422 #define CFG_PCIE1_MEM_PHYS      CFG_PCIE1_MEM_BASE
 423 #define CFG_PCIE1_IO_PHYS       CFG_PCIE1_IO_BASE
 424 #define CFG_PCIE1_IO_SIZE       0x1000000       /* 16M                  */
 425 #endif /* CONFIG_PCIE1 */
 426
 427 #if defined(CONFIG_PCI)
 428
 429 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 430
 431 #define CONFIG_EEPRO100
 432 #undef CONFIG_TULIP
 433
 434 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup  */
 435 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola                     */
 436
 437 #endif /* CONFIG_PCI */
 438
 439 #define CONFIG_NET_MULTI        1
 440
 441 #define CONFIG_MII              1       /* MII PHY management           */
 442 #define CONFIG_TSEC1    1
 443 #define CONFIG_TSEC1_NAME       "TSEC0"
 444 #define CONFIG_TSEC2    1
 445 #define CONFIG_TSEC2_NAME       "TSEC1"
 446 #define TSEC1_PHY_ADDR          2
 447 #define TSEC2_PHY_ADDR          1
 448 #define TSEC1_PHYIDX            0
 449 #define TSEC2_PHYIDX            0
 450 #define TSEC1_FLAGS             TSEC_GIGABIT
 451 #define TSEC2_FLAGS             TSEC_GIGABIT
 452 #define FEC_PHY_ADDR            3
 453 #define FEC_PHYIDX              0
 454 #define FEC_FLAGS               0
 455 #define CONFIG_HAS_ETH0
 456 #define CONFIG_HAS_ETH1
 457 #define CONFIG_HAS_ETH2
 458
 459 #ifdef CONFIG_TQM8548
 460 /*
 461  * TQM8548 has 4 ethernet ports. 4 ETSEC's.
 462  *
 463  * On the STK85xx Starterkit the ETSEC3/4 ports are on an
 464  * additional adapter (AIO) between module and Starterkit.
 465  */
 466 #define CONFIG_TSEC3    1
 467 #define CONFIG_TSEC3_NAME       "TSEC2"
 468 #define CONFIG_TSEC4    1
 469 #define CONFIG_TSEC4_NAME       "TSEC3"
 470 #define TSEC3_PHY_ADDR          4
 471 #define TSEC4_PHY_ADDR          5
 472 #define TSEC3_PHYIDX            0
 473 #define TSEC4_PHYIDX            0
 474 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 475 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 476 #define CONFIG_HAS_ETH3
 477 #define CONFIG_HAS_ETH4
 478 #endif  /* CONFIG_TQM8548 */
 479
 480 /* Options are TSEC[0-1], FEC */
 481 #define CONFIG_ETHPRIME         "TSEC0"
 482
 483 #if defined(CONFIG_TQM8540)
 484 /*
 485  * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
 486  * The FEC port is connected on the same signals as the FCC3 port
 487  * of the TQM8560 to the baseboard (STK85xx Starterkit).
 488  *
 489  * On the STK85xx Starterkit the X47/X50 jumper has to be set to
 490  * a - d (X50.2 - 3) to enable the FEC port.
 491  */
 492 #define CONFIG_MPC85XX_FEC      1
 493 #define CONFIG_MPC85XX_FEC_NAME "FEC"
 494 #endif
 495
 496 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
 497 /*
 498  * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
 499  * can be used at once, since only one FCC port is available on the STK85xx
 500  * Starterkit.
 501  *
 502  * To use this port you have to configure U-Boot to use the FCC port 1...2
 503  * and set the X47/X50 jumper to:
 504  * FCC1: a - b (X47.2 - X50.2)
 505  * FCC2: a - c (X50.2 - 1)
 506  */
 507 #define CONFIG_ETHER_ON_FCC
 508 #define CONFIG_ETHER_INDEX    1 /* FCC channel for ethernet     */
 509 #endif
 510
 511 #if defined(CONFIG_TQM8560)
 512 /*
 513  * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
 514  * can be used at once, since only one FCC port is available on the STK85xx
 515  * Starterkit.
 516  *
 517  * To use this port you have to configure U-Boot to use the FCC port 1...3
 518  * and set the X47/X50 jumper to:
 519  * FCC1: a - b (X47.2 - X50.2)
 520  * FCC2: a - c (X50.2 - 1)
 521  * FCC3: a - d (X50.2 - 3)
 522  */
 523 #define CONFIG_ETHER_ON_FCC
 524 #define CONFIG_ETHER_INDEX    3 /* FCC channel for ethernet     */
 525 #endif
 526
 527 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
 528 #define CONFIG_ETHER_ON_FCC1
 529 #define CFG_CMXFCR_MASK1        (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
 530                                  CMXFCR_TF1CS_MSK)
 531 #define CFG_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
 532 #define CFG_CPMFCR_RAMTYPE      0
 533 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 534 #endif
 535
 536 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 537 #define CONFIG_ETHER_ON_FCC2
 538 #define CFG_CMXFCR_MASK2        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
 539                                  CMXFCR_TF2CS_MSK)
 540 #define CFG_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
 541 #define CFG_CPMFCR_RAMTYPE      0
 542 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 543 #endif
 544
 545 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 546 #define CONFIG_ETHER_ON_FCC3
 547 #define CFG_CMXFCR_MASK3        (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
 548                                  CMXFCR_TF3CS_MSK)
 549 #define CFG_CMXFCR_VALUE3       (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
 550 #define CFG_CPMFCR_RAMTYPE      0
 551 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 552 #endif
 553
 554 /*
 555  * Environment
 556  */
 557 #define CFG_ENV_IS_IN_FLASH     1
 558
 559 #ifdef CONFIG_TQM_FLASH_N_TYPE
 560 #define CFG_ENV_SECT_SIZE       0x40000 /* 256K (one sector) for env    */
 561 #else /* !CONFIG_TQM_FLASH_N_TYPE */
 562 #define CFG_ENV_SECT_SIZE       0x20000 /* 128K (one sector) for env    */
 563 #endif /* CONFIG_TQM_FLASH_N_TYPE */
 564 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
 565 #define CFG_ENV_SIZE            0x2000
 566 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
 567 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 568
 569 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 570 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 571
 572 #define CONFIG_TIMESTAMP        /* Print image info with ts     */
 573
 574 /*
 575  * BOOTP options
 576  */
 577 #define CONFIG_BOOTP_BOOTFILESIZE
 578 #define CONFIG_BOOTP_BOOTPATH
 579 #define CONFIG_BOOTP_GATEWAY
 580 #define CONFIG_BOOTP_HOSTNAME
 581
 582 #ifdef CONFIG_NAND
 583 /*
 584  * Use NAND-FLash as JFFS2 device
 585  */
 586 #define CONFIG_CMD_NAND
 587 #define CONFIG_CMD_JFFS2
 588
 589 #define CONFIG_JFFS2_NAND       1
 590
 591 #ifdef CONFIG_JFFS2_CMDLINE
 592 #define MTDIDS_DEFAULT          "nand0=TQM85xx-nand"
 593 #define MTDPARTS_DEFAULT        "mtdparts=TQM85xx-nand:-"
 594 #else
 595 #define CONFIG_JFFS2_DEV        "nand0" /* NAND device jffs2 lives on   */
 596 #define CONFIG_JFFS2_PART_OFFSET 0      /* start of jffs2 partition     */
 597 #define CONFIG_JFFS2_PART_SIZE  0x200000 /* size of jffs2 partition     */
 598 #endif /* CONFIG_JFFS2_CMDLINE */
 599
 600 #endif /* CONFIG_NAND */
 601
 602 /*
 603  * Command line configuration.
 604  */
 605 #include <config_cmd_default.h>
 606
 607 #define CONFIG_CMD_PING
 608 #define CONFIG_CMD_I2C
 609 #define CONFIG_CMD_DHCP
 610 #define CONFIG_CMD_NFS
 611 #define CONFIG_CMD_SNTP
 612 #define CONFIG_CMD_DATE
 613 #define CONFIG_CMD_EEPROM
 614 #define CONFIG_CMD_DTT
 615 #define CONFIG_CMD_MII
 616
 617 #if defined(CONFIG_PCI)
 618 #define CONFIG_CMD_PCI
 619 #endif
 620
 621 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 622
 623 /*
 624  * Miscellaneous configurable options
 625  */
 626 #define CFG_LONGHELP                    /* undef to save memory         */
 627 #define CFG_LOAD_ADDR   0x2000000       /* default load address         */
 628 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 629
 630 #if defined(CONFIG_CMD_KGDB)
 631 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 632 #else
 633 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 634 #endif
 635
 636 #define CFG_PBSIZE      (CFG_CBSIZE + \
 637                          sizeof(CFG_PROMPT) + 16)   /* Print Buf Size   */
 638 #define CFG_MAXARGS     16              /* max number of command args   */
 639 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 640 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks  */
 641
 642 /*
 643  * For booting Linux, the board info and command line data
 644  * have to be in the first 8 MB of memory, since this is
 645  * the maximum mapped by the Linux kernel during initialization.
 646  */
 647 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux */
 648
 649 /*
 650  * Internal Definitions
 651  *
 652  * Boot Flags
 653  */
 654 #define BOOTFLAG_COLD   0x01            /* Power-On: Boot from FLASH    */
 655 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 656
 657 #if defined(CONFIG_CMD_KGDB)
 658 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port*/
 659 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use     */
 660 #endif
 661
 662 #define CONFIG_LOADADDR  200000         /* default addr for tftp & bootm*/
 663
 664 #define CONFIG_BOOTDELAY 5              /* -1 disables auto-boot        */
 665
 666 #define CONFIG_PREBOOT  "echo;" \
 667         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 668         "echo"
 669
 670 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 671
 672
 673 /*
 674  * Setup some board specific values for the default environment variables
 675  */
 676 #ifdef CONFIG_CPM2
 677 #define CFG_ENV_CONSDEV         "consdev=ttyCPM0\0"
 678 #else
 679 #define CFG_ENV_CONSDEV         "consdev=ttyS0\0"
 680 #endif
 681 #define CFG_ENV_FDT_FILE        "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
 682                                 MK_STR(CONFIG_HOSTNAME)".dtb\0"
 683 #define CFG_ENV_BOOTFILE        "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
 684 #define CFG_ENV_UBOOT           "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
 685                                 "uboot_addr="MK_STR(TEXT_BASE)"\0"
 686
 687 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 688         CFG_ENV_BOOTFILE                                                \
 689         CFG_ENV_FDT_FILE                                                \
 690         CFG_ENV_CONSDEV                                                 \
 691         "netdev=eth0\0"                                                 \
 692         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 693                 "nfsroot=$serverip:$rootpath\0"                         \
 694         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 695         "addip=setenv bootargs $bootargs "                              \
 696                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 697                 ":$hostname:$netdev:off panic=1\0"                      \
 698         "addcons=setenv bootargs $bootargs "                            \
 699                 "console=$consdev,$baudrate\0"                          \
 700         "flash_nfs=run nfsargs addip addcons;"                          \
 701                 "bootm $kernel_addr - $fdt_addr\0"                      \
 702         "flash_self=run ramargs addip addcons;"                         \
 703                 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0"          \
 704         "net_nfs=tftp $kernel_addr_r $bootfile;"                        \
 705                 "tftp $fdt_addr_r $fdt_file;"                           \
 706                 "run nfsargs addip addcons;"                            \
 707                 "bootm $kernel_addr_r - $fdt_addr_r\0"                  \
 708         "rootpath=/opt/eldk/ppc_85xx\0"                                 \
 709         "fdt_addr_r=900000\0"                                           \
 710         "kernel_addr_r=1000000\0"                                       \
 711         "fdt_addr=ffec0000\0"                                           \
 712         "kernel_addr=ffd00000\0"                                        \
 713         "ramdisk_addr=ff800000\0"                                       \
 714         CFG_ENV_UBOOT                                                   \
 715         "load=tftp 100000 $uboot\0"                                     \
 716         "update=protect off $uboot_addr +$filesize;"                    \
 717                 "erase $uboot_addr +$filesize;"                         \
 718                 "cp.b 100000 $uboot_addr $filesize;"                    \
 719                 "setenv filesize;saveenv\0"                             \
 720         "upd=run load update\0"                                         \
 721         ""
 722 #define CONFIG_BOOTCOMMAND      "run flash_self"
 723
 724 #endif /* __CONFIG_H */