include/configs/TQM85xx.h

   1 /*
   2  * (C) Copyright 2007
   3  * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
   4  *
   5  * (C) Copyright 2005
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * Wolfgang Denk <wd@denx.de>
   9  * Copyright 2004 Freescale Semiconductor.
  10  * (C) Copyright 2002,2003 Motorola,Inc.
  11  * Xianghua Xiao <X.Xiao@motorola.com>
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 /*
  33  * TQM85xx (8560/40/55/41/48) board configuration file
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_BOOKE            1       /* BOOKE                        */
  41 #define CONFIG_E500             1       /* BOOKE e500 family            */
  42 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41             */
  43
  44 #if defined(CONFIG_TQM8548_BE)
  45 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  46 #else
  47 #define CONFIG_SYS_TEXT_BASE    0xfffc0000
  48 #endif
  49
  50 #if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
  51 #define CONFIG_TQM8548
  52 #endif
  53
  54 #define CONFIG_PCI
  55 #ifndef CONFIG_TQM8548_AG
  56 #define CONFIG_PCI1                     /* PCI/PCI-X controller         */
  57 #endif
  58 #ifdef CONFIG_TQM8548
  59 #define CONFIG_PCIE1                    /* PCI Express interface        */
  60 #endif
  61
  62 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code     */
  63 #define CONFIG_PCIX_CHECK               /* PCIX olny works at 66 MHz    */
  64 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata       */
  65
  66 #define CONFIG_TSEC_ENET                /* tsec ethernet support        */
  67
  68 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  69
  70  /*
  71  * Configuration for big NOR Flashes
  72  *
  73  * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
  74  * Please be aware, that this changes the whole memory map (new CCSRBAR
  75  * address, etc). You have to use an adapted Linux kernel or FDT blob
  76  * if this option is set.
  77  */
  78 #undef CONFIG_TQM_BIGFLASH
  79
  80 /*
  81  * NAND flash support (disabled by default)
  82  *
  83  * Warning: NAND support will likely increase the U-Boot image size
  84  * to more than 256 KB. Please adjust CONFIG_SYS_TEXT_BASE if necessary.
  85  */
  86 #ifdef CONFIG_TQM8548_BE
  87 #define CONFIG_NAND
  88 #endif
  89
  90 /*
  91  * MPC8540 and MPC8548 don't have CPM module
  92  */
  93 #if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
  94 #define CONFIG_CPM2             1       /* has CPM2                     */
  95 #endif
  96
  97 #define CONFIG_FSL_LAW          1       /* Use common FSL init code     */
  98
  99 #if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
 100 #define CONFIG_CAN_DRIVER               /* CAN Driver support           */
 101 #endif
 102
 103 /*
 104  * sysclk for MPC85xx
 105  *
 106  * Two valid values are:
 107  *    33333333
 108  *    66666666
 109  *
 110  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 111  * is likely the desired value here, so that is now the default.
 112  * The board, however, can run at 66MHz.  In any event, this value
 113  * must match the settings of some switches.  Details can be found
 114  * in the README.mpc85xxads.
 115  */
 116
 117 #ifndef CONFIG_SYS_CLK_FREQ
 118 #define CONFIG_SYS_CLK_FREQ     33333333
 119 #endif
 120
 121 /*
 122  * These can be toggled for performance analysis, otherwise use default.
 123  */
 124 #define CONFIG_L2_CACHE                 /* toggle L2 cache              */
 125 #define CONFIG_BTB                      /* toggle branch predition      */
 126
 127 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions      */
 128
 129 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time      */
 130 #define CONFIG_SYS_MEMTEST_START        0x00000000
 131 #define CONFIG_SYS_MEMTEST_END          0x10000000
 132
 133 #ifdef CONFIG_TQM_BIGFLASH
 134 #define CONFIG_SYS_CCSRBAR              0xA0000000
 135 #else
 136 #define CONFIG_SYS_CCSRBAR              0xE0000000
 137 #endif
 138 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 139
 140 /*
 141  * DDR Setup
 142  */
 143 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory */
 144
 145 #if defined(CONFIG_TQM_BIGFLASH) || \
 146         (!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE))
 147 #define CONFIG_SYS_PPC_DDR_WIMGE (MAS2_I | MAS2_G)
 148 #define CONFIG_SYS_DDR_EARLY_SIZE_MB    (512)
 149 #else
 150 #define CONFIG_SYS_PPC_DDR_WIMGE (0)
 151 #define CONFIG_SYS_DDR_EARLY_SIZE_MB    (2 * 1024)
 152 #endif
 153
 154 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 155 #ifdef CONFIG_TQM8548_AG
 156 #define CONFIG_VERY_BIG_RAM
 157 #endif
 158
 159 #define CONFIG_NUM_DDR_CONTROLLERS      1
 160 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 161 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 162
 163 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
 164 /* TQM8540 & 8560 need DLL-override */
 165 #define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN     /* possible DLL fix needed */
 166 #define CONFIG_DDR_DEFAULT_CL   25              /* CAS latency 2,5      */
 167 #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
 168
 169 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
 170     defined(CONFIG_TQM8548)
 171 #define CONFIG_DDR_DEFAULT_CL   30              /* CAS latency 3        */
 172 #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
 173
 174 /*
 175  * Flash on the Local Bus
 176  */
 177 #ifdef CONFIG_TQM_BIGFLASH
 178 #define CONFIG_SYS_FLASH0               0xE0000000
 179 #define CONFIG_SYS_FLASH1               0xC0000000
 180 #else /* !CONFIG_TQM_BIGFLASH */
 181 #define CONFIG_SYS_FLASH0               0xFC000000
 182 #define CONFIG_SYS_FLASH1               0xF8000000
 183 #endif /* CONFIG_TQM_BIGFLASH */
 184 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 185
 186 #define CONFIG_SYS_LBC_FLASH_BASE       CONFIG_SYS_FLASH1       /* Localbus flash start */
 187 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_LBC_FLASH_BASE  /* start of FLASH    */
 188
 189 /* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
 190  *
 191  * Note: According to timing specifications external addr latch delay
 192  * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
 193  *
 194  * For other Local Bus Clocks see following table:
 195  *
 196  * Clock/MHz   CONFIG_SYS_ORx_PRELIM
 197  * 166         0x.....CA5
 198  * 133         0x.....C85
 199  * 100         0x.....C65
 200  *  83         0x.....FA2
 201  *  66         0x.....C82
 202  *  50         0x.....C60
 203  *  42         0x.....040
 204  *  33         0x.....030
 205  *  25         0x.....020
 206  *
 207  */
 208 #ifdef CONFIG_TQM_BIGFLASH
 209 #define CONFIG_SYS_BR0_PRELIM           0xE0001801      /* port size 32bit      */
 210 #define CONFIG_SYS_OR0_PRELIM           0xE0000040      /* 512MB Flash          */
 211 #define CONFIG_SYS_BR1_PRELIM           0xC0001801      /* port size 32bit      */
 212 #define CONFIG_SYS_OR1_PRELIM           0xE0000040      /* 512MB Flash          */
 213 #else /* !CONFIG_TQM_BIGFLASH */
 214 #define CONFIG_SYS_BR0_PRELIM           0xfc001801      /* port size 32bit      */
 215 #define CONFIG_SYS_OR0_PRELIM           0xfc000040      /* 64MB Flash           */
 216 #define CONFIG_SYS_BR1_PRELIM           0xf8001801      /* port size 32bit      */
 217 #define CONFIG_SYS_OR1_PRELIM           0xfc000040      /* 64MB Flash           */
 218 #endif /* CONFIG_TQM_BIGFLASH */
 219
 220 #define CONFIG_SYS_FLASH_CFI                    /* flash is CFI compat.         */
 221 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 222 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector   */
 223 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash*/
 224 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1 /* speed up output to Flash   */
 225
 226 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks              */
 227 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* sectors per device           */
 228 #undef  CONFIG_SYS_FLASH_CHECKSUM
 229 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms)     */
 230 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms)     */
 231
 232 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor     */
 233
 234 /*
 235  * Note: when changing the Local Bus clock divider you have to
 236  * change the timing values in CONFIG_SYS_ORx_PRELIM.
 237  *
 238  * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
 239  * LCRR[16:17] EADC  : External address delay cycles. It should be set to 2
 240  *                     for Local Bus Clock > 83.3 MHz.
 241  */
 242 #define CONFIG_SYS_LBC_LCRR             0x00030008      /* LB clock ratio reg   */
 243 #define CONFIG_SYS_LBC_LBCR             0x00000000      /* LB config reg        */
 244 #define CONFIG_SYS_LBC_LSRT             0x20000000      /* LB sdram refresh timer */
 245 #define CONFIG_SYS_LBC_MRTPR            0x20000000      /* LB refresh timer presc.*/
 246
 247 #define CONFIG_SYS_INIT_RAM_LOCK        1
 248 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_CCSRBAR \
 249                                  + 0x04010000)  /* Initial RAM address  */
 250 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size used area in RAM        */
 251
 252 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 253 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 254
 255 #define CONFIG_SYS_MONITOR_LEN          (~CONFIG_SYS_TEXT_BASE + 1)/* Reserved for Monitor      */
 256 #define CONFIG_SYS_MALLOC_LEN           (384 * 1024)    /* Reserved for malloc  */
 257
 258 /* Serial Port */
 259 #if defined(CONFIG_TQM8560)
 260
 261 #define CONFIG_CONS_ON_SCC      /* define if console on SCC             */
 262 #undef  CONFIG_CONS_NONE        /* define if console on something else  */
 263 #define CONFIG_CONS_INDEX       1 /* which serial channel for console   */
 264
 265 #else /* !CONFIG_TQM8560 */
 266
 267 #define CONFIG_CONS_INDEX     1
 268 #define CONFIG_SYS_NS16550
 269 #define CONFIG_SYS_NS16550_SERIAL
 270 #define CONFIG_SYS_NS16550_REG_SIZE     1
 271 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 272
 273 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 274 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 275
 276 /* PS/2 Keyboard */
 277 #define CONFIG_PS2KBD                   /* AT-PS/2 Keyboard             */
 278 #define CONFIG_PS2MULT                  /* .. on PS/2 Multiplexer       */
 279 #define CONFIG_PS2SERIAL        2       /* .. on DUART2                 */
 280 #define CONFIG_PS2MULT_DELAY    (CONFIG_SYS_HZ/2)       /* Initial delay        */
 281 #define CONFIG_BOARD_EARLY_INIT_R       1
 282
 283 #endif /* CONFIG_TQM8560 */
 284
 285 #define CONFIG_BAUDRATE         115200
 286
 287 #define CONFIG_SYS_BAUDRATE_TABLE       \
 288         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 289
 290 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 291 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support */
 292 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 293 #ifdef  CONFIG_SYS_HUSH_PARSER
 294 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 295 #endif
 296
 297 /* pass open firmware flat tree */
 298 #define CONFIG_OF_LIBFDT                1
 299 #define CONFIG_OF_BOARD_SETUP           1
 300 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 301
 302 /* CAN */
 303 #define CONFIG_SYS_CAN_BASE             (CONFIG_SYS_CCSRBAR \
 304                                  + 0x03000000)  /* CAN base address     */
 305 #ifdef CONFIG_CAN_DRIVER
 306 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 KiB address mask  */
 307 #define CONFIG_SYS_OR2_CAN              (CONFIG_SYS_CAN_OR_AM | OR_UPM_BI)
 308 #define CONFIG_SYS_BR2_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA) | \
 309                                  BR_PS_8 | BR_MS_UPMC | BR_V)
 310 #endif /* CONFIG_CAN_DRIVER */
 311
 312 /*
 313  * I2C
 314  */
 315 #define CONFIG_FSL_I2C                  /* Use FSL common I2C driver    */
 316 #define CONFIG_HARD_I2C                 /* I2C with hardware support    */
 317 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 318 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 319 #define CONFIG_SYS_I2C_SLAVE            0x7F
 320 #define CONFIG_SYS_I2C_NOPROBES {0x48}  /* Don't probe these addrs      */
 321 #define CONFIG_SYS_I2C_OFFSET           0x3000
 322
 323 /* I2C RTC */
 324 #define CONFIG_RTC_DS1337               /* Use ds1337 rtc via i2c       */
 325 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68              */
 326
 327 /* I2C EEPROM */
 328 /*
 329  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
 330  */
 331 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x             */
 332 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 333 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* =32 Bytes per write  */
 334 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 335 #define CONFIG_SYS_I2C_MULTI_EEPROMS            1       /* more than one eeprom */
 336
 337 /* I2C SYSMON (LM75) */
 338 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 339 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 340 #define CONFIG_SYS_DTT_MAX_TEMP 70
 341 #define CONFIG_SYS_DTT_LOW_TEMP -30
 342 #define CONFIG_SYS_DTT_HYSTERESIS       3
 343
 344 #ifndef CONFIG_PCIE1
 345 /* RapidIO MMU */
 346 #ifdef CONFIG_TQM_BIGFLASH
 347 #define CONFIG_SYS_RIO_MEM_BASE 0xb0000000      /* base address         */
 348 #define CONFIG_SYS_RIO_MEM_SIZE 0x10000000      /* 256M                 */
 349 #else /* !CONFIG_TQM_BIGFLASH */
 350 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000      /* base address         */
 351 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 512M                 */
 352 #endif /* CONFIG_TQM_BIGFLASH */
 353 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
 354 #endif /* CONFIG_PCIE1 */
 355
 356 /* NAND FLASH */
 357 #ifdef CONFIG_NAND
 358
 359 #define CONFIG_NAND_FSL_UPM     1
 360
 361 #define CONFIG_MTD_NAND_ECC_JFFS2       1       /* use JFFS2 ECC        */
 362
 363 /* address distance between chip selects */
 364 #define CONFIG_SYS_NAND_SELECT_DEVICE   1
 365 #define CONFIG_SYS_NAND_CS_DIST 0x200
 366
 367 #define CONFIG_SYS_NAND_SIZE            0x8000
 368 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_CCSRBAR + 0x03010000)
 369
 370 #define CONFIG_SYS_MAX_NAND_DEVICE      1       /* Max number of NAND devices   */
 371 #define CONFIG_SYS_NAND_MAX_CHIPS       2       /* Number of chips per device   */
 372
 373 /* CS3 for NAND Flash */
 374 #define CONFIG_SYS_BR3_PRELIM           ((CONFIG_SYS_NAND_BASE & BR_BA) | \
 375                                          BR_PS_8 | BR_MS_UPMB | BR_V)
 376 #define CONFIG_SYS_OR3_PRELIM           (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
 377
 378 #define NAND_BIG_DELAY_US               25      /* max tR for Samsung devices   */
 379
 380 #endif /* CONFIG_NAND */
 381
 382 /*
 383  * General PCI
 384  * Addresses are mapped 1-1.
 385  */
 386 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 387 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BUS
 388 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M                 */
 389 #define CONFIG_SYS_PCI1_IO_BUS  (CONFIG_SYS_CCSRBAR + 0x02000000)
 390 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS
 391 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000       /*  16M                 */
 392
 393 #ifdef CONFIG_PCIE1
 394 /*
 395  * General PCI express
 396  * Addresses are mapped 1-1.
 397  */
 398 #ifdef CONFIG_TQM_BIGFLASH
 399 #define CONFIG_SYS_PCIE1_MEM_BUS        0xb0000000
 400 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 512M                 */
 401 #define CONFIG_SYS_PCIE1_IO_BUS         0xaf000000
 402 #else /* !CONFIG_TQM_BIGFLASH */
 403 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 404 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M                 */
 405 #define CONFIG_SYS_PCIE1_IO_BUS         0xef000000
 406 #endif /* CONFIG_TQM_BIGFLASH */
 407 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 408 #define CONFIG_SYS_PCIE1_IO_PHYS        CONFIG_SYS_PCIE1_IO_BUS
 409 #define CONFIG_SYS_PCIE1_IO_SIZE        0x1000000       /* 16M                  */
 410 #endif /* CONFIG_PCIE1 */
 411
 412 #if defined(CONFIG_PCI)
 413
 414 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 415
 416 #define CONFIG_EEPRO100
 417 #undef CONFIG_TULIP
 418
 419 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup  */
 420 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola                     */
 421
 422 #endif /* CONFIG_PCI */
 423
 424 #define CONFIG_NET_MULTI        1
 425
 426 #define CONFIG_MII              1       /* MII PHY management           */
 427 #define CONFIG_TSEC1    1
 428 #define CONFIG_TSEC1_NAME       "TSEC0"
 429 #define CONFIG_TSEC2    1
 430 #define CONFIG_TSEC2_NAME       "TSEC1"
 431 #define TSEC1_PHY_ADDR          2
 432 #define TSEC2_PHY_ADDR          1
 433 #define TSEC1_PHYIDX            0
 434 #define TSEC2_PHYIDX            0
 435 #define TSEC1_FLAGS             TSEC_GIGABIT
 436 #define TSEC2_FLAGS             TSEC_GIGABIT
 437 #define FEC_PHY_ADDR            3
 438 #define FEC_PHYIDX              0
 439 #define FEC_FLAGS               0
 440 #define CONFIG_HAS_ETH0
 441 #define CONFIG_HAS_ETH1
 442 #define CONFIG_HAS_ETH2
 443
 444 #ifdef CONFIG_TQM8548
 445 /*
 446  * TQM8548 has 4 ethernet ports. 4 ETSEC's.
 447  *
 448  * On the STK85xx Starterkit the ETSEC3/4 ports are on an
 449  * additional adapter (AIO) between module and Starterkit.
 450  */
 451 #define CONFIG_TSEC3    1
 452 #define CONFIG_TSEC3_NAME       "TSEC2"
 453 #define CONFIG_TSEC4    1
 454 #define CONFIG_TSEC4_NAME       "TSEC3"
 455 #define TSEC3_PHY_ADDR          4
 456 #define TSEC4_PHY_ADDR          5
 457 #define TSEC3_PHYIDX            0
 458 #define TSEC4_PHYIDX            0
 459 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 460 #define TSEC4_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 461 #define CONFIG_HAS_ETH3
 462 #define CONFIG_HAS_ETH4
 463 #endif  /* CONFIG_TQM8548 */
 464
 465 /* Options are TSEC[0-1], FEC */
 466 #define CONFIG_ETHPRIME         "TSEC0"
 467
 468 #if defined(CONFIG_TQM8540)
 469 /*
 470  * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
 471  * The FEC port is connected on the same signals as the FCC3 port
 472  * of the TQM8560 to the baseboard (STK85xx Starterkit).
 473  *
 474  * On the STK85xx Starterkit the X47/X50 jumper has to be set to
 475  * a - d (X50.2 - 3) to enable the FEC port.
 476  */
 477 #define CONFIG_MPC85XX_FEC      1
 478 #define CONFIG_MPC85XX_FEC_NAME "FEC"
 479 #endif
 480
 481 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
 482 /*
 483  * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
 484  * can be used at once, since only one FCC port is available on the STK85xx
 485  * Starterkit.
 486  *
 487  * To use this port you have to configure U-Boot to use the FCC port 1...2
 488  * and set the X47/X50 jumper to:
 489  * FCC1: a - b (X47.2 - X50.2)
 490  * FCC2: a - c (X50.2 - 1)
 491  */
 492 #define CONFIG_ETHER_ON_FCC
 493 #define CONFIG_ETHER_INDEX    1 /* FCC channel for ethernet     */
 494 #endif
 495
 496 #if defined(CONFIG_TQM8560)
 497 /*
 498  * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
 499  * can be used at once, since only one FCC port is available on the STK85xx
 500  * Starterkit.
 501  *
 502  * To use this port you have to configure U-Boot to use the FCC port 1...3
 503  * and set the X47/X50 jumper to:
 504  * FCC1: a - b (X47.2 - X50.2)
 505  * FCC2: a - c (X50.2 - 1)
 506  * FCC3: a - d (X50.2 - 3)
 507  */
 508 #define CONFIG_ETHER_ON_FCC
 509 #define CONFIG_ETHER_INDEX    3 /* FCC channel for ethernet     */
 510 #endif
 511
 512 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
 513 #define CONFIG_ETHER_ON_FCC1
 514 #define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
 515                                  CMXFCR_TF1CS_MSK)
 516 #define CONFIG_SYS_CMXFCR_VALUE1        (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
 517 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 518 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 519 #endif
 520
 521 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 522 #define CONFIG_ETHER_ON_FCC2
 523 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
 524                                  CMXFCR_TF2CS_MSK)
 525 #define CONFIG_SYS_CMXFCR_VALUE2        (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
 526 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 527 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 528 #endif
 529
 530 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 531 #define CONFIG_ETHER_ON_FCC3
 532 #define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
 533                                  CMXFCR_TF3CS_MSK)
 534 #define CONFIG_SYS_CMXFCR_VALUE3        (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
 535 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 536 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
 537 #endif
 538
 539 /*
 540  * Environment
 541  */
 542 #define CONFIG_ENV_IS_IN_FLASH  1
 543
 544 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K (one sector) for env    */
 545 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 546 #define CONFIG_ENV_SIZE         0x2000
 547 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 548 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 549
 550 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 551 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 552
 553 #define CONFIG_TIMESTAMP        /* Print image info with ts     */
 554
 555 /*
 556  * BOOTP options
 557  */
 558 #define CONFIG_BOOTP_BOOTFILESIZE
 559 #define CONFIG_BOOTP_BOOTPATH
 560 #define CONFIG_BOOTP_GATEWAY
 561 #define CONFIG_BOOTP_HOSTNAME
 562
 563 #ifdef CONFIG_NAND
 564 /*
 565  * Use NAND-FLash as JFFS2 device
 566  */
 567 #define CONFIG_CMD_NAND
 568 #define CONFIG_CMD_JFFS2
 569
 570 #define CONFIG_JFFS2_NAND       1
 571
 572 #ifdef CONFIG_CMD_MTDPARTS
 573 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 574 #define CONFIG_FLASH_CFI_MTD
 575 #define MTDIDS_DEFAULT          "nand0=TQM85xx-nand"
 576 #define MTDPARTS_DEFAULT        "mtdparts=TQM85xx-nand:-"
 577 #else
 578 #define CONFIG_JFFS2_DEV        "nand0" /* NAND device jffs2 lives on   */
 579 #define CONFIG_JFFS2_PART_OFFSET 0      /* start of jffs2 partition     */
 580 #define CONFIG_JFFS2_PART_SIZE  0x200000 /* size of jffs2 partition     */
 581 #endif /* CONFIG_CMD_MTDPARTS */
 582
 583 #endif /* CONFIG_NAND */
 584
 585 /*
 586  * Command line configuration.
 587  */
 588 #include <config_cmd_default.h>
 589
 590 #define CONFIG_CMD_PING
 591 #define CONFIG_CMD_I2C
 592 #define CONFIG_CMD_DHCP
 593 #define CONFIG_CMD_NFS
 594 #define CONFIG_CMD_SNTP
 595 #ifndef CONFIG_TQM8548_AG
 596 #define CONFIG_CMD_DATE
 597 #endif
 598 #define CONFIG_CMD_EEPROM
 599 #define CONFIG_CMD_DTT
 600 #define CONFIG_CMD_MII
 601 #define CONFIG_CMD_REGINFO
 602
 603 #if defined(CONFIG_PCI)
 604 #define CONFIG_CMD_PCI
 605 #endif
 606
 607 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 608
 609 /*
 610  * Miscellaneous configurable options
 611  */
 612 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 613 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address         */
 614 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 615
 616 #if defined(CONFIG_CMD_KGDB)
 617 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 618 #else
 619 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 620 #endif
 621
 622 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 623                          sizeof(CONFIG_SYS_PROMPT) + 16)   /* Print Buf Size    */
 624 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 625 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 626 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks  */
 627
 628 /*
 629  * For booting Linux, the board info and command line data
 630  * have to be in the first 8 MB of memory, since this is
 631  * the maximum mapped by the Linux kernel during initialization.
 632  */
 633 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux */
 634
 635 #if defined(CONFIG_CMD_KGDB)
 636 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port*/
 637 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use     */
 638 #endif
 639
 640 #define CONFIG_LOADADDR  200000         /* default addr for tftp & bootm*/
 641
 642 #define CONFIG_BOOTDELAY 5              /* -1 disables auto-boot        */
 643
 644 #define CONFIG_PREBOOT  "echo;" \
 645         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 646         "echo"
 647
 648 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 649
 650
 651 /*
 652  * Setup some board specific values for the default environment variables
 653  */
 654 #ifdef CONFIG_CPM2
 655 #define CONFIG_ENV_CONSDEV              "consdev=ttyCPM0\0"
 656 #else
 657 #define CONFIG_ENV_CONSDEV              "consdev=ttyS0\0"
 658 #endif
 659 #define CONFIG_ENV_FDT_FILE     "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
 660                                 MK_STR(CONFIG_HOSTNAME)".dtb\0"
 661 #define CONFIG_ENV_BOOTFILE     "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
 662 #define CONFIG_ENV_UBOOT                "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
 663                                 "uboot_addr="MK_STR(CONFIG_SYS_TEXT_BASE)"\0"
 664
 665 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 666         CONFIG_ENV_BOOTFILE                                             \
 667         CONFIG_ENV_FDT_FILE                                             \
 668         CONFIG_ENV_CONSDEV                                              \
 669         "netdev=eth0\0"                                                 \
 670         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 671                 "nfsroot=$serverip:$rootpath\0"                         \
 672         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 673         "addip=setenv bootargs $bootargs "                              \
 674                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 675                 ":$hostname:$netdev:off panic=1\0"                      \
 676         "addcons=setenv bootargs $bootargs "                            \
 677                 "console=$consdev,$baudrate\0"                          \
 678         "flash_nfs=run nfsargs addip addcons;"                          \
 679                 "bootm $kernel_addr - $fdt_addr\0"                      \
 680         "flash_self=run ramargs addip addcons;"                         \
 681                 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0"          \
 682         "net_nfs=tftp $kernel_addr_r $bootfile;"                        \
 683                 "tftp $fdt_addr_r $fdt_file;"                           \
 684                 "run nfsargs addip addcons;"                            \
 685                 "bootm $kernel_addr_r - $fdt_addr_r\0"                  \
 686         "rootpath=/opt/eldk/ppc_85xx\0"                                 \
 687         "fdt_addr_r=900000\0"                                           \
 688         "kernel_addr_r=1000000\0"                                       \
 689         "fdt_addr=ffec0000\0"                                           \
 690         "kernel_addr=ffd00000\0"                                        \
 691         "ramdisk_addr=ff800000\0"                                       \
 692         CONFIG_ENV_UBOOT                                                \
 693         "load=tftp 100000 $uboot\0"                                     \
 694         "update=protect off $uboot_addr +$filesize;"                    \
 695                 "erase $uboot_addr +$filesize;"                         \
 696                 "cp.b 100000 $uboot_addr $filesize"                     \
 697         "upd=run load update\0"                                         \
 698         ""
 699 #define CONFIG_BOOTCOMMAND      "run flash_self"
 700
 701 #endif /* __CONFIG_H */