include/configs/TQM85xx.h

   1 /*
   2  * (C) Copyright 2005
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * Wolfgang Denk <wd@denx.de>
   6  * Copyright 2004 Freescale Semiconductor.
   7  * (C) Copyright 2002,2003 Motorola,Inc.
   8  * Xianghua Xiao <X.Xiao@motorola.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /*
  30  * TQM85xx (8560/40/55/41) board configuration file
  31  */
  32
  33 #ifndef __CONFIG_H
  34 #define __CONFIG_H
  35
  36 /* High Level Configuration Options */
  37 #define CONFIG_BOOKE            1       /* BOOKE                        */
  38 #define CONFIG_E500             1       /* BOOKE e500 family            */
  39 #define CONFIG_MPC85xx          1       /* MPC8540/60/55/41             */
  40
  41 #define CONFIG_PCI
  42 #define CONFIG_TSEC_ENET                /* tsec ethernet support        */
  43
  44 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  45
  46 /*
  47  * Only MPC8540 doesn't have CPM module
  48  */
  49 #ifndef CONFIG_MPC8540
  50 #define CONFIG_CPM2             1       /* has CPM2                     */
  51 #endif
  52
  53 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  54
  55 /*
  56  * sysclk for MPC85xx
  57  *
  58  * Two valid values are:
  59  *    33000000
  60  *    66000000
  61  *
  62  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  63  * is likely the desired value here, so that is now the default.
  64  * The board, however, can run at 66MHz.  In any event, this value
  65  * must match the settings of some switches.  Details can be found
  66  * in the README.mpc85xxads.
  67  */
  68
  69 #ifndef CONFIG_SYS_CLK_FREQ
  70 #define CONFIG_SYS_CLK_FREQ     33333333
  71 #endif
  72
  73 /*
  74  * These can be toggled for performance analysis, otherwise use default.
  75  */
  76 #define CONFIG_L2_CACHE                 /* toggle L2 cache              */
  77 #define CONFIG_BTB                      /* toggle branch predition      */
  78 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming        */
  79
  80 #define CFG_INIT_DBCR DBCR_IDM          /* Enable Debug Exceptions      */
  81
  82 #undef  CFG_DRAM_TEST                   /* memory test, takes time      */
  83 #define CFG_MEMTEST_START       0x00000000
  84 #define CFG_MEMTEST_END         0x10000000
  85
  86 /*
  87  * Base addresses -- Note these are effective addresses where the
  88  * actual resources get mapped (not physical addresses)
  89  */
  90 #define CFG_CCSRBAR_DEFAULT     0xFF700000      /* CCSRBAR Default      */
  91 #define CFG_CCSRBAR             0xE0000000      /* relocated CCSRBAR    */
  92 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR   */
  93
  94 /*
  95  * DDR Setup
  96  */
  97 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory */
  98 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
  99
 100 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
 101 /* TQM8540 & 8560 need DLL-override */
 102 #define CONFIG_DDR_DLL                          /* DLL fix needed       */
 103 #define CONFIG_DDR_DEFAULT_CL   25              /* CAS latency 2,5      */
 104 #endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */
 105
 106 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
 107 #define CONFIG_DDR_DEFAULT_CL   30              /* CAS latency 3        */
 108 #endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */
 109
 110 /*
 111  * Flash on the Local Bus
 112  */
 113 #define CFG_FLASH0              0xFC000000
 114 #define CFG_FLASH1              0xF8000000
 115 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH1, CFG_FLASH0 }
 116
 117 #define CFG_LBC_FLASH_BASE      CFG_FLASH1      /* Localbus flash start */
 118 #define CFG_FLASH_BASE          CFG_LBC_FLASH_BASE /* start of FLASH    */
 119
 120 #define CFG_BR0_PRELIM          0xfc001801      /* port size 32bit      */
 121 #define CFG_OR0_PRELIM          0xfc000040      /* 64MB Flash           */
 122 #define CFG_BR1_PRELIM          0xf8001801      /* port size 32bit      */
 123 #define CFG_OR1_PRELIM          0xfc000040      /* 64MB Flash           */
 124
 125 #define CFG_FLASH_CFI                           /* flash is CFI compat. */
 126 #define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver*/
 127 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector   */
 128 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash*/
 129
 130 #define CFG_MAX_FLASH_BANKS     2               /* number of banks      */
 131 #define CFG_MAX_FLASH_SECT      512             /* sectors per device   */
 132 #undef  CFG_FLASH_CHECKSUM
 133 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms)     */
 134 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms)     */
 135
 136 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor     */
 137
 138 #define CFG_LBC_LCRR            0x00030008    /* LB clock ratio reg     */
 139 #define CFG_LBC_LBCR            0x00000000    /* LB config reg          */
 140 #define CFG_LBC_LSRT            0x20000000    /* LB sdram refresh timer */
 141 #define CFG_LBC_MRTPR           0x20000000    /* LB refresh timer presc.*/
 142
 143 #define CONFIG_L1_INIT_RAM
 144 #define CFG_INIT_RAM_LOCK       1
 145 #define CFG_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address  */
 146 #define CFG_INIT_RAM_END        0x4000          /* End used area in RAM */
 147
 148 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data*/
 149 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 150 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 151
 152 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256kB for Mon*/
 153 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc  */
 154
 155 /* Serial Port */
 156 #if defined(CONFIG_TQM8560)
 157
 158 #define CONFIG_CONS_ON_SCC      /* define if console on SCC */
 159 #undef  CONFIG_CONS_NONE        /* define if console on something else */
 160 #define CONFIG_CONS_INDEX       1  /* which serial channel for console */
 161
 162 #else   /* ! TQM8560 */
 163
 164 #define CONFIG_CONS_INDEX     1
 165 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 166 #define CFG_NS16550
 167 #define CFG_NS16550_SERIAL
 168 #define CFG_NS16550_REG_SIZE    1
 169 #define CFG_NS16550_CLK         get_bus_freq(0)
 170
 171 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 172 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 173
 174 /* PS/2 Keyboard */
 175 #if !defined(CONFIG_TQM8560)
 176 #define CONFIG_PS2KBD                   /* AT-PS/2 Keyboard             */
 177 #define CONFIG_PS2MULT                  /* .. on PS/2 Multiplexer       */
 178 #define CONFIG_PS2SERIAL        2       /* .. on DUART2                 */
 179 #define CONFIG_PS2MULT_DELAY    (CFG_HZ/2)      /* Initial delay        */
 180 #define CONFIG_BOARD_EARLY_INIT_R       1
 181 #endif /* !CONFIG_TQM8560 */
 182
 183 #endif /* CONFIG_TQM8560 */
 184
 185 #define CONFIG_BAUDRATE         115200
 186
 187 #define CFG_BAUDRATE_TABLE  \
 188         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 189
 190 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 191 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 192 #ifdef  CFG_HUSH_PARSER
 193 #define CFG_PROMPT_HUSH_PS2     "> "
 194 #endif
 195
 196
 197 /*
 198  * I2C
 199  */
 200 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 201 #define CONFIG_HARD_I2C                 /* I2C with hardware support    */
 202 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 203 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 204 #define CFG_I2C_SLAVE           0x7F
 205 #define CFG_I2C_NOPROBES        {0x48}  /* Don't probe these addrs      */
 206 #define CFG_I2C_OFFSET          0x3000
 207
 208 /* I2C RTC */
 209 #define CONFIG_RTC_DS1337               /* Use ds1337 rtc via i2c       */
 210 #define CFG_I2C_RTC_ADDR        0x68    /* at address 0x68              */
 211
 212 /* I2C EEPROM */
 213 /*
 214  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
 215  */
 216 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x             */
 217 #define CFG_I2C_EEPROM_ADDR_LEN         2
 218 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write  */
 219 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 220 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 221 #define CFG_I2C_MULTI_EEPROMS           1       /* more than one eeprom */
 222
 223 /* I2C SYSMON (LM75) */
 224 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 225 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 226 #define CFG_DTT_MAX_TEMP        70
 227 #define CFG_DTT_LOW_TEMP        -30
 228 #define CFG_DTT_HYSTERESIS      3
 229
 230 /* RapidIO MMU */
 231 #define CFG_RIO_MEM_BASE        0xc0000000      /* base address         */
 232 #define CFG_RIO_MEM_PHYS        CFG_RIO_MEM_BASE
 233 #define CFG_RIO_MEM_SIZE        0x20000000      /* 128M                 */
 234
 235 /*
 236  * General PCI
 237  * Addresses are mapped 1-1.
 238  */
 239 #define CFG_PCI1_MEM_BASE       0x80000000
 240 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 241 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M                 */
 242 #define CFG_PCI1_IO_BASE        0xe2000000
 243 #define CFG_PCI1_IO_PHYS        CFG_PCI1_IO_BASE
 244 #define CFG_PCI1_IO_SIZE        0x1000000       /* 16M                  */
 245
 246 #if defined(CONFIG_PCI)
 247
 248 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 249
 250 #define CONFIG_EEPRO100
 251 #undef CONFIG_TULIP
 252
 253 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup  */
 254 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola                     */
 255
 256 #endif  /* CONFIG_PCI */
 257
 258
 259 #define CONFIG_NET_MULTI        1
 260
 261 #define CONFIG_MII              1       /* MII PHY management           */
 262 #define CONFIG_TSEC1    1
 263 #define CONFIG_TSEC1_NAME       "TSEC0"
 264 #define CONFIG_TSEC2    1
 265 #define CONFIG_TSEC2_NAME       "TSEC1"
 266 #define TSEC1_PHY_ADDR          2
 267 #define TSEC2_PHY_ADDR          1
 268 #define TSEC1_PHYIDX            0
 269 #define TSEC2_PHYIDX            0
 270 #define TSEC1_FLAGS             TSEC_GIGABIT
 271 #define TSEC2_FLAGS             TSEC_GIGABIT
 272 #define FEC_PHY_ADDR            3
 273 #define FEC_PHYIDX              0
 274 #define FEC_FLAGS               0
 275 #define CONFIG_HAS_ETH0
 276 #define CONFIG_HAS_ETH1
 277 #define CONFIG_HAS_ETH2
 278
 279 /* Options are TSEC[0-1], FEC */
 280 #define CONFIG_ETHPRIME         "TSEC0"
 281
 282 #if defined(CONFIG_TQM8540)
 283 /*
 284  * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
 285  * The FEC port is connected on the same signals as the FCC3 port
 286  * of the TQM8560 to the baseboard (STK85xx Starterkit).
 287  *
 288  * On the STK85xx Starterkit the X47/X50 jumper has to be set to
 289  * a - d (X50.2 - 3) to enable the FEC port.
 290  */
 291 #define CONFIG_MPC85XX_FEC      1
 292 #define CONFIG_MPC85XX_FEC_NAME "FEC"
 293 #endif
 294
 295 #if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
 296 /*
 297  * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
 298  * can be used at once, since only one FCC port is available on the STK85xx
 299  * Starterkit.
 300  *
 301  * To use this port you have to configure U-Boot to use the FCC port 1...2
 302  * and set the X47/X50 jumper to:
 303  * FCC1: a - b (X47.2 - X50.2)
 304  * FCC2: a - c (X50.2 - 1)
 305  */
 306 #define CONFIG_ETHER_ON_FCC
 307 #define CONFIG_ETHER_INDEX    1         /* FCC channel for ethernet     */
 308 #endif
 309
 310 #if defined(CONFIG_TQM8560)
 311 /*
 312  * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
 313  * can be used at once, since only one FCC port is available on the STK85xx
 314  * Starterkit.
 315  *
 316  * To use this port you have to configure U-Boot to use the FCC port 1...3
 317  * and set the X47/X50 jumper to:
 318  * FCC1: a - b (X47.2 - X50.2)
 319  * FCC2: a - c (X50.2 - 1)
 320  * FCC3: a - d (X50.2 - 3)
 321  */
 322 #define CONFIG_ETHER_ON_FCC
 323 #define CONFIG_ETHER_INDEX    3         /* FCC channel for ethernet     */
 324 #endif
 325
 326 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
 327 #define CONFIG_ETHER_ON_FCC1
 328 #define CFG_CMXFCR_MASK1        (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
 329 #define CFG_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
 330 #define CFG_CPMFCR_RAMTYPE      0
 331 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 332 #endif
 333
 334 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 335 #define CONFIG_ETHER_ON_FCC2
 336 #define CFG_CMXFCR_MASK2        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 337 #define CFG_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
 338 #define CFG_CPMFCR_RAMTYPE      0
 339 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 340 #endif
 341
 342 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 343 #define CONFIG_ETHER_ON_FCC3
 344 #define CFG_CMXFCR_MASK3        (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
 345 #define CFG_CMXFCR_VALUE3       (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
 346 #define CFG_CPMFCR_RAMTYPE      0
 347 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
 348 #endif
 349
 350 /*
 351  * Environment
 352  */
 353 #define CFG_ENV_IS_IN_FLASH     1
 354 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - 0x20000)
 355 #define CFG_ENV_SECT_SIZE       0x20000 /* 128K(one sector) for env     */
 356 #define CFG_ENV_SIZE            0x2000
 357 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 358 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 359
 360 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 361 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 362
 363 #define CONFIG_TIMESTAMP                /* Print image info with ts     */
 364
 365
 366 /*
 367  * BOOTP options
 368  */
 369 #define CONFIG_BOOTP_BOOTFILESIZE
 370 #define CONFIG_BOOTP_BOOTPATH
 371 #define CONFIG_BOOTP_GATEWAY
 372 #define CONFIG_BOOTP_HOSTNAME
 373
 374
 375 /*
 376  * Command line configuration.
 377  */
 378 #include <config_cmd_default.h>
 379
 380 #define CONFIG_CMD_PING
 381 #define CONFIG_CMD_I2C
 382 #define CONFIG_CMD_DHCP
 383 #define CONFIG_CMD_NFS
 384 #define CONFIG_CMD_SNTP
 385 #define CONFIG_CMD_DATE
 386 #define CONFIG_CMD_EEPROM
 387 #define CONFIG_CMD_DTT
 388 #define CONFIG_CMD_MII
 389
 390 #if defined(CONFIG_PCI)
 391     #define CONFIG_CMD_PCI
 392 #endif
 393
 394
 395 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 396
 397 /*
 398  * Miscellaneous configurable options
 399  */
 400 #define CFG_LONGHELP                    /* undef to save memory         */
 401 #define CFG_LOAD_ADDR   0x2000000       /* default load address         */
 402 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 403
 404 #if defined(CONFIG_CMD_KGDB)
 405     #define CFG_CBSIZE  1024            /* Console I/O Buffer Size      */
 406 #else
 407     #define CFG_CBSIZE  256             /* Console I/O Buffer Size      */
 408 #endif
 409
 410 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */
 411 #define CFG_MAXARGS     16              /* max number of command args   */
 412 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 413 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks  */
 414
 415 /*
 416  * For booting Linux, the board info and command line data
 417  * have to be in the first 8 MB of memory, since this is
 418  * the maximum mapped by the Linux kernel during initialization.
 419  */
 420 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux */
 421
 422 /*
 423  * Internal Definitions
 424  *
 425  * Boot Flags
 426  */
 427 #define BOOTFLAG_COLD   0x01            /* Power-On: Boot from FLASH    */
 428 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 429
 430 #if defined(CONFIG_CMD_KGDB)
 431 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port*/
 432 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use     */
 433 #endif
 434
 435
 436 #define CONFIG_LOADADDR  200000         /* default addr for tftp & bootm*/
 437
 438 #define CONFIG_BOOTDELAY 5              /* -1 disables auto-boot        */
 439
 440 #define CONFIG_PREBOOT  "echo;" \
 441         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 442         "echo"
 443
 444 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 445
 446 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 447         "bootfile="CFG_BOOTFILE_PATH"\0"                                \
 448         "netdev=eth0\0"                                                 \
 449         "consdev=ttyS0\0"                                               \
 450         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 451                 "nfsroot=$serverip:$rootpath\0"                         \
 452         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 453         "addip=setenv bootargs $bootargs "                              \
 454                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 455                 ":$hostname:$netdev:off panic=1\0"                      \
 456         "addcons=setenv bootargs $bootargs "                            \
 457                 "console=$consdev,$baudrate\0"                          \
 458         "flash_nfs=run nfsargs addip addcons;"                          \
 459                 "bootm $kernel_addr\0"                                  \
 460         "flash_self=run ramargs addip addcons;"                         \
 461                 "bootm $kernel_addr $ramdisk_addr\0"                    \
 462         "net_nfs=tftp $loadaddr $bootfile;"                             \
 463                 "run nfsargs addip addcons;bootm\0"                     \
 464         "rootpath=/opt/eldk/ppc_85xx\0"                                 \
 465         "kernel_addr=FE000000\0"                                        \
 466         "ramdisk_addr=FE180000\0"                                       \
 467         "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0"             \
 468         "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"   \
 469                 "cp.b 100000 fffc0000 40000;"                           \
 470                 "setenv filesize;saveenv\0"                             \
 471         "upd=run load;run update\0"                                     \
 472         ""
 473 #define CONFIG_BOOTCOMMAND      "run flash_self"
 474
 475 #endif  /* __CONFIG_H */