include/configs/TQM860L.h

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC860           1       /* This is a MPC860 CPU         */
  37 #define CONFIG_TQM860L          1       /* ...on a TQM8xxL module       */
  38
  39 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  40 #undef  CONFIG_8xx_CONS_SMC2
  41 #undef  CONFIG_8xx_CONS_NONE
  42
  43 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  44
  45 #define CONFIG_BOOTCOUNT_LIMIT
  46
  47 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  48
  49 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  50
  51 #define CONFIG_PREBOOT  "echo;" \
  52         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  53         "echo"
  54
  55 #undef  CONFIG_BOOTARGS
  56
  57 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  58         "netdev=eth0\0"                                                 \
  59         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  60                 "nfsroot=$(serverip):$(rootpath)\0"                     \
  61         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  62         "addip=setenv bootargs $(bootargs) "                            \
  63                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
  64                 ":$(hostname):$(netdev):off panic=1\0"                  \
  65         "flash_nfs=run nfsargs addip;"                                  \
  66                 "bootm $(kernel_addr)\0"                                \
  67         "flash_self=run ramargs addip;"                                 \
  68                 "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
  69         "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"     \
  70         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  71         "bootfile=/tftpboot/TQM860L/uImage\0"                           \
  72         "kernel_addr=40040000\0"                                        \
  73         "ramdisk_addr=40100000\0"                                       \
  74         ""
  75 #define CONFIG_BOOTCOMMAND      "run flash_self"
  76
  77 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  78 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  79
  80 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  81
  82 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  83
  84 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  85
  86 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  87
  88 #define CONFIG_MAC_PARTITION
  89 #define CONFIG_DOS_PARTITION
  90
  91 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  92
  93 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
  94                                 CFG_CMD_ASKENV  | \
  95                                 CFG_CMD_DHCP    | \
  96                                 CFG_CMD_ELF     | \
  97                                 CFG_CMD_IDE     | \
  98                                 CFG_CMD_DATE    )
  99
 100 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 101 #include <cmd_confdefs.h>
 102
 103 /*
 104  * Miscellaneous configurable options
 105  */
 106 #define CFG_LONGHELP                    /* undef to save memory         */
 107 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 108
 109 #if 0
 110 #define CFG_HUSH_PARSER         1       /* use "hush" command parser    */
 111 #endif
 112 #ifdef  CFG_HUSH_PARSER
 113 #define CFG_PROMPT_HUSH_PS2     "> "
 114 #endif
 115
 116 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 117 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 118 #else
 119 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 120 #endif
 121 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 122 #define CFG_MAXARGS             16      /* max number of command args   */
 123 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 124
 125 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 126 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 127
 128 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 129
 130 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 131
 132 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 133
 134 /*
 135  * Low Level Configuration Settings
 136  * (address mappings, register initial values, etc.)
 137  * You should know what you are doing if you make changes here.
 138  */
 139 /*-----------------------------------------------------------------------
 140  * Internal Memory Mapped Register
 141  */
 142 #define CFG_IMMR                0xFFF00000
 143
 144 /*-----------------------------------------------------------------------
 145  * Definitions for initial stack pointer and data area (in DPRAM)
 146  */
 147 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 148 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 149 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 150 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 151 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 152
 153 /*-----------------------------------------------------------------------
 154  * Start addresses for the final memory configuration
 155  * (Set up by the startup code)
 156  * Please note that CFG_SDRAM_BASE _must_ start at 0
 157  */
 158 #define CFG_SDRAM_BASE          0x00000000
 159 #define CFG_FLASH_BASE          0x40000000
 160 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 161 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 162 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 163
 164 /*
 165  * For booting Linux, the board info and command line data
 166  * have to be in the first 8 MB of memory, since this is
 167  * the maximum mapped by the Linux kernel during initialization.
 168  */
 169 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 170
 171 /*-----------------------------------------------------------------------
 172  * FLASH organization
 173  */
 174 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 175 #define CFG_MAX_FLASH_SECT      71      /* max number of sectors on one chip    */
 176
 177 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 178 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 179
 180 #define CFG_ENV_IS_IN_FLASH     1
 181 #define CFG_ENV_OFFSET          0x8000  /*   Offset   of Environment Sector     */
 182 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 183
 184 /* Address and size of Redundant Environment Sector     */
 185 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
 186 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 187
 188 /*-----------------------------------------------------------------------
 189  * Hardware Information Block
 190  */
 191 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 192 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 193 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 194
 195 /*-----------------------------------------------------------------------
 196  * Cache Configuration
 197  */
 198 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 199 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 200 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 201 #endif
 202
 203 /*-----------------------------------------------------------------------
 204  * SYPCR - System Protection Control                            11-9
 205  * SYPCR can only be written once after reset!
 206  *-----------------------------------------------------------------------
 207  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 208  */
 209 #if defined(CONFIG_WATCHDOG)
 210 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 211                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 212 #else
 213 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 214 #endif
 215
 216 /*-----------------------------------------------------------------------
 217  * SIUMCR - SIU Module Configuration                            11-6
 218  *-----------------------------------------------------------------------
 219  * PCMCIA config., multi-function pin tri-state
 220  */
 221 #ifndef CONFIG_CAN_DRIVER
 222 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 223 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 224 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 225 #endif  /* CONFIG_CAN_DRIVER */
 226
 227 /*-----------------------------------------------------------------------
 228  * TBSCR - Time Base Status and Control                         11-26
 229  *-----------------------------------------------------------------------
 230  * Clear Reference Interrupt Status, Timebase freezing enabled
 231  */
 232 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 233
 234 /*-----------------------------------------------------------------------
 235  * RTCSC - Real-Time Clock Status and Control Register          11-27
 236  *-----------------------------------------------------------------------
 237  */
 238 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 239
 240 /*-----------------------------------------------------------------------
 241  * PISCR - Periodic Interrupt Status and Control                11-31
 242  *-----------------------------------------------------------------------
 243  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 244  */
 245 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 246
 247 /*-----------------------------------------------------------------------
 248  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 249  *-----------------------------------------------------------------------
 250  * Reset PLL lock status sticky bit, timer expired status bit and timer
 251  * interrupt status bit
 252  */
 253 #define CFG_PLPRCR      (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 254
 255 /*-----------------------------------------------------------------------
 256  * SCCR - System Clock and reset Control Register               15-27
 257  *-----------------------------------------------------------------------
 258  * Set clock output, timebase and RTC source and divider,
 259  * power management and some other internal clocks
 260  */
 261 #define SCCR_MASK       SCCR_EBDF11
 262 #define CFG_SCCR        (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 263                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 264                          SCCR_DFALCD00)
 265
 266 /*-----------------------------------------------------------------------
 267  * PCMCIA stuff
 268  *-----------------------------------------------------------------------
 269  *
 270  */
 271 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 272 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 273 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 274 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 275 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 276 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 277 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 278 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 279
 280 /*-----------------------------------------------------------------------
 281  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 282  *-----------------------------------------------------------------------
 283  */
 284
 285 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 286
 287 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 288 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 289 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 290
 291 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 292 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 293
 294 #define CFG_ATA_IDE0_OFFSET     0x0000
 295
 296 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 297
 298 /* Offset for data I/O                  */
 299 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 300
 301 /* Offset for normal register accesses  */
 302 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 303
 304 /* Offset for alternate registers       */
 305 #define CFG_ATA_ALT_OFFSET      0x0100
 306
 307 /*-----------------------------------------------------------------------
 308  *
 309  *-----------------------------------------------------------------------
 310  *
 311  */
 312 #define CFG_DER 0
 313
 314 /*
 315  * Init Memory Controller:
 316  *
 317  * BR0/1 and OR0/1 (FLASH)
 318  */
 319
 320 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 321 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 322
 323 /* used to re-map FLASH both when starting from SRAM or FLASH:
 324  * restrict access enough to keep SRAM working (if any)
 325  * but not too much to meddle with FLASH accesses
 326  */
 327 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 328 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 329
 330 /*
 331  * FLASH timing:
 332  */
 333 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 334                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 335
 336 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 337 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 338 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 339
 340 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 341 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 342 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 343
 344 /*
 345  * BR2/3 and OR2/3 (SDRAM)
 346  *
 347  */
 348 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 349 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 350 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 351
 352 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 353 #define CFG_OR_TIMING_SDRAM     0x00000A00
 354
 355 #define CFG_OR2_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 356 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 357
 358 #ifndef CONFIG_CAN_DRIVER
 359 #define CFG_OR3_PRELIM  CFG_OR2_PRELIM
 360 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 361 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 362 #define CFG_CAN_BASE            0xC0000000      /* CAN mapped at 0xC0000000     */
 363 #define CFG_CAN_OR_AM           0xFFFF8000      /* 32 kB address mask           */
 364 #define CFG_OR3_CAN             (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
 365 #define CFG_BR3_CAN             ((CFG_CAN_BASE & BR_BA_MSK) | \
 366                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 367 #endif  /* CONFIG_CAN_DRIVER */
 368
 369 /*
 370  * Memory Periodic Timer Prescaler
 371  *
 372  * The Divider for PTA (refresh timer) configuration is based on an
 373  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 374  * the number of chip selects (NCS) and the actually needed refresh
 375  * rate is done by setting MPTPR.
 376  *
 377  * PTA is calculated from
 378  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 379  *
 380  *      gclk      CPU clock (not bus clock!)
 381  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 382  *
 383  * 4096  Rows from SDRAM example configuration
 384  * 1000  factor s -> ms
 385  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 386  *    4  Number of refresh cycles per period
 387  *   64  Refresh cycle in ms per number of rows
 388  * --------------------------------------------
 389  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 390  *
 391  * 50 MHz => 50.000.000 / Divider =  98
 392  * 66 Mhz => 66.000.000 / Divider = 129
 393  * 80 Mhz => 80.000.000 / Divider = 156
 394  */
 395
 396 #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
 397 #define CFG_MAMR_PTA    98
 398
 399 /*
 400  * For 16 MBit, refresh rates could be 31.3 us
 401  * (= 64 ms / 2K = 125 / quad bursts).
 402  * For a simpler initialization, 15.6 us is used instead.
 403  *
 404  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 405  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 406  */
 407 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 408 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 409
 410 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 411 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 412 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 413
 414 /*
 415  * MAMR settings for SDRAM
 416  */
 417
 418 /* 8 column SDRAM */
 419 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 420                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 421                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 422 /* 9 column SDRAM */
 423 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 424                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 425                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 426
 427
 428 /*
 429  * Internal Definitions
 430  *
 431  * Boot Flags
 432  */
 433 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 434 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 435
 436 #define CONFIG_SCC1_ENET
 437 #define CONFIG_FEC_ENET
 438 #define CONFIG_ETHPRIME         "SCC ETHERNET"
 439
 440 #endif  /* __CONFIG_H */