include/configs/TQM866M.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC866           1       /* This is a MPC866 CPU         */
  37 #define CONFIG_TQM866M          1       /* ...on a TQM8xxM module       */
  38
  39 #define CONFIG_8xx_OSCLK                10000000        /*  10 MHz - PLL input clock    */
  40 #define CFG_8xx_CPUCLK_MIN              15000000        /*  15 MHz - CPU minimum clock  */
  41 #define CFG_8xx_CPUCLK_MAX              133000000       /* 133 MHz - CPU maximum clock  */
  42 #define CONFIG_8xx_CPUCLK_DEFAULT       50000000        /*  50 MHz - CPU default clock  */
  43                                                 /* (it will be used if there is no      */
  44                                                 /* 'cpuclk' variable with valid value)  */
  45
  46 #undef CFG_MEASURE_CPUCLK                       /* Measure real cpu clock       */
  47                                                 /* (function measure_gclk()     */
  48                                                 /* will be called)              */
  49 #ifdef CFG_MEASURE_CPUCLK
  50 #define CFG_8XX_XIN             10000000        /* measure_gclk() needs this    */
  51 #endif
  52
  53 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  54
  55 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  56
  57 #define CONFIG_BOOTCOUNT_LIMIT
  58
  59 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  60
  61 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  62
  63 #define CONFIG_PREBOOT  "echo;" \
  64         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  65         "echo"
  66
  67 #undef  CONFIG_BOOTARGS
  68
  69 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  70         "netdev=eth0\0"                                                 \
  71         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  72                 "nfsroot=${serverip}:${rootpath}\0"                     \
  73         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  74         "addip=setenv bootargs ${bootargs} "                            \
  75                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  76                 ":${hostname}:${netdev}:off panic=1\0"                  \
  77         "flash_nfs=run nfsargs addip;"                                  \
  78                 "bootm ${kernel_addr}\0"                                \
  79         "flash_self=run ramargs addip;"                                 \
  80                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  81         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  82         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  83         "bootfile=/tftpboot/TQM866M/uImage\0"                           \
  84         "kernel_addr=40080000\0"                                        \
  85         "ramdisk_addr=40180000\0"                                       \
  86         ""
  87 #define CONFIG_BOOTCOMMAND      "run flash_self"
  88
  89 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  90 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  91
  92 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  93
  94 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  95
  96 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  97
  98 /* enable I2C and select the hardware/software driver */
  99 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 100 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 101
 102 #define CFG_I2C_SPEED           93000   /* 93 kHz is supposed to work   */
 103 #define CFG_I2C_SLAVE           0xFE
 104
 105 #ifdef CONFIG_SOFT_I2C
 106 /*
 107  * Software (bit-bang) I2C driver configuration
 108  */
 109 #define PB_SCL          0x00000020      /* PB 26 */
 110 #define PB_SDA          0x00000010      /* PB 27 */
 111
 112 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 113 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 114 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 115 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 116 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 117                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 118 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 119                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 120 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 121 #endif  /* CONFIG_SOFT_I2C */
 122
 123 #define CFG_I2C_EEPROM_ADDR     0x50            /* EEPROM AT24C256      */
 124 #define CFG_I2C_EEPROM_ADDR_LEN 2               /* two byte address     */
 125 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 126 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 127
 128 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
 129
 130 #define CONFIG_MAC_PARTITION
 131 #define CONFIG_DOS_PARTITION
 132
 133 #undef CONFIG_RTC_MPC8xx                /* MPC866 does not support RTC  */
 134
 135 #define CONFIG_TIMESTAMP                /* but print image timestmps    */
 136
 137
 138 /*
 139  * Command line configuration.
 140  */
 141 #include <config_cmd_default.h>
 142
 143 #define CONFIG_CMD_ASKENV
 144 #define CONFIG_CMD_DHCP
 145 #define CONFIG_CMD_EEPROM
 146 #define CONFIG_CMD_I2C
 147 #define CONFIG_CMD_IDE
 148 #define CONFIG_CMD_NFS
 149
 150
 151 /*
 152  * Miscellaneous configurable options
 153  */
 154 #define CFG_LONGHELP                    /* undef to save memory         */
 155 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 156
 157 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 158 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 159 #ifdef  CFG_HUSH_PARSER
 160 #define CFG_PROMPT_HUSH_PS2     "> "
 161 #endif
 162
 163 #if defined(CONFIG_CMD_KGDB)
 164 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 165 #else
 166 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 167 #endif
 168 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 169 #define CFG_MAXARGS             16      /* max number of command args   */
 170 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 171
 172 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 173 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 174
 175 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 176
 177 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 178
 179 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 180
 181 /*
 182  * Low Level Configuration Settings
 183  * (address mappings, register initial values, etc.)
 184  * You should know what you are doing if you make changes here.
 185  */
 186 /*-----------------------------------------------------------------------
 187  * Internal Memory Mapped Register
 188  */
 189 #define CFG_IMMR                0xFFF00000
 190
 191 /*-----------------------------------------------------------------------
 192  * Definitions for initial stack pointer and data area (in DPRAM)
 193  */
 194 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 195 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 196 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 197 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 198 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 199
 200 /*-----------------------------------------------------------------------
 201  * Start addresses for the final memory configuration
 202  * (Set up by the startup code)
 203  * Please note that CFG_SDRAM_BASE _must_ start at 0
 204  */
 205 #define CFG_SDRAM_BASE          0x00000000
 206 #define CFG_FLASH_BASE          0x40000000
 207 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 208 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 209 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 210
 211 /*
 212  * For booting Linux, the board info and command line data
 213  * have to be in the first 8 MB of memory, since this is
 214  * the maximum mapped by the Linux kernel during initialization.
 215  */
 216 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 217
 218 /*-----------------------------------------------------------------------
 219  * FLASH organization
 220  */
 221 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 222 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 223
 224 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 225 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 226
 227 #define CFG_ENV_IS_IN_FLASH     1
 228 #define CFG_ENV_OFFSET          0x40000 /*   Offset   of Environment Sector     */
 229 #define CFG_ENV_SIZE            0x08000 /* Total Size of Environment Sector     */
 230 #define CFG_ENV_SECT_SIZE       0x20000 /* Total Size of Environment Sector     */
 231
 232 /* Address and size of Redundant Environment Sector     */
 233 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
 234 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 235
 236 /*-----------------------------------------------------------------------
 237  * Hardware Information Block
 238  */
 239 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 240 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 241 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 242
 243 /*-----------------------------------------------------------------------
 244  * Cache Configuration
 245  */
 246 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 247 #if defined(CONFIG_CMD_KGDB)
 248 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 249 #endif
 250
 251 /*-----------------------------------------------------------------------
 252  * SYPCR - System Protection Control                            11-9
 253  * SYPCR can only be written once after reset!
 254  *-----------------------------------------------------------------------
 255  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 256  */
 257 #if defined(CONFIG_WATCHDOG)
 258 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 259                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 260 #else
 261 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 262 #endif
 263
 264 /*-----------------------------------------------------------------------
 265  * SIUMCR - SIU Module Configuration                            11-6
 266  *-----------------------------------------------------------------------
 267  * PCMCIA config., multi-function pin tri-state
 268  */
 269 #ifndef CONFIG_CAN_DRIVER
 270 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 271 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 272 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 273 #endif  /* CONFIG_CAN_DRIVER */
 274
 275 /*-----------------------------------------------------------------------
 276  * TBSCR - Time Base Status and Control                         11-26
 277  *-----------------------------------------------------------------------
 278  * Clear Reference Interrupt Status, Timebase freezing enabled
 279  */
 280 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 281
 282 /*-----------------------------------------------------------------------
 283  * PISCR - Periodic Interrupt Status and Control                11-31
 284  *-----------------------------------------------------------------------
 285  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 286  */
 287 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 288
 289 /*-----------------------------------------------------------------------
 290  * SCCR - System Clock and reset Control Register               15-27
 291  *-----------------------------------------------------------------------
 292  * Set clock output, timebase and RTC source and divider,
 293  * power management and some other internal clocks
 294  */
 295 #define SCCR_MASK       SCCR_EBDF11
 296 #define CFG_SCCR        (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 297                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 298                          SCCR_DFALCD00)
 299
 300 /*-----------------------------------------------------------------------
 301  * PCMCIA stuff
 302  *-----------------------------------------------------------------------
 303  *
 304  */
 305 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 306 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 307 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 308 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 309 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 310 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 311 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 312 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 313
 314 /*-----------------------------------------------------------------------
 315  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 316  *-----------------------------------------------------------------------
 317  */
 318
 319 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 320
 321 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 322 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 323 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 324
 325 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 326 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 327
 328 #define CFG_ATA_IDE0_OFFSET     0x0000
 329
 330 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 331
 332 /* Offset for data I/O                  */
 333 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 334
 335 /* Offset for normal register accesses  */
 336 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 337
 338 /* Offset for alternate registers       */
 339 #define CFG_ATA_ALT_OFFSET      0x0100
 340
 341 /*-----------------------------------------------------------------------
 342  *
 343  *-----------------------------------------------------------------------
 344  *
 345  */
 346 #define CFG_DER 0
 347
 348 /*
 349  * Init Memory Controller:
 350  *
 351  * BR0/1 and OR0/1 (FLASH)
 352  */
 353
 354 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 355 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 356
 357 /* used to re-map FLASH both when starting from SRAM or FLASH:
 358  * restrict access enough to keep SRAM working (if any)
 359  * but not too much to meddle with FLASH accesses
 360  */
 361 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 362 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 363
 364 /*
 365  * FLASH timing: Default value of OR0 after reset
 366  */
 367 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
 368                                  OR_SCY_15_CLK | OR_TRLX)
 369
 370 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 371 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 372 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 373
 374 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 375 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 376 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 377
 378 /*
 379  * BR2/3 and OR2/3 (SDRAM)
 380  *
 381  */
 382 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 383 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 384 #define SDRAM_MAX_SIZE          (256 << 20)     /* max 256 MB per bank  */
 385
 386 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 387 #define CFG_OR_TIMING_SDRAM     0x00000A00
 388
 389 #define CFG_OR2_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 390 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 391
 392 #ifndef CONFIG_CAN_DRIVER
 393 #define CFG_OR3_PRELIM  CFG_OR2_PRELIM
 394 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 395 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 396 #define CFG_CAN_BASE            0xC0000000      /* CAN mapped at 0xC0000000     */
 397 #define CFG_CAN_OR_AM           0xFFFF8000      /* 32 kB address mask           */
 398 #define CFG_OR3_CAN             (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
 399 #define CFG_BR3_CAN             ((CFG_CAN_BASE & BR_BA_MSK) | \
 400                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 401 #endif  /* CONFIG_CAN_DRIVER */
 402
 403 /*
 404  * 4096 Rows from SDRAM example configuration
 405  * 1000 factor s -> ms
 406  * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 407  * 4    Number of refresh cycles per period
 408  * 64   Refresh cycle in ms per number of rows
 409  */
 410 #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
 411
 412 /*
 413  * Memory Periodic Timer Prescaler
 414  * Periodic timer for refresh, start with refresh rate for 40 MHz clock
 415  * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
 416  */
 417 #define CFG_MAMR_PTA            39
 418
 419 /*
 420  * For 16 MBit, refresh rates could be 31.3 us
 421  * (= 64 ms / 2K = 125 / quad bursts).
 422  * For a simpler initialization, 15.6 us is used instead.
 423  *
 424  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 425  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 426  */
 427 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 428 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 429
 430 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 431 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 432 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 433
 434 /*
 435  * MAMR settings for SDRAM
 436  */
 437
 438 /* 8 column SDRAM */
 439 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 440                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 441                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 442 /* 9 column SDRAM */
 443 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 444                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 445                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 446 /* 10 column SDRAM */
 447 #define CFG_MAMR_10COL  ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 448                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |   \
 449                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 450
 451 /*
 452  * Internal Definitions
 453  *
 454  * Boot Flags
 455  */
 456 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 457 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 458
 459 #define CONFIG_SCC1_ENET
 460 #define CONFIG_FEC_ENET
 461 #define CONFIG_ETHPRIME         "SCC ETHERNET"
 462
 463 #endif  /* __CONFIG_H */