include/configs/TQM885D.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*
  35  * High Level Configuration Options
  36  * (easy to change)
  37  */
  38
  39 #define CONFIG_MPC885           1       /* This is a MPC885 CPU         */
  40 #define CONFIG_TQM885D          1       /* ...on a TQM88D module        */
  41
  42 #define CONFIG_8xx_OSCLK                10000000        /*  10 MHz - PLL input clock    */
  43 #define CFG_8xx_CPUCLK_MIN              15000000        /*  15 MHz - CPU minimum clock  */
  44 #define CFG_8xx_CPUCLK_MAX              133000000       /* 133 MHz - CPU maximum clock  */
  45 #define CONFIG_8xx_CPUCLK_DEFAULT       66000000        /*  50 MHz - CPU default clock  */
  46                                                 /* (it will be used if there is no      */
  47                                                 /* 'cpuclk' variable with valid value)  */
  48
  49 #define CFG_MEASURE_CPUCLK                      /* Measure real cpu clock       */
  50                                                 /* (function measure_gclk()     */
  51                                                 /* will be called)              */
  52 #ifdef CFG_MEASURE_CPUCLK
  53 #define CFG_8XX_XIN             10000000        /* measure_gclk() needs this    */
  54 #endif
  55
  56 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  57
  58 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  59
  60 #define CONFIG_BOOTCOUNT_LIMIT
  61
  62 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  63
  64 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  65
  66 #define CONFIG_PREBOOT  "echo;" \
  67         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
  68         "echo"
  69
  70 #undef  CONFIG_BOOTARGS
  71
  72 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  73         "netdev=eth0\0"                                                 \
  74         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  75                 "nfsroot=${serverip}:${rootpath}\0"                     \
  76         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  77         "addip=setenv bootargs ${bootargs} "                            \
  78                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  79                 ":${hostname}:${netdev}:off panic=1\0"                  \
  80         "flash_nfs=run nfsargs addip;"                                  \
  81                 "bootm ${kernel_addr}\0"                                \
  82         "flash_self=run ramargs addip;"                                 \
  83                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  84         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  85         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  86         "bootfile=/tftpboot/TQM866M/uImage\0"                           \
  87         "kernel_addr=40080000\0"                                        \
  88         "ramdisk_addr=40180000\0"                                       \
  89         ""
  90 #define CONFIG_BOOTCOMMAND      "run flash_self"
  91
  92 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  93 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  94
  95 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  96
  97 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  98
  99 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
 100
 101 /* enable I2C and select the hardware/software driver */
 102 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 103 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 104
 105 #define CFG_I2C_SPEED           93000   /* 93 kHz is supposed to work   */
 106 #define CFG_I2C_SLAVE           0xFE
 107
 108 #ifdef CONFIG_SOFT_I2C
 109 /*
 110  * Software (bit-bang) I2C driver configuration
 111  */
 112 #define PB_SCL          0x00000020      /* PB 26 */
 113 #define PB_SDA          0x00000010      /* PB 27 */
 114
 115 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 116 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 117 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 118 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 119 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 120                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 121 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 122                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 123 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 124 #endif  /* CONFIG_SOFT_I2C */
 125
 126 #define CFG_I2C_EEPROM_ADDR     0x50            /* EEPROM AT24C??       */
 127 #define CFG_I2C_EEPROM_ADDR_LEN 2               /* two byte address     */
 128 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 129 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 130
 131 # define CONFIG_RTC_DS1337 1
 132 # define CFG_I2C_RTC_ADDR 0x68
 133
 134 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
 135
 136 #define CONFIG_MAC_PARTITION
 137 #define CONFIG_DOS_PARTITION
 138
 139 #undef CONFIG_RTC_MPC8xx                /* MPC866 does not support RTC  */
 140
 141 #define CONFIG_TIMESTAMP                /* but print image timestmps    */
 142
 143 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
 144                                 CFG_CMD_ASKENV  | \
 145                                 CFG_CMD_DATE    | \
 146                                 CFG_CMD_DHCP    | \
 147                                 CFG_CMD_EEPROM  | \
 148                                 CFG_CMD_I2C     | \
 149                                 CFG_CMD_IDE     | \
 150                                 CFG_CMD_MII     | \
 151                                 CFG_CMD_NFS     | \
 152                                 CFG_CMD_PING )
 153
 154 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 155 #include <cmd_confdefs.h>
 156
 157 /*
 158  * Miscellaneous configurable options
 159  */
 160 #define CFG_LONGHELP                    /* undef to save memory         */
 161 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 162
 163 #if 0
 164 #define CFG_HUSH_PARSER         1       /* use "hush" command parser    */
 165 #endif
 166 #ifdef  CFG_HUSH_PARSER
 167 #define CFG_PROMPT_HUSH_PS2     "> "
 168 #endif
 169
 170 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 171 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 172 #else
 173 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 174 #endif
 175 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 176 #define CFG_MAXARGS             16      /* max number of command args   */
 177 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 178
 179 #define CFG_MEMTEST_START       0x0100000       /* memtest works on     */
 180 #define CFG_MEMTEST_END         0x0300000       /* 1 ... 3 MB in DRAM   */
 181 #define CFG_ALT_MEMTEST                         /* alternate, more extensive
 182                                                    memory test.*/
 183
 184 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 185
 186 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 187
 188 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 189
 190 /*
 191  * Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined,
 192  * which is normally part of the default commands (CFV_CMD_DFL)
 193  */
 194 #define CONFIG_LOOPW
 195
 196 /*
 197  * Low Level Configuration Settings
 198  * (address mappings, register initial values, etc.)
 199  * You should know what you are doing if you make changes here.
 200  */
 201 /*-----------------------------------------------------------------------
 202  * Internal Memory Mapped Register
 203  */
 204 #define CFG_IMMR                0xFFF00000
 205
 206 /*-----------------------------------------------------------------------
 207  * Definitions for initial stack pointer and data area (in DPRAM)
 208  */
 209 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 210 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 211 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 212 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 213 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 214
 215 /*-----------------------------------------------------------------------
 216  * Start addresses for the final memory configuration
 217  * (Set up by the startup code)
 218  * Please note that CFG_SDRAM_BASE _must_ start at 0
 219  */
 220 #define CFG_SDRAM_BASE          0x00000000
 221 #define CFG_FLASH_BASE          0x40000000
 222 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 223 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 224 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 225
 226 /*
 227  * For booting Linux, the board info and command line data
 228  * have to be in the first 8 MB of memory, since this is
 229  * the maximum mapped by the Linux kernel during initialization.
 230  */
 231 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 232
 233 /*-----------------------------------------------------------------------
 234  * FLASH organization
 235  */
 236 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 237 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 238
 239 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 240 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 241
 242 #define CFG_ENV_IS_IN_FLASH     1
 243 #define CFG_ENV_OFFSET          0x40000 /*   Offset   of Environment Sector     */
 244 #define CFG_ENV_SIZE            0x08000 /* Total Size of Environment Sector     */
 245 #define CFG_ENV_SECT_SIZE       0x20000 /* Total Size of Environment Sector     */
 246
 247 /* Address and size of Redundant Environment Sector     */
 248 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
 249 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 250
 251 /*-----------------------------------------------------------------------
 252  * Hardware Information Block
 253  */
 254 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 255 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 256 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 257
 258 /*-----------------------------------------------------------------------
 259  * Cache Configuration
 260  */
 261 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 262 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 263 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 264 #endif
 265
 266 /*-----------------------------------------------------------------------
 267  * SYPCR - System Protection Control                            11-9
 268  * SYPCR can only be written once after reset!
 269  *-----------------------------------------------------------------------
 270  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 271  */
 272 #if defined(CONFIG_WATCHDOG)
 273 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 274                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 275 #else
 276 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 277 #endif
 278
 279 /*-----------------------------------------------------------------------
 280  * SIUMCR - SIU Module Configuration                            11-6
 281  *-----------------------------------------------------------------------
 282  * PCMCIA config., multi-function pin tri-state
 283  */
 284 #ifndef CONFIG_CAN_DRIVER
 285 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 286 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 287 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 288 #endif  /* CONFIG_CAN_DRIVER */
 289
 290 /*-----------------------------------------------------------------------
 291  * TBSCR - Time Base Status and Control                         11-26
 292  *-----------------------------------------------------------------------
 293  * Clear Reference Interrupt Status, Timebase freezing enabled
 294  */
 295 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 296
 297 /*-----------------------------------------------------------------------
 298  * PISCR - Periodic Interrupt Status and Control                11-31
 299  *-----------------------------------------------------------------------
 300  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 301  */
 302 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 303
 304 /*-----------------------------------------------------------------------
 305  * SCCR - System Clock and reset Control Register               15-27
 306  *-----------------------------------------------------------------------
 307  * Set clock output, timebase and RTC source and divider,
 308  * power management and some other internal clocks
 309  */
 310 #define SCCR_MASK       SCCR_EBDF11
 311 #define CFG_SCCR        (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 312                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 313                          SCCR_DFALCD00)
 314
 315 /*-----------------------------------------------------------------------
 316  * PCMCIA stuff
 317  *-----------------------------------------------------------------------
 318  *
 319  */
 320 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 321 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 322 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 323 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 324 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 325 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 326 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 327 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 328
 329 /*-----------------------------------------------------------------------
 330  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 331  *-----------------------------------------------------------------------
 332  */
 333
 334 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 335
 336 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 337 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 338 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 339
 340 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 341 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 342
 343 #define CFG_ATA_IDE0_OFFSET     0x0000
 344
 345 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 346
 347 /* Offset for data I/O                  */
 348 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 349
 350 /* Offset for normal register accesses  */
 351 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 352
 353 /* Offset for alternate registers       */
 354 #define CFG_ATA_ALT_OFFSET      0x0100
 355
 356 /*-----------------------------------------------------------------------
 357  *
 358  *-----------------------------------------------------------------------
 359  *
 360  */
 361 #define CFG_DER 0
 362
 363 /*
 364  * Init Memory Controller:
 365  *
 366  * BR0/1 and OR0/1 (FLASH)
 367  */
 368
 369 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 370 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 371
 372 /* used to re-map FLASH both when starting from SRAM or FLASH:
 373  * restrict access enough to keep SRAM working (if any)
 374  * but not too much to meddle with FLASH accesses
 375  */
 376 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 377 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 378
 379 /*
 380  * FLASH timing: Default value of OR0 after reset
 381  */
 382 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
 383                                  OR_SCY_6_CLK | OR_TRLX)
 384
 385 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 386 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 387 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 388
 389 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 390 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 391 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 392
 393 /*
 394  * BR2/3 and OR2/3 (SDRAM)
 395  *
 396  */
 397 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 398 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 399 #define SDRAM_MAX_SIZE          (256 << 20)     /* max 256 MB per bank  */
 400
 401 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 402 #define CFG_OR_TIMING_SDRAM     0x00000A00
 403
 404 #define CFG_OR2_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 405 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 406
 407 #ifndef CONFIG_CAN_DRIVER
 408 #define CFG_OR3_PRELIM  CFG_OR2_PRELIM
 409 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 410 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 411 #define CFG_CAN_BASE            0xC0000000      /* CAN mapped at 0xC0000000     */
 412 #define CFG_CAN_OR_AM           0xFFFF8000      /* 32 kB address mask           */
 413 #define CFG_OR3_CAN             (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
 414 #define CFG_BR3_CAN             ((CFG_CAN_BASE & BR_BA_MSK) | \
 415                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 416 #endif  /* CONFIG_CAN_DRIVER */
 417
 418 /*
 419  * 4096 Rows from SDRAM example configuration
 420  * 1000 factor s -> ms
 421  * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 422  * 4    Number of refresh cycles per period
 423  * 64   Refresh cycle in ms per number of rows
 424  */
 425 #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
 426
 427 /*
 428  * Memory Periodic Timer Prescaler
 429  * Periodic timer for refresh, start with refresh rate for 40 MHz clock
 430  * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
 431  */
 432 #define CFG_MAMR_PTA            39
 433
 434 /*
 435  * For 16 MBit, refresh rates could be 31.3 us
 436  * (= 64 ms / 2K = 125 / quad bursts).
 437  * For a simpler initialization, 15.6 us is used instead.
 438  *
 439  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 440  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 441  */
 442 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 443 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 444
 445 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 446 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 447 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 448
 449 /*
 450  * MAMR settings for SDRAM
 451  */
 452
 453 /* 8 column SDRAM */
 454 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 455                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 456                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 457 /* 9 column SDRAM */
 458 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 459                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 460                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 461 /* 10 column SDRAM */
 462 #define CFG_MAMR_10COL  ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 463                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |   \
 464                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 465
 466 /*
 467  * Internal Definitions
 468  *
 469  * Boot Flags
 470  */
 471 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 472 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 473
 474 /*
 475  * Network configuration
 476  */
 477 #define CONFIG_SCC2_ENET                /* enable ethernet on SCC2 */
 478 #define CONFIG_FEC_ENET                 /* enable ethernet on FEC */
 479 #define CONFIG_ETHER_ON_FEC1            /* ... for FEC1 */
 480 #define CONFIG_ETHER_ON_FEC2            /* ... for FEC2 */
 481
 482 #if (CONFIG_COMMANDS & CFG_CMD_MII)
 483 #define CFG_DISCOVER_PHY
 484 #endif
 485
 486 #define CONFIG_NET_RETRY_COUNT 1        /* reduce max. timeout before
 487                                            switching to another netwok (if the
 488                                            tried network is unreachable) */
 489
 490 #define CONFIG_ETHPRIME         "SCC ETHERNET"
 491
 492 #endif  /* __CONFIG_H */