include/configs/Total5200.h

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * Check valid setting of revision define.
  32  * Total5100 and Total5200 Rev.1 are identical except for the processor.
  33  */
  34 #if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
  35 #error CONFIG_TOTAL5200_REV must be 1 or 2
  36 #endif
  37
  38 /*
  39  * High Level Configuration Options
  40  * (easy to change)
  41  */
  42
  43 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  44 #define CONFIG_MPC5200          1       /* (more precisely a MPC5200 CPU) */
  45 #define CONFIG_TOTAL5200        1       /* ... on Total5200 board */
  46
  47 /*
  48  * Valid values for CONFIG_SYS_TEXT_BASE are:
  49  * 0xFFF00000   boot high (standard configuration)
  50  * 0xFE000000   boot low
  51  * 0x00100000   boot from RAM (for testing only)
  52  */
  53 #ifndef CONFIG_SYS_TEXT_BASE
  54 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  55 #endif
  56
  57 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz */
  58
  59 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  60
  61 /*
  62  * Serial console configuration
  63  */
  64 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 */
  65 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  66 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  67
  68 /*
  69  * Video console
  70  */
  71 #define CONFIG_VIDEO
  72 #define CONFIG_VIDEO_SED13806
  73 #define CONFIG_VIDEO_SED13806_16BPP
  74
  75 #define CONFIG_CFB_CONSOLE
  76 #define CONFIG_VIDEO_LOGO
  77 /* #define CONFIG_VIDEO_BMP_LOGO */
  78 #define CONFIG_CONSOLE_EXTRA_INFO
  79 #define CONFIG_VGA_AS_SINGLE_DEVICE
  80 #define CONFIG_VIDEO_SW_CURSOR
  81 #define CONFIG_SPLASH_SCREEN
  82
  83
  84 /*
  85  * PCI Mapping:
  86  * 0x40000000 - 0x4fffffff - PCI Memory
  87  * 0x50000000 - 0x50ffffff - PCI IO Space
  88  */
  89 #define CONFIG_PCI              1
  90 #define CONFIG_PCI_PNP          1
  91 #define CONFIG_PCI_SCAN_SHOW    1
  92 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  93
  94 #define CONFIG_PCI_MEM_BUS      0x40000000
  95 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  96 #define CONFIG_PCI_MEM_SIZE     0x10000000
  97
  98 #define CONFIG_PCI_IO_BUS       0x50000000
  99 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
 100 #define CONFIG_PCI_IO_SIZE      0x01000000
 101
 102 #define CONFIG_NET_MULTI        1
 103 #define CONFIG_MII              1
 104 #define CONFIG_EEPRO100         1
 105 #define CONFIG_SYS_RX_ETH_BUFFER        8  /* use 8 rx buffer on eepro100  */
 106 #define CONFIG_NS8382X          1
 107
 108 /* Partitions */
 109 #define CONFIG_MAC_PARTITION
 110 #define CONFIG_DOS_PARTITION
 111
 112 /* USB */
 113 #define CONFIG_USB_OHCI
 114 #define CONFIG_USB_STORAGE
 115
 116
 117 /*
 118  * BOOTP options
 119  */
 120 #define CONFIG_BOOTP_BOOTFILESIZE
 121 #define CONFIG_BOOTP_BOOTPATH
 122 #define CONFIG_BOOTP_GATEWAY
 123 #define CONFIG_BOOTP_HOSTNAME
 124
 125
 126 /*
 127  * Command line configuration.
 128  */
 129 #include <config_cmd_default.h>
 130
 131 #define CONFIG_CMD_PCI
 132
 133 #define CONFIG_CMD_BMP
 134 #define CONFIG_CMD_EEPROM
 135 #define CONFIG_CMD_FAT
 136 #define CONFIG_CMD_I2C
 137 #define CONFIG_CMD_IDE
 138 #define CONFIG_CMD_PING
 139 #define CONFIG_CMD_USB
 140
 141
 142 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)                /* Boot low */
 143 #   define CONFIG_SYS_LOWBOOT           1
 144 #endif
 145
 146 /*
 147  * Autobooting
 148  */
 149 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 150
 151 #define CONFIG_PREBOOT  \
 152         "setenv stdout serial;setenv stderr serial;" \
 153         "echo;" \
 154         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 155         "echo"
 156
 157 #undef  CONFIG_BOOTARGS
 158
 159 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 160         "netdev=eth0\0"                                                 \
 161         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 162                 "nfsroot=${serverip}:${rootpath}\0"                     \
 163         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 164         "addip=setenv bootargs ${bootargs} "                            \
 165                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 166                 ":${hostname}:${netdev}:off panic=1\0"                  \
 167         "flash_nfs=run nfsargs addip;"                                  \
 168                 "bootm ${kernel_addr}\0"                                \
 169         "flash_self=run ramargs addip;"                                 \
 170                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 171         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 172         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
 173         "bootfile=/tftpboot/MPC5200/uImage\0"                           \
 174         ""
 175
 176 #define CONFIG_BOOTCOMMAND      "run flash_self"
 177
 178 /*
 179  * IPB Bus clocking configuration.
 180  */
 181 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK          /* define for 133MHz speed */
 182
 183 /*
 184  * I2C configuration
 185  */
 186 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 187 #define CONFIG_SYS_I2C_MODULE           1       /* Select I2C module #1 or #2 */
 188
 189 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 190 #define CONFIG_SYS_I2C_SLAVE            0x7F
 191
 192 /*
 193  * EEPROM configuration
 194  */
 195 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 196 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 197 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 198 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
 199
 200 /*
 201  * Flash configuration
 202  */
 203 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 204 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 205 #if CONFIG_TOTAL5200_REV==2
 206 #   define CONFIG_SYS_MAX_FLASH_BANKS   3       /* max num of flash banks */
 207 #   define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START }
 208 #else
 209 #   define CONFIG_SYS_MAX_FLASH_BANKS   1       /* max num of flash banks  */
 210 #   define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
 211 #endif
 212 #define CONFIG_SYS_FLASH_EMPTY_INFO
 213 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 214
 215 #if CONFIG_TOTAL5200_REV==1
 216 #   define CONFIG_SYS_FLASH_BASE        0xFE000000
 217 #   define CONFIG_SYS_FLASH_SIZE        0x02000000
 218 #elif CONFIG_TOTAL5200_REV==2
 219 #   define CONFIG_SYS_FLASH_BASE        0xFA000000
 220 #   define CONFIG_SYS_FLASH_SIZE        0x06000000
 221 #endif /* CONFIG_TOTAL5200_REV */
 222
 223 #if defined(CONFIG_SYS_LOWBOOT)
 224 #   define CONFIG_ENV_ADDR              0xFE040000
 225 #else   /* CONFIG_SYS_LOWBOOT */
 226 #   define CONFIG_ENV_ADDR              0xFFF40000
 227 #endif  /* CONFIG_SYS_LOWBOOT */
 228
 229 /*
 230  * Environment settings
 231  */
 232 #define CONFIG_ENV_IS_IN_FLASH  1
 233 #define CONFIG_ENV_SIZE         0x40000
 234 #define CONFIG_ENV_SECT_SIZE    0x40000
 235 #define CONFIG_ENV_OVERWRITE    1
 236
 237 /*
 238  * Memory map
 239  */
 240 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 241 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 242 #define CONFIG_SYS_MBAR         0xF0000000      /*   64 kB */
 243 #define CONFIG_SYS_FPGA_BASE            0xF0010000      /*   64 kB */
 244 #define CONFIG_SYS_CPLD_BASE            0xF0020000      /*   64 kB */
 245 #define CONFIG_SYS_LCD_BASE             0xF1000000      /* 4096 kB */
 246
 247 /* Use SRAM until RAM will be available */
 248 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 249 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
 250
 251 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 252 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 253
 254 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 255 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 256 #   define CONFIG_SYS_RAMBOOT           1
 257 #endif
 258
 259 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 260 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 261 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 262
 263 /*
 264  * Ethernet configuration
 265  */
 266 #define CONFIG_MPC5xxx_FEC      1
 267 #define CONFIG_MPC5xxx_FEC_SEVENWIRE
 268 /* dummy, 7-wire FEC does not have phy address */
 269 #define CONFIG_PHY_ADDR         0x00
 270
 271 /*
 272  * GPIO configuration
 273  *
 274  * CS1:   SDRAM CS1 disabled, gpio_wkup_6 enabled                0
 275  * Reserved                                                      0
 276  * ALTs:  CAN1/2 on PSC2, SPI on PSC3                            00
 277  * CS7:   Interrupt GPIO on PSC3_5                               0
 278  * CS8:   Interrupt GPIO on PSC3_4                               0
 279  * ATA:   reset default, changed in ATA driver                   00
 280  * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO       0
 281  * IRDA:  reset default, changed in IrDA driver                  000
 282  * ETHER: reset default, changed in Ethernet driver              0000
 283  * PCI_DIS: reset default, changed in PCI driver                 0
 284  * USB_SE: reset default, changed in USB driver                  0
 285  * USB:   reset default, changed in USB driver                   00
 286  * PSC3:  SPI and UART functionality without CD                  1100
 287  * Reserved                                                      0
 288  * PSC2:  CAN1/2                                                 001
 289  * Reserved                                                      0
 290  * PSC1:  reset default, changed in AC'97 driver                 000
 291  *
 292  */
 293 #define CONFIG_SYS_GPS_PORT_CONFIG      0x00000C10
 294
 295 /*
 296  * Miscellaneous configurable options
 297  */
 298 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 299 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 300 #if defined(CONFIG_CMD_KGDB)
 301 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 302 #else
 303 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 304 #endif
 305 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 306 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 307 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 308
 309 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 310 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 311
 312 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 313
 314 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 315
 316 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 317 #if defined(CONFIG_CMD_KGDB)
 318 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 319 #endif
 320
 321
 322 /*
 323  * Various low-level settings
 324  */
 325 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 326 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 327
 328 #if CONFIG_TOTAL5200_REV==1
 329 #   define CONFIG_SYS_BOOTCS_START      CONFIG_SYS_FLASH_BASE
 330 #   define CONFIG_SYS_BOOTCS_SIZE       0x02000000      /* 32 MB */
 331 #   define CONFIG_SYS_BOOTCS_CFG        0x0004DF00      /* 4WS, MX, AL, CE, AS_25, DS_32 */
 332 #   define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
 333 #   define CONFIG_SYS_CS0_SIZE          0x02000000      /* 32 MB */
 334 #else
 335 #   define CONFIG_SYS_BOOTCS_START      (CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE)
 336 #   define CONFIG_SYS_BOOTCS_SIZE       0x02000000      /* 32 MB */
 337 #   define CONFIG_SYS_BOOTCS_CFG        0x0004DF00      /* 4WS, MX, AL, CE, AS_25, DS_32 */
 338 #   define CONFIG_SYS_CS4_START (CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE)
 339 #   define CONFIG_SYS_CS4_SIZE          0x02000000      /* 32 MB */
 340 #   define CONFIG_SYS_CS4_CFG           0x0004DF00      /* 4WS, MX, AL, CE, AS_25, DS_32 */
 341 #   define CONFIG_SYS_CS5_START CONFIG_SYS_FLASH_BASE
 342 #   define CONFIG_SYS_CS5_SIZE          0x02000000      /* 32 MB */
 343 #   define CONFIG_SYS_CS5_CFG           0x0004DF00      /* 4WS, MX, AL, CE, AS_25, DS_32 */
 344 #endif
 345
 346 #define CONFIG_SYS_CS1_START            CONFIG_SYS_FPGA_BASE
 347 #define CONFIG_SYS_CS1_SIZE             0x00010000      /* 64 kB */
 348 #define CONFIG_SYS_CS1_CFG              0x0019FF00      /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
 349
 350 #define CONFIG_SYS_CS2_START            CONFIG_SYS_LCD_BASE
 351 #define CONFIG_SYS_CS2_SIZE             0x00400000      /* 4096 kB */
 352 #define CONFIG_SYS_CS2_CFG              0x0032FD0C      /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
 353
 354 #if CONFIG_TOTAL5200_REV==1
 355 #   define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
 356 #   define CONFIG_SYS_CS3_SIZE          0x00010000      /* 64 kB */
 357 #   define CONFIG_SYS_CS3_CFG           0x000ADF00      /* 10WS, MX, AL, CE, AS_25, DS_32 */
 358 #else
 359 #   define CONFIG_SYS_CS3_START CONFIG_SYS_CPLD_BASE
 360 #   define CONFIG_SYS_CS3_SIZE          0x00010000      /* 64 kB */
 361 #   define CONFIG_SYS_CS3_CFG           0x000AD800      /* 10WS, MX, AL, CE, AS_24, DS_8 */
 362 #endif
 363
 364 #define CONFIG_SYS_CS_BURST             0x00000000
 365 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 366
 367 /*-----------------------------------------------------------------------
 368  * USB stuff
 369  *-----------------------------------------------------------------------
 370  */
 371 #define CONFIG_USB_CLOCK        0x0001BBBB
 372 #define CONFIG_USB_CONFIG       0x00001000
 373
 374 /*-----------------------------------------------------------------------
 375  * IDE/ATA stuff Supports IDE harddisk
 376  *-----------------------------------------------------------------------
 377  */
 378
 379 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 380
 381 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 382 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 383
 384 #define CONFIG_IDE_RESET                /* reset for ide supported      */
 385 #define CONFIG_IDE_PREINIT
 386
 387 #define CONFIG_SYS_ATA_CS_ON_I2C2
 388 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 389 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 390
 391 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 392
 393 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 394
 395 /* Offset for data I/O                  */
 396 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 397
 398 /* Offset for normal register accesses  */
 399 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 400
 401 /* Offset for alternate registers       */
 402 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 403
 404 /* Interval between registers                                                */
 405 #define CONFIG_SYS_ATA_STRIDE          4
 406
 407 #endif /* __CONFIG_H */