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[people/ms/u-boot.git] / include / configs / UCP1020.h
1 /*
2 * Copyright 2013-2015 Arcturus Networks, Inc.
3 * http://www.arcturusnetworks.com/products/ucp1020/
4 * based on include/configs/p1_p2_rdb_pc.h
5 * original copyright follows:
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 /*
12 * QorIQ uCP1020-xx boards configuration file
13 */
14 #ifndef __CONFIG_H
15 #define __CONFIG_H
16
17 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
18 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
19 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
20 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
21 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
22 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
23
24 #if defined(CONFIG_TARTGET_UCP1020T1)
25
26 #define CONFIG_UCP1020_REV_1_3
27
28 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
29
30 #define CONFIG_TSEC_ENET
31 #define CONFIG_TSEC1
32 #define CONFIG_TSEC3
33 #define CONFIG_HAS_ETH0
34 #define CONFIG_HAS_ETH1
35 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
36 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
37 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
38 #define CONFIG_IPADDR 10.80.41.229
39 #define CONFIG_SERVERIP 10.80.41.227
40 #define CONFIG_NETMASK 255.255.252.0
41 #define CONFIG_ETHPRIME "eTSEC3"
42
43 #ifndef CONFIG_SPI_FLASH
44 #endif
45 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
46
47 #define CONFIG_SYS_L2_SIZE (256 << 10)
48
49 #define CONFIG_LAST_STAGE_INIT
50
51 #endif
52
53 #if defined(CONFIG_TARGET_UCP1020)
54
55 #define CONFIG_UCP1020
56 #define CONFIG_UCP1020_REV_1_3
57
58 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
59
60 #define CONFIG_TSEC_ENET
61 #define CONFIG_TSEC1
62 #define CONFIG_TSEC2
63 #define CONFIG_TSEC3
64 #define CONFIG_HAS_ETH0
65 #define CONFIG_HAS_ETH1
66 #define CONFIG_HAS_ETH2
67 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
68 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
69 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
70 #define CONFIG_IPADDR 192.168.1.81
71 #define CONFIG_IPADDR1 192.168.1.82
72 #define CONFIG_IPADDR2 192.168.1.83
73 #define CONFIG_SERVERIP 192.168.1.80
74 #define CONFIG_GATEWAYIP 102.168.1.1
75 #define CONFIG_NETMASK 255.255.255.0
76 #define CONFIG_ETHPRIME "eTSEC1"
77
78 #ifndef CONFIG_SPI_FLASH
79 #endif
80 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
81
82 #define CONFIG_SYS_L2_SIZE (256 << 10)
83
84 #define CONFIG_LAST_STAGE_INIT
85
86 #endif
87
88 #ifdef CONFIG_SDCARD
89 #define CONFIG_RAMBOOT_SDCARD
90 #define CONFIG_SYS_RAMBOOT
91 #define CONFIG_SYS_EXTRA_ENV_RELOC
92 #define CONFIG_SYS_TEXT_BASE 0x11000000
93 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
94 #endif
95
96 #ifdef CONFIG_SPIFLASH
97 #define CONFIG_RAMBOOT_SPIFLASH
98 #define CONFIG_SYS_RAMBOOT
99 #define CONFIG_SYS_EXTRA_ENV_RELOC
100 #define CONFIG_SYS_TEXT_BASE 0x11000000
101 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
102 #endif
103
104 #ifndef CONFIG_SYS_TEXT_BASE
105 #define CONFIG_SYS_TEXT_BASE 0xeff80000
106 #endif
107 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
108
109 #ifndef CONFIG_RESET_VECTOR_ADDRESS
110 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
111 #endif
112
113 #ifndef CONFIG_SYS_MONITOR_BASE
114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
115 #endif
116
117 #define CONFIG_MP
118
119 #define CONFIG_ENV_OVERWRITE
120
121 #define CONFIG_SYS_SATA_MAX_DEVICE 2
122 #define CONFIG_LBA48
123
124 #define CONFIG_SYS_CLK_FREQ 66666666
125 #define CONFIG_DDR_CLK_FREQ 66666666
126
127 #define CONFIG_HWCONFIG
128
129 /*
130 * These can be toggled for performance analysis, otherwise use default.
131 */
132 #define CONFIG_L2_CACHE
133 #define CONFIG_BTB
134
135 #define CONFIG_ENABLE_36BIT_PHYS
136
137 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
138 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
139 #define CONFIG_PANIC_HANG /* do not reset board on panic */
140
141 #define CONFIG_SYS_CCSRBAR 0xffe00000
142 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
143
144 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
145 SPL code*/
146 #ifdef CONFIG_SPL_BUILD
147 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
148 #endif
149
150 /* DDR Setup */
151 #define CONFIG_DDR_ECC_ENABLE
152 #ifndef CONFIG_DDR_ECC_ENABLE
153 #define CONFIG_SYS_DDR_RAW_TIMING
154 #define CONFIG_DDR_SPD
155 #endif
156 #define CONFIG_SYS_SPD_BUS_NUM 1
157 #undef CONFIG_FSL_DDR_INTERACTIVE
158
159 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
160 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
161 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
162 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
163 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
164
165 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
166
167 /* Default settings for DDR3 */
168 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
169 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
170 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
171 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
172 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
173 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
174
175 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
176 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
177 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
178 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
179
180 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
181 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
182 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
183 #define CONFIG_SYS_DDR_RCW_1 0x00000000
184 #define CONFIG_SYS_DDR_RCW_2 0x00000000
185 #ifdef CONFIG_DDR_ECC_ENABLE
186 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
187 #else
188 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
189 #endif
190 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
191 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
192 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
193
194 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
195 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
196 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
197 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
198 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
199 #define CONFIG_SYS_DDR_MODE_1 0x40461520
200 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
201 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
202
203 #undef CONFIG_CLOCKS_IN_MHZ
204
205 /*
206 * Memory map
207 *
208 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
209 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
210 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
211 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
212 * (early boot only)
213 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
214 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
215 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
216 */
217
218 /*
219 * Local Bus Definitions
220 */
221 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
222 #define CONFIG_SYS_FLASH_BASE 0xec000000
223
224 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
225
226 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
227 | BR_PS_16 | BR_V)
228
229 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
230
231 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
232 #define CONFIG_SYS_FLASH_QUIET_TEST
233 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
234
235 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
236
237 #undef CONFIG_SYS_FLASH_CHECKSUM
238 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
239 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
240
241 #define CONFIG_FLASH_CFI_DRIVER
242 #define CONFIG_SYS_FLASH_CFI
243 #define CONFIG_SYS_FLASH_EMPTY_INFO
244 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
245
246 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
247
248 #define CONFIG_SYS_INIT_RAM_LOCK
249 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
250 /* Initial L1 address */
251 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
252 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
253 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
254 /* Size of used area in RAM */
255 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
256
257 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
258 GENERATED_GBL_DATA_SIZE)
259 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
260
261 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
262 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
263
264 #define CONFIG_SYS_PMC_BASE 0xff980000
265 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
266 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
267 BR_PS_8 | BR_V)
268 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
269 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
270 OR_GPCM_EAD)
271
272 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
273 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
274 #ifdef CONFIG_NAND_FSL_ELBC
275 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
276 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
277 #endif
278
279 /* Serial Port - controlled on board with jumper J8
280 * open - index 2
281 * shorted - index 1
282 */
283 #define CONFIG_CONS_INDEX 1
284 #undef CONFIG_SERIAL_SOFTWARE_FIFO
285 #define CONFIG_SYS_NS16550_SERIAL
286 #define CONFIG_SYS_NS16550_REG_SIZE 1
287 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
288 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
289 #define CONFIG_NS16550_MIN_FUNCTIONS
290 #endif
291
292 #define CONFIG_SYS_BAUDRATE_TABLE \
293 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
294
295 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
296 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
297
298 /* I2C */
299 #define CONFIG_SYS_I2C
300 #define CONFIG_SYS_I2C_FSL
301 #define CONFIG_SYS_FSL_I2C_SPEED 400000
302 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
303 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
304 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
305 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
306 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
307 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
308 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
309
310 #define CONFIG_RTC_DS1337
311 #define CONFIG_RTC_DS1337_NOOSC
312 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
313 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
314 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
315 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
316
317 /*
318 * eSPI - Enhanced SPI
319 */
320 #define CONFIG_HARD_SPI
321
322 #define CONFIG_SF_DEFAULT_SPEED 10000000
323 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
324
325 #if defined(CONFIG_PCI)
326 /*
327 * General PCI
328 * Memory space is mapped 1-1, but I/O space must start from 0.
329 */
330
331 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
332 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
333 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
334 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
335 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
336 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
337 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
338 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
339 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
340 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
341
342 /* controller 1, Slot 2, tgtid 1, Base address a000 */
343 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
344 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
345 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
346 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
347 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
348 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
349 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
350 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
351 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
352
353 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
354 #endif /* CONFIG_PCI */
355
356 /*
357 * Environment
358 */
359 #ifdef CONFIG_ENV_FIT_UCBOOT
360
361 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
362 #define CONFIG_ENV_SIZE 0x20000
363 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
364
365 #else
366
367 #define CONFIG_ENV_SPI_BUS 0
368 #define CONFIG_ENV_SPI_CS 0
369 #define CONFIG_ENV_SPI_MAX_HZ 10000000
370 #define CONFIG_ENV_SPI_MODE 0
371
372 #ifdef CONFIG_RAMBOOT_SPIFLASH
373
374 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */
375 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
376 #define CONFIG_ENV_SECT_SIZE 0x1000
377
378 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
379 /* Address and size of Redundant Environment Sector */
380 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
381 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
382 #endif
383
384 #elif defined(CONFIG_RAMBOOT_SDCARD)
385 #define CONFIG_FSL_FIXED_MMC_LOCATION
386 #define CONFIG_ENV_SIZE 0x2000
387 #define CONFIG_SYS_MMC_ENV_DEV 0
388
389 #elif defined(CONFIG_SYS_RAMBOOT)
390 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
391 #define CONFIG_ENV_SIZE 0x2000
392
393 #else
394 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
395 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
396 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
397 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
398 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
399 /* Address and size of Redundant Environment Sector */
400 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
401 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
402 #endif
403
404 #endif
405
406 #endif /* CONFIG_ENV_FIT_UCBOOT */
407
408 #define CONFIG_LOADS_ECHO /* echo on for serial download */
409 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
410
411 /*
412 * USB
413 */
414 #define CONFIG_HAS_FSL_DR_USB
415
416 #if defined(CONFIG_HAS_FSL_DR_USB)
417 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
418
419 #ifdef CONFIG_USB_EHCI_HCD
420 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
421 #define CONFIG_USB_EHCI_FSL
422 #endif
423 #endif
424
425 #undef CONFIG_WATCHDOG /* watchdog disabled */
426
427 #ifdef CONFIG_MMC
428 #define CONFIG_FSL_ESDHC
429 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
430 #define CONFIG_MMC_SPI
431 #endif
432
433 /* Misc Extra Settings */
434 #undef CONFIG_WATCHDOG /* watchdog disabled */
435
436 /*
437 * Miscellaneous configurable options
438 */
439 #define CONFIG_SYS_LONGHELP /* undef to save memory */
440 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
441 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
442 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
443
444 /*
445 * For booting Linux, the board info and command line data
446 * have to be in the first 64 MB of memory, since this is
447 * the maximum mapped by the Linux kernel during initialization.
448 */
449 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
450 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
451
452 #if defined(CONFIG_CMD_KGDB)
453 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
454 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
455 #endif
456
457 /*
458 * Environment Configuration
459 */
460
461 #if defined(CONFIG_TSEC_ENET)
462
463 #if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
464 #else
465 #error "UCP1020 module revision is not defined !!!"
466 #endif
467
468 #define CONFIG_BOOTP_SERVERIP
469
470 #define CONFIG_MII /* MII PHY management */
471 #define CONFIG_TSEC1_NAME "eTSEC1"
472 #define CONFIG_TSEC2_NAME "eTSEC2"
473 #define CONFIG_TSEC3_NAME "eTSEC3"
474
475 #define TSEC1_PHY_ADDR 4
476 #define TSEC2_PHY_ADDR 0
477 #define TSEC2_PHY_ADDR_SGMII 0x00
478 #define TSEC3_PHY_ADDR 6
479
480 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
481 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
482 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
483
484 #define TSEC1_PHYIDX 0
485 #define TSEC2_PHYIDX 0
486 #define TSEC3_PHYIDX 0
487
488 #endif
489
490 #define CONFIG_HOSTNAME UCP1020
491 #define CONFIG_ROOTPATH "/opt/nfsroot"
492 #define CONFIG_BOOTFILE "uImage"
493 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
494
495 /* default location for tftp and bootm */
496 #define CONFIG_LOADADDR 1000000
497
498 #if defined(CONFIG_DONGLE)
499
500 #define CONFIG_EXTRA_ENV_SETTINGS \
501 "bootcmd=run prog_spi_mbrbootcramfs\0" \
502 "bootfile=uImage\0" \
503 "consoledev=ttyS0\0" \
504 "cramfsfile=image.cramfs\0" \
505 "dtbaddr=0x00c00000\0" \
506 "dtbfile=image.dtb\0" \
507 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
508 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
509 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
510 "fileaddr=0x01000000\0" \
511 "filesize=0x00080000\0" \
512 "flashmbr=sf probe 0; " \
513 "tftp $loadaddr $mbr; " \
514 "sf erase $mbr_offset +$filesize; " \
515 "sf write $loadaddr $mbr_offset $filesize\0" \
516 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
517 "protect off $nor_recoveryaddr +$filesize; " \
518 "erase $nor_recoveryaddr +$filesize; " \
519 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
520 "protect on $nor_recoveryaddr +$filesize\0 " \
521 "flashuboot=tftp $ubootaddr $ubootfile; " \
522 "protect off $nor_ubootaddr +$filesize; " \
523 "erase $nor_ubootaddr +$filesize; " \
524 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
525 "protect on $nor_ubootaddr +$filesize\0 " \
526 "flashworking=tftp $workingaddr $cramfsfile; " \
527 "protect off $nor_workingaddr +$filesize; " \
528 "erase $nor_workingaddr +$filesize; " \
529 "cp.b $workingaddr $nor_workingaddr $filesize; " \
530 "protect on $nor_workingaddr +$filesize\0 " \
531 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
532 "kerneladdr=0x01100000\0" \
533 "kernelfile=uImage\0" \
534 "loadaddr=0x01000000\0" \
535 "mbr=uCP1020d.mbr\0" \
536 "mbr_offset=0x00000000\0" \
537 "mmbr=uCP1020Quiet.mbr\0" \
538 "mmcpart=0:2\0" \
539 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
540 "mmc erase 1 1; " \
541 "mmc write $loadaddr 1 1\0" \
542 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
543 "mmc erase 0x40 0x400; " \
544 "mmc write $loadaddr 0x40 0x400\0" \
545 "netdev=eth0\0" \
546 "nor_recoveryaddr=0xEC0A0000\0" \
547 "nor_ubootaddr=0xEFF80000\0" \
548 "nor_workingaddr=0xECFA0000\0" \
549 "norbootrecovery=setenv bootargs $recoverybootargs" \
550 " console=$consoledev,$baudrate $othbootargs; " \
551 "run norloadrecovery; " \
552 "bootm $kerneladdr - $dtbaddr\0" \
553 "norbootworking=setenv bootargs $workingbootargs" \
554 " console=$consoledev,$baudrate $othbootargs; " \
555 "run norloadworking; " \
556 "bootm $kerneladdr - $dtbaddr\0" \
557 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
558 "setenv cramfsaddr $nor_recoveryaddr; " \
559 "cramfsload $dtbaddr $dtbfile; " \
560 "cramfsload $kerneladdr $kernelfile\0" \
561 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
562 "setenv cramfsaddr $nor_workingaddr; " \
563 "cramfsload $dtbaddr $dtbfile; " \
564 "cramfsload $kerneladdr $kernelfile\0" \
565 "prog_spi_mbr=run spi__mbr\0" \
566 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
567 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
568 "run spi__cramfs\0" \
569 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
570 " console=$consoledev,$baudrate $othbootargs; " \
571 "tftp $rootfsaddr $rootfsfile; " \
572 "tftp $loadaddr $kernelfile; " \
573 "tftp $dtbaddr $dtbfile; " \
574 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
575 "ramdisk_size=120000\0" \
576 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
577 "recoveryaddr=0x02F00000\0" \
578 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
579 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
580 "mw.l 0xffe0f008 0x00400000\0" \
581 "rootfsaddr=0x02F00000\0" \
582 "rootfsfile=rootfs.ext2.gz.uboot\0" \
583 "rootpath=/opt/nfsroot\0" \
584 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
585 "protect off 0xeC000000 +$filesize; " \
586 "erase 0xEC000000 +$filesize; " \
587 "cp.b $loadaddr 0xEC000000 $filesize; " \
588 "cmp.b $loadaddr 0xEC000000 $filesize; " \
589 "protect on 0xeC000000 +$filesize\0" \
590 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
591 "protect off 0xeFF80000 +$filesize; " \
592 "erase 0xEFF80000 +$filesize; " \
593 "cp.b $loadaddr 0xEFF80000 $filesize; " \
594 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
595 "protect on 0xeFF80000 +$filesize\0" \
596 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
597 "sf probe 0; sf erase 0x8000 +$filesize; " \
598 "sf write $loadaddr 0x8000 $filesize\0" \
599 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
600 "protect off 0xec0a0000 +$filesize; " \
601 "erase 0xeC0A0000 +$filesize; " \
602 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
603 "protect on 0xec0a0000 +$filesize\0" \
604 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
605 "sf probe 1; sf erase 0 +$filesize; " \
606 "sf write $loadaddr 0 $filesize\0" \
607 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
608 "sf probe 0; sf erase 0 +$filesize; " \
609 "sf write $loadaddr 0 $filesize\0" \
610 "tftpflash=tftpboot $loadaddr $uboot; " \
611 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
612 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
613 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
614 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
615 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
616 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
617 "ubootaddr=0x01000000\0" \
618 "ubootfile=u-boot.bin\0" \
619 "ubootd=u-boot4dongle.bin\0" \
620 "upgrade=run flashworking\0" \
621 "usb_phy_type=ulpi\0 " \
622 "workingaddr=0x02F00000\0" \
623 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
624
625 #else
626
627 #if defined(CONFIG_UCP1020T1)
628
629 #define CONFIG_EXTRA_ENV_SETTINGS \
630 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
631 "bootfile=uImage\0" \
632 "consoledev=ttyS0\0" \
633 "cramfsfile=image.cramfs\0" \
634 "dtbaddr=0x00c00000\0" \
635 "dtbfile=image.dtb\0" \
636 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
637 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
638 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
639 "fileaddr=0x01000000\0" \
640 "filesize=0x00080000\0" \
641 "flashmbr=sf probe 0; " \
642 "tftp $loadaddr $mbr; " \
643 "sf erase $mbr_offset +$filesize; " \
644 "sf write $loadaddr $mbr_offset $filesize\0" \
645 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
646 "protect off $nor_recoveryaddr +$filesize; " \
647 "erase $nor_recoveryaddr +$filesize; " \
648 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
649 "protect on $nor_recoveryaddr +$filesize\0 " \
650 "flashuboot=tftp $ubootaddr $ubootfile; " \
651 "protect off $nor_ubootaddr +$filesize; " \
652 "erase $nor_ubootaddr +$filesize; " \
653 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
654 "protect on $nor_ubootaddr +$filesize\0 " \
655 "flashworking=tftp $workingaddr $cramfsfile; " \
656 "protect off $nor_workingaddr +$filesize; " \
657 "erase $nor_workingaddr +$filesize; " \
658 "cp.b $workingaddr $nor_workingaddr $filesize; " \
659 "protect on $nor_workingaddr +$filesize\0 " \
660 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
661 "kerneladdr=0x01100000\0" \
662 "kernelfile=uImage\0" \
663 "loadaddr=0x01000000\0" \
664 "mbr=uCP1020.mbr\0" \
665 "mbr_offset=0x00000000\0" \
666 "netdev=eth0\0" \
667 "nor_recoveryaddr=0xEC0A0000\0" \
668 "nor_ubootaddr=0xEFF80000\0" \
669 "nor_workingaddr=0xECFA0000\0" \
670 "norbootrecovery=setenv bootargs $recoverybootargs" \
671 " console=$consoledev,$baudrate $othbootargs; " \
672 "run norloadrecovery; " \
673 "bootm $kerneladdr - $dtbaddr\0" \
674 "norbootworking=setenv bootargs $workingbootargs" \
675 " console=$consoledev,$baudrate $othbootargs; " \
676 "run norloadworking; " \
677 "bootm $kerneladdr - $dtbaddr\0" \
678 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
679 "setenv cramfsaddr $nor_recoveryaddr; " \
680 "cramfsload $dtbaddr $dtbfile; " \
681 "cramfsload $kerneladdr $kernelfile\0" \
682 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
683 "setenv cramfsaddr $nor_workingaddr; " \
684 "cramfsload $dtbaddr $dtbfile; " \
685 "cramfsload $kerneladdr $kernelfile\0" \
686 "othbootargs=quiet\0" \
687 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
688 " console=$consoledev,$baudrate $othbootargs; " \
689 "tftp $rootfsaddr $rootfsfile; " \
690 "tftp $loadaddr $kernelfile; " \
691 "tftp $dtbaddr $dtbfile; " \
692 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
693 "ramdisk_size=120000\0" \
694 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
695 "recoveryaddr=0x02F00000\0" \
696 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
697 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
698 "mw.l 0xffe0f008 0x00400000\0" \
699 "rootfsaddr=0x02F00000\0" \
700 "rootfsfile=rootfs.ext2.gz.uboot\0" \
701 "rootpath=/opt/nfsroot\0" \
702 "silent=1\0" \
703 "tftpflash=tftpboot $loadaddr $uboot; " \
704 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
705 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
706 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
707 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
708 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
709 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
710 "ubootaddr=0x01000000\0" \
711 "ubootfile=u-boot.bin\0" \
712 "upgrade=run flashworking\0" \
713 "workingaddr=0x02F00000\0" \
714 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
715
716 #else /* For Arcturus Modules */
717
718 #define CONFIG_EXTRA_ENV_SETTINGS \
719 "bootcmd=run norkernel\0" \
720 "bootfile=uImage\0" \
721 "consoledev=ttyS0\0" \
722 "dtbaddr=0x00c00000\0" \
723 "dtbfile=image.dtb\0" \
724 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
725 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
726 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
727 "fileaddr=0x01000000\0" \
728 "filesize=0x00080000\0" \
729 "flashmbr=sf probe 0; " \
730 "tftp $loadaddr $mbr; " \
731 "sf erase $mbr_offset +$filesize; " \
732 "sf write $loadaddr $mbr_offset $filesize\0" \
733 "flashuboot=tftp $loadaddr $ubootfile; " \
734 "protect off $nor_ubootaddr0 +$filesize; " \
735 "erase $nor_ubootaddr0 +$filesize; " \
736 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
737 "protect on $nor_ubootaddr0 +$filesize; " \
738 "protect off $nor_ubootaddr1 +$filesize; " \
739 "erase $nor_ubootaddr1 +$filesize; " \
740 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
741 "protect on $nor_ubootaddr1 +$filesize\0 " \
742 "format0=protect off $part0base +$part0size; " \
743 "erase $part0base +$part0size\0" \
744 "format1=protect off $part1base +$part1size; " \
745 "erase $part1base +$part1size\0" \
746 "format2=protect off $part2base +$part2size; " \
747 "erase $part2base +$part2size\0" \
748 "format3=protect off $part3base +$part3size; " \
749 "erase $part3base +$part3size\0" \
750 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
751 "kerneladdr=0x01100000\0" \
752 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
753 "kernelfile=uImage\0" \
754 "loadaddr=0x01000000\0" \
755 "mbr=uCP1020.mbr\0" \
756 "mbr_offset=0x00000000\0" \
757 "netdev=eth0\0" \
758 "nor_ubootaddr0=0xEC000000\0" \
759 "nor_ubootaddr1=0xEFF80000\0" \
760 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
761 "run norkernelload; " \
762 "bootm $kerneladdr - $dtbaddr\0" \
763 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
764 "setenv cramfsaddr $part0base; " \
765 "cramfsload $dtbaddr $dtbfile; " \
766 "cramfsload $kerneladdr $kernelfile\0" \
767 "part0base=0xEC100000\0" \
768 "part0size=0x00700000\0" \
769 "part1base=0xEC800000\0" \
770 "part1size=0x02000000\0" \
771 "part2base=0xEE800000\0" \
772 "part2size=0x00800000\0" \
773 "part3base=0xEF000000\0" \
774 "part3size=0x00F80000\0" \
775 "partENVbase=0xEC080000\0" \
776 "partENVsize=0x00080000\0" \
777 "program0=tftp part0-000000.bin; " \
778 "protect off $part0base +$filesize; " \
779 "erase $part0base +$filesize; " \
780 "cp.b $loadaddr $part0base $filesize; " \
781 "echo Verifying...; " \
782 "cmp.b $loadaddr $part0base $filesize\0" \
783 "program1=tftp part1-000000.bin; " \
784 "protect off $part1base +$filesize; " \
785 "erase $part1base +$filesize; " \
786 "cp.b $loadaddr $part1base $filesize; " \
787 "echo Verifying...; " \
788 "cmp.b $loadaddr $part1base $filesize\0" \
789 "program2=tftp part2-000000.bin; " \
790 "protect off $part2base +$filesize; " \
791 "erase $part2base +$filesize; " \
792 "cp.b $loadaddr $part2base $filesize; " \
793 "echo Verifying...; " \
794 "cmp.b $loadaddr $part2base $filesize\0" \
795 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
796 " console=$consoledev,$baudrate $othbootargs; " \
797 "tftp $rootfsaddr $rootfsfile; " \
798 "tftp $loadaddr $kernelfile; " \
799 "tftp $dtbaddr $dtbfile; " \
800 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
801 "ramdisk_size=120000\0" \
802 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
803 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
804 "mw.l 0xffe0f008 0x00400000\0" \
805 "rootfsaddr=0x02F00000\0" \
806 "rootfsfile=rootfs.ext2.gz.uboot\0" \
807 "rootpath=/opt/nfsroot\0" \
808 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
809 "sf probe 0; sf erase 0 +$filesize; " \
810 "sf write $loadaddr 0 $filesize\0" \
811 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
812 "protect off 0xeC000000 +$filesize; " \
813 "erase 0xEC000000 +$filesize; " \
814 "cp.b $loadaddr 0xEC000000 $filesize; " \
815 "cmp.b $loadaddr 0xEC000000 $filesize; " \
816 "protect on 0xeC000000 +$filesize\0" \
817 "tftpflash=tftpboot $loadaddr $uboot; " \
818 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
819 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
820 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
821 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
822 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
823 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
824 "ubootfile=u-boot.bin\0" \
825 "upgrade=run flashuboot\0" \
826 "usb_phy_type=ulpi\0 " \
827 "boot_nfs= " \
828 "setenv bootargs root=/dev/nfs rw " \
829 "nfsroot=$serverip:$rootpath " \
830 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
831 "console=$consoledev,$baudrate $othbootargs;" \
832 "tftp $loadaddr $bootfile;" \
833 "tftp $fdtaddr $fdtfile;" \
834 "bootm $loadaddr - $fdtaddr\0" \
835 "boot_hd = " \
836 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
837 "console=$consoledev,$baudrate $othbootargs;" \
838 "usb start;" \
839 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
840 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
841 "bootm $loadaddr - $fdtaddr\0" \
842 "boot_usb_fat = " \
843 "setenv bootargs root=/dev/ram rw " \
844 "console=$consoledev,$baudrate $othbootargs " \
845 "ramdisk_size=$ramdisk_size;" \
846 "usb start;" \
847 "fatload usb 0:2 $loadaddr $bootfile;" \
848 "fatload usb 0:2 $fdtaddr $fdtfile;" \
849 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
850 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
851 "boot_usb_ext2 = " \
852 "setenv bootargs root=/dev/ram rw " \
853 "console=$consoledev,$baudrate $othbootargs " \
854 "ramdisk_size=$ramdisk_size;" \
855 "usb start;" \
856 "ext2load usb 0:4 $loadaddr $bootfile;" \
857 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
858 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
859 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
860 "boot_nor = " \
861 "setenv bootargs root=/dev/$jffs2nor rw " \
862 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
863 "bootm $norbootaddr - $norfdtaddr\0 " \
864 "boot_ram = " \
865 "setenv bootargs root=/dev/ram rw " \
866 "console=$consoledev,$baudrate $othbootargs " \
867 "ramdisk_size=$ramdisk_size;" \
868 "tftp $ramdiskaddr $ramdiskfile;" \
869 "tftp $loadaddr $bootfile;" \
870 "tftp $fdtaddr $fdtfile;" \
871 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
872
873 #endif
874 #endif
875
876 #endif /* __CONFIG_H */
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