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[thirdparty/u-boot.git] / include / configs / UCP1020.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright 2013-2015 Arcturus Networks, Inc.
4 * http://www.arcturusnetworks.com/products/ucp1020/
5 * based on include/configs/p1_p2_rdb_pc.h
6 * original copyright follows:
7 * Copyright 2009-2011 Freescale Semiconductor, Inc.
8 */
9
10 /*
11 * QorIQ uCP1020-xx boards configuration file
12 */
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15
16 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
17 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
18 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
19 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
20 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
21 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
22
23 #if defined(CONFIG_TARTGET_UCP1020T1)
24
25 #define CONFIG_UCP1020_REV_1_3
26
27 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
28
29 #define CONFIG_TSEC1
30 #define CONFIG_TSEC3
31 #define CONFIG_HAS_ETH0
32 #define CONFIG_HAS_ETH1
33 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
34 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
35 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
36 #define CONFIG_IPADDR 10.80.41.229
37 #define CONFIG_SERVERIP 10.80.41.227
38 #define CONFIG_NETMASK 255.255.252.0
39 #define CONFIG_ETHPRIME "eTSEC3"
40
41 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
42
43 #define CONFIG_SYS_L2_SIZE (256 << 10)
44
45 #endif
46
47 #if defined(CONFIG_TARGET_UCP1020)
48
49 #define CONFIG_UCP1020
50 #define CONFIG_UCP1020_REV_1_3
51
52 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
53
54 #define CONFIG_TSEC1
55 #define CONFIG_TSEC2
56 #define CONFIG_TSEC3
57 #define CONFIG_HAS_ETH0
58 #define CONFIG_HAS_ETH1
59 #define CONFIG_HAS_ETH2
60 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
61 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
62 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
63 #define CONFIG_IPADDR 192.168.1.81
64 #define CONFIG_IPADDR1 192.168.1.82
65 #define CONFIG_IPADDR2 192.168.1.83
66 #define CONFIG_SERVERIP 192.168.1.80
67 #define CONFIG_GATEWAYIP 102.168.1.1
68 #define CONFIG_NETMASK 255.255.255.0
69 #define CONFIG_ETHPRIME "eTSEC1"
70
71 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
72
73 #define CONFIG_SYS_L2_SIZE (256 << 10)
74
75 #endif
76
77 #ifdef CONFIG_SDCARD
78 #define CONFIG_RAMBOOT_SDCARD
79 #define CONFIG_SYS_RAMBOOT
80 #define CONFIG_SYS_EXTRA_ENV_RELOC
81 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
82 #endif
83
84 #ifdef CONFIG_SPIFLASH
85 #define CONFIG_RAMBOOT_SPIFLASH
86 #define CONFIG_SYS_RAMBOOT
87 #define CONFIG_SYS_EXTRA_ENV_RELOC
88 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
89 #endif
90
91 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
92
93 #ifndef CONFIG_RESET_VECTOR_ADDRESS
94 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
95 #endif
96
97 #ifndef CONFIG_SYS_MONITOR_BASE
98 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
99 #endif
100
101 #define CONFIG_ENV_OVERWRITE
102
103 #define CONFIG_SYS_SATA_MAX_DEVICE 2
104 #define CONFIG_LBA48
105
106 #define CONFIG_SYS_CLK_FREQ 66666666
107 #define CONFIG_DDR_CLK_FREQ 66666666
108
109 #define CONFIG_HWCONFIG
110
111 /*
112 * These can be toggled for performance analysis, otherwise use default.
113 */
114 #define CONFIG_L2_CACHE
115 #define CONFIG_BTB
116
117 #define CONFIG_ENABLE_36BIT_PHYS
118
119 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
120 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
121
122 #define CONFIG_SYS_CCSRBAR 0xffe00000
123 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
124
125 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
126 SPL code*/
127 #ifdef CONFIG_SPL_BUILD
128 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
129 #endif
130
131 /* DDR Setup */
132 #define CONFIG_DDR_ECC_ENABLE
133 #ifndef CONFIG_DDR_ECC_ENABLE
134 #define CONFIG_SYS_DDR_RAW_TIMING
135 #define CONFIG_DDR_SPD
136 #endif
137 #define CONFIG_SYS_SPD_BUS_NUM 1
138 #undef CONFIG_FSL_DDR_INTERACTIVE
139
140 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
141 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
142 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
143 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
144 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
145
146 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
147
148 /* Default settings for DDR3 */
149 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
150 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
151 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
152 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
153 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
154 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
155
156 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
157 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
158 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
159 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
160
161 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
162 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
163 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
164 #define CONFIG_SYS_DDR_RCW_1 0x00000000
165 #define CONFIG_SYS_DDR_RCW_2 0x00000000
166 #ifdef CONFIG_DDR_ECC_ENABLE
167 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
168 #else
169 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
170 #endif
171 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
172 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
173 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
174
175 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
176 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
177 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
178 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
179 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
180 #define CONFIG_SYS_DDR_MODE_1 0x40461520
181 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
182 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
183
184 #undef CONFIG_CLOCKS_IN_MHZ
185
186 /*
187 * Memory map
188 *
189 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
190 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
191 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
192 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
193 * (early boot only)
194 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
195 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
196 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
197 */
198
199 /*
200 * Local Bus Definitions
201 */
202 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
203 #define CONFIG_SYS_FLASH_BASE 0xec000000
204
205 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
206
207 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
208 | BR_PS_16 | BR_V)
209
210 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
211
212 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
213 #define CONFIG_SYS_FLASH_QUIET_TEST
214 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
215
216 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
217
218 #undef CONFIG_SYS_FLASH_CHECKSUM
219 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
220 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
221
222 #define CONFIG_FLASH_CFI_DRIVER
223 #define CONFIG_SYS_FLASH_CFI
224 #define CONFIG_SYS_FLASH_EMPTY_INFO
225 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
226
227 #define CONFIG_SYS_INIT_RAM_LOCK
228 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
229 /* Initial L1 address */
230 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
231 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
232 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
233 /* Size of used area in RAM */
234 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
235
236 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
237 GENERATED_GBL_DATA_SIZE)
238 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
239
240 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
241 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
242
243 #define CONFIG_SYS_PMC_BASE 0xff980000
244 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
245 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
246 BR_PS_8 | BR_V)
247 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
248 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
249 OR_GPCM_EAD)
250
251 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
252 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
253 #ifdef CONFIG_NAND_FSL_ELBC
254 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
255 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
256 #endif
257
258 /* Serial Port - controlled on board with jumper J8
259 * open - index 2
260 * shorted - index 1
261 */
262 #undef CONFIG_SERIAL_SOFTWARE_FIFO
263 #define CONFIG_SYS_NS16550_SERIAL
264 #define CONFIG_SYS_NS16550_REG_SIZE 1
265 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
266 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
267 #define CONFIG_NS16550_MIN_FUNCTIONS
268 #endif
269
270 #define CONFIG_SYS_BAUDRATE_TABLE \
271 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
272
273 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
274 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
275
276 /* I2C */
277 #define CONFIG_SYS_I2C
278 #define CONFIG_SYS_I2C_FSL
279 #define CONFIG_SYS_FSL_I2C_SPEED 400000
280 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
281 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
282 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
283 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
284 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
285 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
286 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
287
288 #define CONFIG_RTC_DS1337
289 #define CONFIG_RTC_DS1337_NOOSC
290 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
291 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
292 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
293 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
294
295 /*
296 * eSPI - Enhanced SPI
297 */
298 #define CONFIG_HARD_SPI
299
300 #define CONFIG_SF_DEFAULT_SPEED 10000000
301 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
302
303 #if defined(CONFIG_PCI)
304 /*
305 * General PCI
306 * Memory space is mapped 1-1, but I/O space must start from 0.
307 */
308
309 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
310 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
311 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
312 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
313 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
314 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
315 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
316 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
317 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
318 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
319
320 /* controller 1, Slot 2, tgtid 1, Base address a000 */
321 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
322 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
323 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
324 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
325 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
326 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
327 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
328 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
329 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
330
331 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
332 #endif /* CONFIG_PCI */
333
334 /*
335 * Environment
336 */
337 #ifdef CONFIG_ENV_FIT_UCBOOT
338
339 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
340 #define CONFIG_ENV_SIZE 0x20000
341 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
342
343 #else
344
345 #define CONFIG_ENV_SPI_BUS 0
346 #define CONFIG_ENV_SPI_CS 0
347 #define CONFIG_ENV_SPI_MAX_HZ 10000000
348 #define CONFIG_ENV_SPI_MODE 0
349
350 #ifdef CONFIG_RAMBOOT_SPIFLASH
351
352 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */
353 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
354 #define CONFIG_ENV_SECT_SIZE 0x1000
355
356 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
357 /* Address and size of Redundant Environment Sector */
358 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
359 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
360 #endif
361
362 #elif defined(CONFIG_RAMBOOT_SDCARD)
363 #define CONFIG_FSL_FIXED_MMC_LOCATION
364 #define CONFIG_ENV_SIZE 0x2000
365 #define CONFIG_SYS_MMC_ENV_DEV 0
366
367 #elif defined(CONFIG_SYS_RAMBOOT)
368 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
369 #define CONFIG_ENV_SIZE 0x2000
370
371 #else
372 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
373 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
374 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
375 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
376 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
377 /* Address and size of Redundant Environment Sector */
378 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
379 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
380 #endif
381
382 #endif
383
384 #endif /* CONFIG_ENV_FIT_UCBOOT */
385
386 #define CONFIG_LOADS_ECHO /* echo on for serial download */
387 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
388
389 /*
390 * USB
391 */
392 #define CONFIG_HAS_FSL_DR_USB
393
394 #if defined(CONFIG_HAS_FSL_DR_USB)
395 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
396
397 #ifdef CONFIG_USB_EHCI_HCD
398 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
399 #define CONFIG_USB_EHCI_FSL
400 #endif
401 #endif
402
403 #undef CONFIG_WATCHDOG /* watchdog disabled */
404
405 #ifdef CONFIG_MMC
406 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
407 #define CONFIG_MMC_SPI
408 #endif
409
410 /* Misc Extra Settings */
411 #undef CONFIG_WATCHDOG /* watchdog disabled */
412
413 /*
414 * Miscellaneous configurable options
415 */
416 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
417 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
418
419 /*
420 * For booting Linux, the board info and command line data
421 * have to be in the first 64 MB of memory, since this is
422 * the maximum mapped by the Linux kernel during initialization.
423 */
424 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
425 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
426
427 #if defined(CONFIG_CMD_KGDB)
428 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
429 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
430 #endif
431
432 /*
433 * Environment Configuration
434 */
435
436 #if defined(CONFIG_TSEC_ENET)
437
438 #if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
439 #else
440 #error "UCP1020 module revision is not defined !!!"
441 #endif
442
443 #define CONFIG_BOOTP_SERVERIP
444
445 #define CONFIG_MII /* MII PHY management */
446 #define CONFIG_TSEC1_NAME "eTSEC1"
447 #define CONFIG_TSEC2_NAME "eTSEC2"
448 #define CONFIG_TSEC3_NAME "eTSEC3"
449
450 #define TSEC1_PHY_ADDR 4
451 #define TSEC2_PHY_ADDR 0
452 #define TSEC2_PHY_ADDR_SGMII 0x00
453 #define TSEC3_PHY_ADDR 6
454
455 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
456 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
457 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
458
459 #define TSEC1_PHYIDX 0
460 #define TSEC2_PHYIDX 0
461 #define TSEC3_PHYIDX 0
462
463 #endif
464
465 #define CONFIG_HOSTNAME "UCP1020"
466 #define CONFIG_ROOTPATH "/opt/nfsroot"
467 #define CONFIG_BOOTFILE "uImage"
468 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
469
470 /* default location for tftp and bootm */
471 #define CONFIG_LOADADDR 1000000
472
473 #if defined(CONFIG_DONGLE)
474
475 #define CONFIG_EXTRA_ENV_SETTINGS \
476 "bootcmd=run prog_spi_mbrbootcramfs\0" \
477 "bootfile=uImage\0" \
478 "consoledev=ttyS0\0" \
479 "cramfsfile=image.cramfs\0" \
480 "dtbaddr=0x00c00000\0" \
481 "dtbfile=image.dtb\0" \
482 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
483 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
484 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
485 "fileaddr=0x01000000\0" \
486 "filesize=0x00080000\0" \
487 "flashmbr=sf probe 0; " \
488 "tftp $loadaddr $mbr; " \
489 "sf erase $mbr_offset +$filesize; " \
490 "sf write $loadaddr $mbr_offset $filesize\0" \
491 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
492 "protect off $nor_recoveryaddr +$filesize; " \
493 "erase $nor_recoveryaddr +$filesize; " \
494 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
495 "protect on $nor_recoveryaddr +$filesize\0 " \
496 "flashuboot=tftp $ubootaddr $ubootfile; " \
497 "protect off $nor_ubootaddr +$filesize; " \
498 "erase $nor_ubootaddr +$filesize; " \
499 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
500 "protect on $nor_ubootaddr +$filesize\0 " \
501 "flashworking=tftp $workingaddr $cramfsfile; " \
502 "protect off $nor_workingaddr +$filesize; " \
503 "erase $nor_workingaddr +$filesize; " \
504 "cp.b $workingaddr $nor_workingaddr $filesize; " \
505 "protect on $nor_workingaddr +$filesize\0 " \
506 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
507 "kerneladdr=0x01100000\0" \
508 "kernelfile=uImage\0" \
509 "loadaddr=0x01000000\0" \
510 "mbr=uCP1020d.mbr\0" \
511 "mbr_offset=0x00000000\0" \
512 "mmbr=uCP1020Quiet.mbr\0" \
513 "mmcpart=0:2\0" \
514 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
515 "mmc erase 1 1; " \
516 "mmc write $loadaddr 1 1\0" \
517 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
518 "mmc erase 0x40 0x400; " \
519 "mmc write $loadaddr 0x40 0x400\0" \
520 "netdev=eth0\0" \
521 "nor_recoveryaddr=0xEC0A0000\0" \
522 "nor_ubootaddr=0xEFF80000\0" \
523 "nor_workingaddr=0xECFA0000\0" \
524 "norbootrecovery=setenv bootargs $recoverybootargs" \
525 " console=$consoledev,$baudrate $othbootargs; " \
526 "run norloadrecovery; " \
527 "bootm $kerneladdr - $dtbaddr\0" \
528 "norbootworking=setenv bootargs $workingbootargs" \
529 " console=$consoledev,$baudrate $othbootargs; " \
530 "run norloadworking; " \
531 "bootm $kerneladdr - $dtbaddr\0" \
532 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
533 "setenv cramfsaddr $nor_recoveryaddr; " \
534 "cramfsload $dtbaddr $dtbfile; " \
535 "cramfsload $kerneladdr $kernelfile\0" \
536 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
537 "setenv cramfsaddr $nor_workingaddr; " \
538 "cramfsload $dtbaddr $dtbfile; " \
539 "cramfsload $kerneladdr $kernelfile\0" \
540 "prog_spi_mbr=run spi__mbr\0" \
541 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
542 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
543 "run spi__cramfs\0" \
544 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
545 " console=$consoledev,$baudrate $othbootargs; " \
546 "tftp $rootfsaddr $rootfsfile; " \
547 "tftp $loadaddr $kernelfile; " \
548 "tftp $dtbaddr $dtbfile; " \
549 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
550 "ramdisk_size=120000\0" \
551 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
552 "recoveryaddr=0x02F00000\0" \
553 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
554 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
555 "mw.l 0xffe0f008 0x00400000\0" \
556 "rootfsaddr=0x02F00000\0" \
557 "rootfsfile=rootfs.ext2.gz.uboot\0" \
558 "rootpath=/opt/nfsroot\0" \
559 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
560 "protect off 0xeC000000 +$filesize; " \
561 "erase 0xEC000000 +$filesize; " \
562 "cp.b $loadaddr 0xEC000000 $filesize; " \
563 "cmp.b $loadaddr 0xEC000000 $filesize; " \
564 "protect on 0xeC000000 +$filesize\0" \
565 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
566 "protect off 0xeFF80000 +$filesize; " \
567 "erase 0xEFF80000 +$filesize; " \
568 "cp.b $loadaddr 0xEFF80000 $filesize; " \
569 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
570 "protect on 0xeFF80000 +$filesize\0" \
571 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
572 "sf probe 0; sf erase 0x8000 +$filesize; " \
573 "sf write $loadaddr 0x8000 $filesize\0" \
574 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
575 "protect off 0xec0a0000 +$filesize; " \
576 "erase 0xeC0A0000 +$filesize; " \
577 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
578 "protect on 0xec0a0000 +$filesize\0" \
579 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
580 "sf probe 1; sf erase 0 +$filesize; " \
581 "sf write $loadaddr 0 $filesize\0" \
582 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
583 "sf probe 0; sf erase 0 +$filesize; " \
584 "sf write $loadaddr 0 $filesize\0" \
585 "tftpflash=tftpboot $loadaddr $uboot; " \
586 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
587 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
588 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
589 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
590 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
591 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
592 "ubootaddr=0x01000000\0" \
593 "ubootfile=u-boot.bin\0" \
594 "ubootd=u-boot4dongle.bin\0" \
595 "upgrade=run flashworking\0" \
596 "usb_phy_type=ulpi\0 " \
597 "workingaddr=0x02F00000\0" \
598 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
599
600 #else
601
602 #if defined(CONFIG_UCP1020T1)
603
604 #define CONFIG_EXTRA_ENV_SETTINGS \
605 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
606 "bootfile=uImage\0" \
607 "consoledev=ttyS0\0" \
608 "cramfsfile=image.cramfs\0" \
609 "dtbaddr=0x00c00000\0" \
610 "dtbfile=image.dtb\0" \
611 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
612 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
613 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
614 "fileaddr=0x01000000\0" \
615 "filesize=0x00080000\0" \
616 "flashmbr=sf probe 0; " \
617 "tftp $loadaddr $mbr; " \
618 "sf erase $mbr_offset +$filesize; " \
619 "sf write $loadaddr $mbr_offset $filesize\0" \
620 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
621 "protect off $nor_recoveryaddr +$filesize; " \
622 "erase $nor_recoveryaddr +$filesize; " \
623 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
624 "protect on $nor_recoveryaddr +$filesize\0 " \
625 "flashuboot=tftp $ubootaddr $ubootfile; " \
626 "protect off $nor_ubootaddr +$filesize; " \
627 "erase $nor_ubootaddr +$filesize; " \
628 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
629 "protect on $nor_ubootaddr +$filesize\0 " \
630 "flashworking=tftp $workingaddr $cramfsfile; " \
631 "protect off $nor_workingaddr +$filesize; " \
632 "erase $nor_workingaddr +$filesize; " \
633 "cp.b $workingaddr $nor_workingaddr $filesize; " \
634 "protect on $nor_workingaddr +$filesize\0 " \
635 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
636 "kerneladdr=0x01100000\0" \
637 "kernelfile=uImage\0" \
638 "loadaddr=0x01000000\0" \
639 "mbr=uCP1020.mbr\0" \
640 "mbr_offset=0x00000000\0" \
641 "netdev=eth0\0" \
642 "nor_recoveryaddr=0xEC0A0000\0" \
643 "nor_ubootaddr=0xEFF80000\0" \
644 "nor_workingaddr=0xECFA0000\0" \
645 "norbootrecovery=setenv bootargs $recoverybootargs" \
646 " console=$consoledev,$baudrate $othbootargs; " \
647 "run norloadrecovery; " \
648 "bootm $kerneladdr - $dtbaddr\0" \
649 "norbootworking=setenv bootargs $workingbootargs" \
650 " console=$consoledev,$baudrate $othbootargs; " \
651 "run norloadworking; " \
652 "bootm $kerneladdr - $dtbaddr\0" \
653 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
654 "setenv cramfsaddr $nor_recoveryaddr; " \
655 "cramfsload $dtbaddr $dtbfile; " \
656 "cramfsload $kerneladdr $kernelfile\0" \
657 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
658 "setenv cramfsaddr $nor_workingaddr; " \
659 "cramfsload $dtbaddr $dtbfile; " \
660 "cramfsload $kerneladdr $kernelfile\0" \
661 "othbootargs=quiet\0" \
662 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
663 " console=$consoledev,$baudrate $othbootargs; " \
664 "tftp $rootfsaddr $rootfsfile; " \
665 "tftp $loadaddr $kernelfile; " \
666 "tftp $dtbaddr $dtbfile; " \
667 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
668 "ramdisk_size=120000\0" \
669 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
670 "recoveryaddr=0x02F00000\0" \
671 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
672 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
673 "mw.l 0xffe0f008 0x00400000\0" \
674 "rootfsaddr=0x02F00000\0" \
675 "rootfsfile=rootfs.ext2.gz.uboot\0" \
676 "rootpath=/opt/nfsroot\0" \
677 "silent=1\0" \
678 "tftpflash=tftpboot $loadaddr $uboot; " \
679 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
680 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
681 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
682 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
683 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
684 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
685 "ubootaddr=0x01000000\0" \
686 "ubootfile=u-boot.bin\0" \
687 "upgrade=run flashworking\0" \
688 "workingaddr=0x02F00000\0" \
689 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
690
691 #else /* For Arcturus Modules */
692
693 #define CONFIG_EXTRA_ENV_SETTINGS \
694 "bootcmd=run norkernel\0" \
695 "bootfile=uImage\0" \
696 "consoledev=ttyS0\0" \
697 "dtbaddr=0x00c00000\0" \
698 "dtbfile=image.dtb\0" \
699 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
700 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
701 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
702 "fileaddr=0x01000000\0" \
703 "filesize=0x00080000\0" \
704 "flashmbr=sf probe 0; " \
705 "tftp $loadaddr $mbr; " \
706 "sf erase $mbr_offset +$filesize; " \
707 "sf write $loadaddr $mbr_offset $filesize\0" \
708 "flashuboot=tftp $loadaddr $ubootfile; " \
709 "protect off $nor_ubootaddr0 +$filesize; " \
710 "erase $nor_ubootaddr0 +$filesize; " \
711 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
712 "protect on $nor_ubootaddr0 +$filesize; " \
713 "protect off $nor_ubootaddr1 +$filesize; " \
714 "erase $nor_ubootaddr1 +$filesize; " \
715 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
716 "protect on $nor_ubootaddr1 +$filesize\0 " \
717 "format0=protect off $part0base +$part0size; " \
718 "erase $part0base +$part0size\0" \
719 "format1=protect off $part1base +$part1size; " \
720 "erase $part1base +$part1size\0" \
721 "format2=protect off $part2base +$part2size; " \
722 "erase $part2base +$part2size\0" \
723 "format3=protect off $part3base +$part3size; " \
724 "erase $part3base +$part3size\0" \
725 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
726 "kerneladdr=0x01100000\0" \
727 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
728 "kernelfile=uImage\0" \
729 "loadaddr=0x01000000\0" \
730 "mbr=uCP1020.mbr\0" \
731 "mbr_offset=0x00000000\0" \
732 "netdev=eth0\0" \
733 "nor_ubootaddr0=0xEC000000\0" \
734 "nor_ubootaddr1=0xEFF80000\0" \
735 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
736 "run norkernelload; " \
737 "bootm $kerneladdr - $dtbaddr\0" \
738 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
739 "setenv cramfsaddr $part0base; " \
740 "cramfsload $dtbaddr $dtbfile; " \
741 "cramfsload $kerneladdr $kernelfile\0" \
742 "part0base=0xEC100000\0" \
743 "part0size=0x00700000\0" \
744 "part1base=0xEC800000\0" \
745 "part1size=0x02000000\0" \
746 "part2base=0xEE800000\0" \
747 "part2size=0x00800000\0" \
748 "part3base=0xEF000000\0" \
749 "part3size=0x00F80000\0" \
750 "partENVbase=0xEC080000\0" \
751 "partENVsize=0x00080000\0" \
752 "program0=tftp part0-000000.bin; " \
753 "protect off $part0base +$filesize; " \
754 "erase $part0base +$filesize; " \
755 "cp.b $loadaddr $part0base $filesize; " \
756 "echo Verifying...; " \
757 "cmp.b $loadaddr $part0base $filesize\0" \
758 "program1=tftp part1-000000.bin; " \
759 "protect off $part1base +$filesize; " \
760 "erase $part1base +$filesize; " \
761 "cp.b $loadaddr $part1base $filesize; " \
762 "echo Verifying...; " \
763 "cmp.b $loadaddr $part1base $filesize\0" \
764 "program2=tftp part2-000000.bin; " \
765 "protect off $part2base +$filesize; " \
766 "erase $part2base +$filesize; " \
767 "cp.b $loadaddr $part2base $filesize; " \
768 "echo Verifying...; " \
769 "cmp.b $loadaddr $part2base $filesize\0" \
770 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
771 " console=$consoledev,$baudrate $othbootargs; " \
772 "tftp $rootfsaddr $rootfsfile; " \
773 "tftp $loadaddr $kernelfile; " \
774 "tftp $dtbaddr $dtbfile; " \
775 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
776 "ramdisk_size=120000\0" \
777 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
778 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
779 "mw.l 0xffe0f008 0x00400000\0" \
780 "rootfsaddr=0x02F00000\0" \
781 "rootfsfile=rootfs.ext2.gz.uboot\0" \
782 "rootpath=/opt/nfsroot\0" \
783 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
784 "sf probe 0; sf erase 0 +$filesize; " \
785 "sf write $loadaddr 0 $filesize\0" \
786 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
787 "protect off 0xeC000000 +$filesize; " \
788 "erase 0xEC000000 +$filesize; " \
789 "cp.b $loadaddr 0xEC000000 $filesize; " \
790 "cmp.b $loadaddr 0xEC000000 $filesize; " \
791 "protect on 0xeC000000 +$filesize\0" \
792 "tftpflash=tftpboot $loadaddr $uboot; " \
793 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
794 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
795 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
796 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
797 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
798 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
799 "ubootfile=u-boot.bin\0" \
800 "upgrade=run flashuboot\0" \
801 "usb_phy_type=ulpi\0 " \
802 "boot_nfs= " \
803 "setenv bootargs root=/dev/nfs rw " \
804 "nfsroot=$serverip:$rootpath " \
805 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
806 "console=$consoledev,$baudrate $othbootargs;" \
807 "tftp $loadaddr $bootfile;" \
808 "tftp $fdtaddr $fdtfile;" \
809 "bootm $loadaddr - $fdtaddr\0" \
810 "boot_hd = " \
811 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
812 "console=$consoledev,$baudrate $othbootargs;" \
813 "usb start;" \
814 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
815 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
816 "bootm $loadaddr - $fdtaddr\0" \
817 "boot_usb_fat = " \
818 "setenv bootargs root=/dev/ram rw " \
819 "console=$consoledev,$baudrate $othbootargs " \
820 "ramdisk_size=$ramdisk_size;" \
821 "usb start;" \
822 "fatload usb 0:2 $loadaddr $bootfile;" \
823 "fatload usb 0:2 $fdtaddr $fdtfile;" \
824 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
825 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
826 "boot_usb_ext2 = " \
827 "setenv bootargs root=/dev/ram rw " \
828 "console=$consoledev,$baudrate $othbootargs " \
829 "ramdisk_size=$ramdisk_size;" \
830 "usb start;" \
831 "ext2load usb 0:4 $loadaddr $bootfile;" \
832 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
833 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
834 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
835 "boot_nor = " \
836 "setenv bootargs root=/dev/$jffs2nor rw " \
837 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
838 "bootm $norbootaddr - $norfdtaddr\0 " \
839 "boot_ram = " \
840 "setenv bootargs root=/dev/ram rw " \
841 "console=$consoledev,$baudrate $othbootargs " \
842 "ramdisk_size=$ramdisk_size;" \
843 "tftp $ramdiskaddr $ramdiskfile;" \
844 "tftp $loadaddr $bootfile;" \
845 "tftp $fdtaddr $fdtfile;" \
846 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
847
848 #endif
849 #endif
850
851 #endif /* __CONFIG_H */
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