]> git.ipfire.org Git - thirdparty/u-boot.git/blob - include/configs/UCP1020.h
projects / thirdparty / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'u-boot-imx-20181025' of git://git.denx.de/u-boot-imx
[thirdparty/u-boot.git] / include / configs / UCP1020.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright 2013-2015 Arcturus Networks, Inc.
4 * http://www.arcturusnetworks.com/products/ucp1020/
5 * based on include/configs/p1_p2_rdb_pc.h
6 * original copyright follows:
7 * Copyright 2009-2011 Freescale Semiconductor, Inc.
8 */
9
10 /*
11 * QorIQ uCP1020-xx boards configuration file
12 */
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15
16 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
17 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
18 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
19 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
20 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
21 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
22
23 #if defined(CONFIG_TARTGET_UCP1020T1)
24
25 #define CONFIG_UCP1020_REV_1_3
26
27 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
28
29 #define CONFIG_TSEC1
30 #define CONFIG_TSEC3
31 #define CONFIG_HAS_ETH0
32 #define CONFIG_HAS_ETH1
33 #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
34 #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
35 #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
36 #define CONFIG_IPADDR 10.80.41.229
37 #define CONFIG_SERVERIP 10.80.41.227
38 #define CONFIG_NETMASK 255.255.252.0
39 #define CONFIG_ETHPRIME "eTSEC3"
40
41 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
42
43 #define CONFIG_SYS_L2_SIZE (256 << 10)
44
45 #endif
46
47 #if defined(CONFIG_TARGET_UCP1020)
48
49 #define CONFIG_UCP1020
50 #define CONFIG_UCP1020_REV_1_3
51
52 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
53
54 #define CONFIG_TSEC1
55 #define CONFIG_TSEC2
56 #define CONFIG_TSEC3
57 #define CONFIG_HAS_ETH0
58 #define CONFIG_HAS_ETH1
59 #define CONFIG_HAS_ETH2
60 #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
61 #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
62 #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
63 #define CONFIG_IPADDR 192.168.1.81
64 #define CONFIG_IPADDR1 192.168.1.82
65 #define CONFIG_IPADDR2 192.168.1.83
66 #define CONFIG_SERVERIP 192.168.1.80
67 #define CONFIG_GATEWAYIP 102.168.1.1
68 #define CONFIG_NETMASK 255.255.255.0
69 #define CONFIG_ETHPRIME "eTSEC1"
70
71 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
72
73 #define CONFIG_SYS_L2_SIZE (256 << 10)
74
75 #endif
76
77 #ifdef CONFIG_SDCARD
78 #define CONFIG_RAMBOOT_SDCARD
79 #define CONFIG_SYS_RAMBOOT
80 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
81 #endif
82
83 #ifdef CONFIG_SPIFLASH
84 #define CONFIG_RAMBOOT_SPIFLASH
85 #define CONFIG_SYS_RAMBOOT
86 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
87 #endif
88
89 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
90
91 #ifndef CONFIG_RESET_VECTOR_ADDRESS
92 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
93 #endif
94
95 #ifndef CONFIG_SYS_MONITOR_BASE
96 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
97 #endif
98
99 #define CONFIG_ENV_OVERWRITE
100
101 #define CONFIG_SYS_SATA_MAX_DEVICE 2
102 #define CONFIG_LBA48
103
104 #define CONFIG_SYS_CLK_FREQ 66666666
105 #define CONFIG_DDR_CLK_FREQ 66666666
106
107 #define CONFIG_HWCONFIG
108
109 /*
110 * These can be toggled for performance analysis, otherwise use default.
111 */
112 #define CONFIG_L2_CACHE
113 #define CONFIG_BTB
114
115 #define CONFIG_ENABLE_36BIT_PHYS
116
117 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
118 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
119
120 #define CONFIG_SYS_CCSRBAR 0xffe00000
121 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
122
123 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
124 SPL code*/
125 #ifdef CONFIG_SPL_BUILD
126 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
127 #endif
128
129 /* DDR Setup */
130 #define CONFIG_DDR_ECC_ENABLE
131 #ifndef CONFIG_DDR_ECC_ENABLE
132 #define CONFIG_SYS_DDR_RAW_TIMING
133 #define CONFIG_DDR_SPD
134 #endif
135 #define CONFIG_SYS_SPD_BUS_NUM 1
136 #undef CONFIG_FSL_DDR_INTERACTIVE
137
138 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
139 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
140 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
141 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
142 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
143
144 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
145
146 /* Default settings for DDR3 */
147 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
148 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
149 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
150 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
151 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
152 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
153
154 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
155 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
156 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
157 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
158
159 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
160 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
161 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
162 #define CONFIG_SYS_DDR_RCW_1 0x00000000
163 #define CONFIG_SYS_DDR_RCW_2 0x00000000
164 #ifdef CONFIG_DDR_ECC_ENABLE
165 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
166 #else
167 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
168 #endif
169 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
170 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
171 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
172
173 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
174 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
175 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
176 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
177 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
178 #define CONFIG_SYS_DDR_MODE_1 0x40461520
179 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
180 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
181
182 #undef CONFIG_CLOCKS_IN_MHZ
183
184 /*
185 * Memory map
186 *
187 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
188 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
189 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
190 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
191 * (early boot only)
192 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
193 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
194 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
195 */
196
197 /*
198 * Local Bus Definitions
199 */
200 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
201 #define CONFIG_SYS_FLASH_BASE 0xec000000
202
203 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
204
205 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
206 | BR_PS_16 | BR_V)
207
208 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
209
210 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
211 #define CONFIG_SYS_FLASH_QUIET_TEST
212 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
213
214 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
215
216 #undef CONFIG_SYS_FLASH_CHECKSUM
217 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
218 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
219
220 #define CONFIG_SYS_FLASH_EMPTY_INFO
221
222 #define CONFIG_SYS_INIT_RAM_LOCK
223 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
224 /* Initial L1 address */
225 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
226 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
227 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
228 /* Size of used area in RAM */
229 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
230
231 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
232 GENERATED_GBL_DATA_SIZE)
233 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
234
235 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
236 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
237
238 #define CONFIG_SYS_PMC_BASE 0xff980000
239 #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
240 #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
241 BR_PS_8 | BR_V)
242 #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
243 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
244 OR_GPCM_EAD)
245
246 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
247 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
248 #ifdef CONFIG_NAND_FSL_ELBC
249 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
250 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
251 #endif
252
253 /* Serial Port - controlled on board with jumper J8
254 * open - index 2
255 * shorted - index 1
256 */
257 #undef CONFIG_SERIAL_SOFTWARE_FIFO
258 #define CONFIG_SYS_NS16550_SERIAL
259 #define CONFIG_SYS_NS16550_REG_SIZE 1
260 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
261 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
262 #define CONFIG_NS16550_MIN_FUNCTIONS
263 #endif
264
265 #define CONFIG_SYS_BAUDRATE_TABLE \
266 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
267
268 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
269 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
270
271 /* I2C */
272 #define CONFIG_SYS_I2C
273 #define CONFIG_SYS_I2C_FSL
274 #define CONFIG_SYS_FSL_I2C_SPEED 400000
275 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
276 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
277 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
278 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
279 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
280 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
281 #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
282
283 #define CONFIG_RTC_DS1337
284 #define CONFIG_RTC_DS1337_NOOSC
285 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
286 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
287 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
288 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
289
290 /*
291 * eSPI - Enhanced SPI
292 */
293 #define CONFIG_HARD_SPI
294
295 #define CONFIG_SF_DEFAULT_SPEED 10000000
296 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
297
298 #if defined(CONFIG_PCI)
299 /*
300 * General PCI
301 * Memory space is mapped 1-1, but I/O space must start from 0.
302 */
303
304 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
305 #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
306 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
307 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
308 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
309 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
310 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
311 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
312 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
313 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
314
315 /* controller 1, Slot 2, tgtid 1, Base address a000 */
316 #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
317 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
318 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
319 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
320 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
321 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
322 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
323 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
324 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
325
326 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
327 #endif /* CONFIG_PCI */
328
329 /*
330 * Environment
331 */
332 #ifdef CONFIG_ENV_FIT_UCBOOT
333
334 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
335 #define CONFIG_ENV_SIZE 0x20000
336 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
337
338 #else
339
340 #define CONFIG_ENV_SPI_BUS 0
341 #define CONFIG_ENV_SPI_CS 0
342 #define CONFIG_ENV_SPI_MAX_HZ 10000000
343 #define CONFIG_ENV_SPI_MODE 0
344
345 #ifdef CONFIG_RAMBOOT_SPIFLASH
346
347 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */
348 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
349 #define CONFIG_ENV_SECT_SIZE 0x1000
350
351 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
352 /* Address and size of Redundant Environment Sector */
353 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
354 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
355 #endif
356
357 #elif defined(CONFIG_RAMBOOT_SDCARD)
358 #define CONFIG_FSL_FIXED_MMC_LOCATION
359 #define CONFIG_ENV_SIZE 0x2000
360 #define CONFIG_SYS_MMC_ENV_DEV 0
361
362 #elif defined(CONFIG_SYS_RAMBOOT)
363 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
364 #define CONFIG_ENV_SIZE 0x2000
365
366 #else
367 #define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
368 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
369 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
370 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
371 #if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
372 /* Address and size of Redundant Environment Sector */
373 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
374 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
375 #endif
376
377 #endif
378
379 #endif /* CONFIG_ENV_FIT_UCBOOT */
380
381 #define CONFIG_LOADS_ECHO /* echo on for serial download */
382 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
383
384 /*
385 * USB
386 */
387 #define CONFIG_HAS_FSL_DR_USB
388
389 #if defined(CONFIG_HAS_FSL_DR_USB)
390 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
391
392 #ifdef CONFIG_USB_EHCI_HCD
393 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
394 #define CONFIG_USB_EHCI_FSL
395 #endif
396 #endif
397
398 #undef CONFIG_WATCHDOG /* watchdog disabled */
399
400 #ifdef CONFIG_MMC
401 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
402 #define CONFIG_MMC_SPI
403 #endif
404
405 /* Misc Extra Settings */
406 #undef CONFIG_WATCHDOG /* watchdog disabled */
407
408 /*
409 * Miscellaneous configurable options
410 */
411 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
412 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
413
414 /*
415 * For booting Linux, the board info and command line data
416 * have to be in the first 64 MB of memory, since this is
417 * the maximum mapped by the Linux kernel during initialization.
418 */
419 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
420 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
421
422 #if defined(CONFIG_CMD_KGDB)
423 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
424 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
425 #endif
426
427 /*
428 * Environment Configuration
429 */
430
431 #if defined(CONFIG_TSEC_ENET)
432
433 #if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
434 #else
435 #error "UCP1020 module revision is not defined !!!"
436 #endif
437
438 #define CONFIG_BOOTP_SERVERIP
439
440 #define CONFIG_TSEC1_NAME "eTSEC1"
441 #define CONFIG_TSEC2_NAME "eTSEC2"
442 #define CONFIG_TSEC3_NAME "eTSEC3"
443
444 #define TSEC1_PHY_ADDR 4
445 #define TSEC2_PHY_ADDR 0
446 #define TSEC2_PHY_ADDR_SGMII 0x00
447 #define TSEC3_PHY_ADDR 6
448
449 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
450 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
451 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
452
453 #define TSEC1_PHYIDX 0
454 #define TSEC2_PHYIDX 0
455 #define TSEC3_PHYIDX 0
456
457 #endif
458
459 #define CONFIG_HOSTNAME "UCP1020"
460 #define CONFIG_ROOTPATH "/opt/nfsroot"
461 #define CONFIG_BOOTFILE "uImage"
462 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
463
464 /* default location for tftp and bootm */
465 #define CONFIG_LOADADDR 1000000
466
467 #if defined(CONFIG_DONGLE)
468
469 #define CONFIG_EXTRA_ENV_SETTINGS \
470 "bootcmd=run prog_spi_mbrbootcramfs\0" \
471 "bootfile=uImage\0" \
472 "consoledev=ttyS0\0" \
473 "cramfsfile=image.cramfs\0" \
474 "dtbaddr=0x00c00000\0" \
475 "dtbfile=image.dtb\0" \
476 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
477 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
478 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
479 "fileaddr=0x01000000\0" \
480 "filesize=0x00080000\0" \
481 "flashmbr=sf probe 0; " \
482 "tftp $loadaddr $mbr; " \
483 "sf erase $mbr_offset +$filesize; " \
484 "sf write $loadaddr $mbr_offset $filesize\0" \
485 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
486 "protect off $nor_recoveryaddr +$filesize; " \
487 "erase $nor_recoveryaddr +$filesize; " \
488 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
489 "protect on $nor_recoveryaddr +$filesize\0 " \
490 "flashuboot=tftp $ubootaddr $ubootfile; " \
491 "protect off $nor_ubootaddr +$filesize; " \
492 "erase $nor_ubootaddr +$filesize; " \
493 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
494 "protect on $nor_ubootaddr +$filesize\0 " \
495 "flashworking=tftp $workingaddr $cramfsfile; " \
496 "protect off $nor_workingaddr +$filesize; " \
497 "erase $nor_workingaddr +$filesize; " \
498 "cp.b $workingaddr $nor_workingaddr $filesize; " \
499 "protect on $nor_workingaddr +$filesize\0 " \
500 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
501 "kerneladdr=0x01100000\0" \
502 "kernelfile=uImage\0" \
503 "loadaddr=0x01000000\0" \
504 "mbr=uCP1020d.mbr\0" \
505 "mbr_offset=0x00000000\0" \
506 "mmbr=uCP1020Quiet.mbr\0" \
507 "mmcpart=0:2\0" \
508 "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
509 "mmc erase 1 1; " \
510 "mmc write $loadaddr 1 1\0" \
511 "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
512 "mmc erase 0x40 0x400; " \
513 "mmc write $loadaddr 0x40 0x400\0" \
514 "netdev=eth0\0" \
515 "nor_recoveryaddr=0xEC0A0000\0" \
516 "nor_ubootaddr=0xEFF80000\0" \
517 "nor_workingaddr=0xECFA0000\0" \
518 "norbootrecovery=setenv bootargs $recoverybootargs" \
519 " console=$consoledev,$baudrate $othbootargs; " \
520 "run norloadrecovery; " \
521 "bootm $kerneladdr - $dtbaddr\0" \
522 "norbootworking=setenv bootargs $workingbootargs" \
523 " console=$consoledev,$baudrate $othbootargs; " \
524 "run norloadworking; " \
525 "bootm $kerneladdr - $dtbaddr\0" \
526 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
527 "setenv cramfsaddr $nor_recoveryaddr; " \
528 "cramfsload $dtbaddr $dtbfile; " \
529 "cramfsload $kerneladdr $kernelfile\0" \
530 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
531 "setenv cramfsaddr $nor_workingaddr; " \
532 "cramfsload $dtbaddr $dtbfile; " \
533 "cramfsload $kerneladdr $kernelfile\0" \
534 "prog_spi_mbr=run spi__mbr\0" \
535 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
536 "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
537 "run spi__cramfs\0" \
538 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
539 " console=$consoledev,$baudrate $othbootargs; " \
540 "tftp $rootfsaddr $rootfsfile; " \
541 "tftp $loadaddr $kernelfile; " \
542 "tftp $dtbaddr $dtbfile; " \
543 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
544 "ramdisk_size=120000\0" \
545 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
546 "recoveryaddr=0x02F00000\0" \
547 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
548 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
549 "mw.l 0xffe0f008 0x00400000\0" \
550 "rootfsaddr=0x02F00000\0" \
551 "rootfsfile=rootfs.ext2.gz.uboot\0" \
552 "rootpath=/opt/nfsroot\0" \
553 "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
554 "protect off 0xeC000000 +$filesize; " \
555 "erase 0xEC000000 +$filesize; " \
556 "cp.b $loadaddr 0xEC000000 $filesize; " \
557 "cmp.b $loadaddr 0xEC000000 $filesize; " \
558 "protect on 0xeC000000 +$filesize\0" \
559 "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
560 "protect off 0xeFF80000 +$filesize; " \
561 "erase 0xEFF80000 +$filesize; " \
562 "cp.b $loadaddr 0xEFF80000 $filesize; " \
563 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
564 "protect on 0xeFF80000 +$filesize\0" \
565 "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
566 "sf probe 0; sf erase 0x8000 +$filesize; " \
567 "sf write $loadaddr 0x8000 $filesize\0" \
568 "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
569 "protect off 0xec0a0000 +$filesize; " \
570 "erase 0xeC0A0000 +$filesize; " \
571 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
572 "protect on 0xec0a0000 +$filesize\0" \
573 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
574 "sf probe 1; sf erase 0 +$filesize; " \
575 "sf write $loadaddr 0 $filesize\0" \
576 "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
577 "sf probe 0; sf erase 0 +$filesize; " \
578 "sf write $loadaddr 0 $filesize\0" \
579 "tftpflash=tftpboot $loadaddr $uboot; " \
580 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
581 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
582 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
583 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
584 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
585 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
586 "ubootaddr=0x01000000\0" \
587 "ubootfile=u-boot.bin\0" \
588 "ubootd=u-boot4dongle.bin\0" \
589 "upgrade=run flashworking\0" \
590 "usb_phy_type=ulpi\0 " \
591 "workingaddr=0x02F00000\0" \
592 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
593
594 #else
595
596 #if defined(CONFIG_UCP1020T1)
597
598 #define CONFIG_EXTRA_ENV_SETTINGS \
599 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
600 "bootfile=uImage\0" \
601 "consoledev=ttyS0\0" \
602 "cramfsfile=image.cramfs\0" \
603 "dtbaddr=0x00c00000\0" \
604 "dtbfile=image.dtb\0" \
605 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
606 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
607 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
608 "fileaddr=0x01000000\0" \
609 "filesize=0x00080000\0" \
610 "flashmbr=sf probe 0; " \
611 "tftp $loadaddr $mbr; " \
612 "sf erase $mbr_offset +$filesize; " \
613 "sf write $loadaddr $mbr_offset $filesize\0" \
614 "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
615 "protect off $nor_recoveryaddr +$filesize; " \
616 "erase $nor_recoveryaddr +$filesize; " \
617 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
618 "protect on $nor_recoveryaddr +$filesize\0 " \
619 "flashuboot=tftp $ubootaddr $ubootfile; " \
620 "protect off $nor_ubootaddr +$filesize; " \
621 "erase $nor_ubootaddr +$filesize; " \
622 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
623 "protect on $nor_ubootaddr +$filesize\0 " \
624 "flashworking=tftp $workingaddr $cramfsfile; " \
625 "protect off $nor_workingaddr +$filesize; " \
626 "erase $nor_workingaddr +$filesize; " \
627 "cp.b $workingaddr $nor_workingaddr $filesize; " \
628 "protect on $nor_workingaddr +$filesize\0 " \
629 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
630 "kerneladdr=0x01100000\0" \
631 "kernelfile=uImage\0" \
632 "loadaddr=0x01000000\0" \
633 "mbr=uCP1020.mbr\0" \
634 "mbr_offset=0x00000000\0" \
635 "netdev=eth0\0" \
636 "nor_recoveryaddr=0xEC0A0000\0" \
637 "nor_ubootaddr=0xEFF80000\0" \
638 "nor_workingaddr=0xECFA0000\0" \
639 "norbootrecovery=setenv bootargs $recoverybootargs" \
640 " console=$consoledev,$baudrate $othbootargs; " \
641 "run norloadrecovery; " \
642 "bootm $kerneladdr - $dtbaddr\0" \
643 "norbootworking=setenv bootargs $workingbootargs" \
644 " console=$consoledev,$baudrate $othbootargs; " \
645 "run norloadworking; " \
646 "bootm $kerneladdr - $dtbaddr\0" \
647 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
648 "setenv cramfsaddr $nor_recoveryaddr; " \
649 "cramfsload $dtbaddr $dtbfile; " \
650 "cramfsload $kerneladdr $kernelfile\0" \
651 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
652 "setenv cramfsaddr $nor_workingaddr; " \
653 "cramfsload $dtbaddr $dtbfile; " \
654 "cramfsload $kerneladdr $kernelfile\0" \
655 "othbootargs=quiet\0" \
656 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
657 " console=$consoledev,$baudrate $othbootargs; " \
658 "tftp $rootfsaddr $rootfsfile; " \
659 "tftp $loadaddr $kernelfile; " \
660 "tftp $dtbaddr $dtbfile; " \
661 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
662 "ramdisk_size=120000\0" \
663 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
664 "recoveryaddr=0x02F00000\0" \
665 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
666 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
667 "mw.l 0xffe0f008 0x00400000\0" \
668 "rootfsaddr=0x02F00000\0" \
669 "rootfsfile=rootfs.ext2.gz.uboot\0" \
670 "rootpath=/opt/nfsroot\0" \
671 "silent=1\0" \
672 "tftpflash=tftpboot $loadaddr $uboot; " \
673 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
674 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
675 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
676 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
677 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
678 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
679 "ubootaddr=0x01000000\0" \
680 "ubootfile=u-boot.bin\0" \
681 "upgrade=run flashworking\0" \
682 "workingaddr=0x02F00000\0" \
683 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
684
685 #else /* For Arcturus Modules */
686
687 #define CONFIG_EXTRA_ENV_SETTINGS \
688 "bootcmd=run norkernel\0" \
689 "bootfile=uImage\0" \
690 "consoledev=ttyS0\0" \
691 "dtbaddr=0x00c00000\0" \
692 "dtbfile=image.dtb\0" \
693 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
694 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
695 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
696 "fileaddr=0x01000000\0" \
697 "filesize=0x00080000\0" \
698 "flashmbr=sf probe 0; " \
699 "tftp $loadaddr $mbr; " \
700 "sf erase $mbr_offset +$filesize; " \
701 "sf write $loadaddr $mbr_offset $filesize\0" \
702 "flashuboot=tftp $loadaddr $ubootfile; " \
703 "protect off $nor_ubootaddr0 +$filesize; " \
704 "erase $nor_ubootaddr0 +$filesize; " \
705 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
706 "protect on $nor_ubootaddr0 +$filesize; " \
707 "protect off $nor_ubootaddr1 +$filesize; " \
708 "erase $nor_ubootaddr1 +$filesize; " \
709 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
710 "protect on $nor_ubootaddr1 +$filesize\0 " \
711 "format0=protect off $part0base +$part0size; " \
712 "erase $part0base +$part0size\0" \
713 "format1=protect off $part1base +$part1size; " \
714 "erase $part1base +$part1size\0" \
715 "format2=protect off $part2base +$part2size; " \
716 "erase $part2base +$part2size\0" \
717 "format3=protect off $part3base +$part3size; " \
718 "erase $part3base +$part3size\0" \
719 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
720 "kerneladdr=0x01100000\0" \
721 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
722 "kernelfile=uImage\0" \
723 "loadaddr=0x01000000\0" \
724 "mbr=uCP1020.mbr\0" \
725 "mbr_offset=0x00000000\0" \
726 "netdev=eth0\0" \
727 "nor_ubootaddr0=0xEC000000\0" \
728 "nor_ubootaddr1=0xEFF80000\0" \
729 "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
730 "run norkernelload; " \
731 "bootm $kerneladdr - $dtbaddr\0" \
732 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
733 "setenv cramfsaddr $part0base; " \
734 "cramfsload $dtbaddr $dtbfile; " \
735 "cramfsload $kerneladdr $kernelfile\0" \
736 "part0base=0xEC100000\0" \
737 "part0size=0x00700000\0" \
738 "part1base=0xEC800000\0" \
739 "part1size=0x02000000\0" \
740 "part2base=0xEE800000\0" \
741 "part2size=0x00800000\0" \
742 "part3base=0xEF000000\0" \
743 "part3size=0x00F80000\0" \
744 "partENVbase=0xEC080000\0" \
745 "partENVsize=0x00080000\0" \
746 "program0=tftp part0-000000.bin; " \
747 "protect off $part0base +$filesize; " \
748 "erase $part0base +$filesize; " \
749 "cp.b $loadaddr $part0base $filesize; " \
750 "echo Verifying...; " \
751 "cmp.b $loadaddr $part0base $filesize\0" \
752 "program1=tftp part1-000000.bin; " \
753 "protect off $part1base +$filesize; " \
754 "erase $part1base +$filesize; " \
755 "cp.b $loadaddr $part1base $filesize; " \
756 "echo Verifying...; " \
757 "cmp.b $loadaddr $part1base $filesize\0" \
758 "program2=tftp part2-000000.bin; " \
759 "protect off $part2base +$filesize; " \
760 "erase $part2base +$filesize; " \
761 "cp.b $loadaddr $part2base $filesize; " \
762 "echo Verifying...; " \
763 "cmp.b $loadaddr $part2base $filesize\0" \
764 "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
765 " console=$consoledev,$baudrate $othbootargs; " \
766 "tftp $rootfsaddr $rootfsfile; " \
767 "tftp $loadaddr $kernelfile; " \
768 "tftp $dtbaddr $dtbfile; " \
769 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
770 "ramdisk_size=120000\0" \
771 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
772 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
773 "mw.l 0xffe0f008 0x00400000\0" \
774 "rootfsaddr=0x02F00000\0" \
775 "rootfsfile=rootfs.ext2.gz.uboot\0" \
776 "rootpath=/opt/nfsroot\0" \
777 "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
778 "sf probe 0; sf erase 0 +$filesize; " \
779 "sf write $loadaddr 0 $filesize\0" \
780 "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
781 "protect off 0xeC000000 +$filesize; " \
782 "erase 0xEC000000 +$filesize; " \
783 "cp.b $loadaddr 0xEC000000 $filesize; " \
784 "cmp.b $loadaddr 0xEC000000 $filesize; " \
785 "protect on 0xeC000000 +$filesize\0" \
786 "tftpflash=tftpboot $loadaddr $uboot; " \
787 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
788 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
789 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
790 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
791 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
792 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
793 "ubootfile=u-boot.bin\0" \
794 "upgrade=run flashuboot\0" \
795 "usb_phy_type=ulpi\0 " \
796 "boot_nfs= " \
797 "setenv bootargs root=/dev/nfs rw " \
798 "nfsroot=$serverip:$rootpath " \
799 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
800 "console=$consoledev,$baudrate $othbootargs;" \
801 "tftp $loadaddr $bootfile;" \
802 "tftp $fdtaddr $fdtfile;" \
803 "bootm $loadaddr - $fdtaddr\0" \
804 "boot_hd = " \
805 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
806 "console=$consoledev,$baudrate $othbootargs;" \
807 "usb start;" \
808 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
809 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
810 "bootm $loadaddr - $fdtaddr\0" \
811 "boot_usb_fat = " \
812 "setenv bootargs root=/dev/ram rw " \
813 "console=$consoledev,$baudrate $othbootargs " \
814 "ramdisk_size=$ramdisk_size;" \
815 "usb start;" \
816 "fatload usb 0:2 $loadaddr $bootfile;" \
817 "fatload usb 0:2 $fdtaddr $fdtfile;" \
818 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
819 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
820 "boot_usb_ext2 = " \
821 "setenv bootargs root=/dev/ram rw " \
822 "console=$consoledev,$baudrate $othbootargs " \
823 "ramdisk_size=$ramdisk_size;" \
824 "usb start;" \
825 "ext2load usb 0:4 $loadaddr $bootfile;" \
826 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
827 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
828 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
829 "boot_nor = " \
830 "setenv bootargs root=/dev/$jffs2nor rw " \
831 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
832 "bootm $norbootaddr - $norfdtaddr\0 " \
833 "boot_ram = " \
834 "setenv bootargs root=/dev/ram rw " \
835 "console=$consoledev,$baudrate $othbootargs " \
836 "ramdisk_size=$ramdisk_size;" \
837 "tftp $ramdiskaddr $ramdiskfile;" \
838 "tftp $loadaddr $bootfile;" \
839 "tftp $fdtaddr $fdtfile;" \
840 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
841
842 #endif
843 #endif
844
845 #endif /* __CONFIG_H */
"Das U-Boot" Source Tree