include/configs/VCMA9.h

   1 /*
   2  * (C) Copyright 2002, 2003
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  * Gary Jennejohn <gj@denx.de>
   6  * David Mueller <d.mueller@elsoft.ch>
   7  *
   8  * Configuation settings for the MPL VCMA9 board.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  * (easy to change)
  35  */
  36 #define CONFIG_ARM920T          1       /* This is an ARM920T Core      */
  37 #define CONFIG_S3C2410          1       /* in a SAMSUNG S3C2410 SoC     */
  38 #define CONFIG_VCMA9            1       /* on a MPL VCMA9 Board  */
  39 #define LITTLEENDIAN            1       /* used by usb_ohci.c           */
  40
  41 /* input clock of PLL */
  42 #define CONFIG_SYS_CLK_FREQ     12000000/* VCMA9 has 12MHz input clock  */
  43
  44 #define USE_920T_MMU            1
  45 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff  */
  46
  47 #define CONFIG_CMDLINE_TAG       1      /* enable passing of ATAGs      */
  48 #define CONFIG_SETUP_MEMORY_TAGS 1
  49 #define CONFIG_INITRD_TAG        1
  50
  51 /***********************************************************
  52  * Command definition
  53  ***********************************************************/
  54 #define CONFIG_COMMANDS \
  55                         (CONFIG_CMD_DFL  | \
  56                         CFG_CMD_CACHE    | \
  57                         /*CFG_CMD_JFFS2  |*/ \
  58                         /*CFG_CMD_NAND   |*/ \
  59                         CFG_CMD_EEPROM   | \
  60                         CFG_CMD_I2C      | \
  61                         CFG_CMD_USB      | \
  62                         CFG_CMD_REGINFO  | \
  63                         CFG_CMD_FAT      | \
  64                         CFG_CMD_DATE     | \
  65                         CFG_CMD_ELF      | \
  66                         CFG_CMD_DHCP     | \
  67                         CFG_CMD_PING     | \
  68                         CFG_CMD_BSP)
  69
  70 /* this must be included after the definiton of CONFIG_COMMANDS */
  71 #include <cmd_confdefs.h>
  72
  73 #define CFG_HUSH_PARSER
  74 #define CFG_PROMPT_HUSH_PS2 "> "
  75 /***********************************************************
  76  * I2C stuff:
  77  * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
  78  * address 0x50 with 16bit addressing
  79  ***********************************************************/
  80 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
  81 #define CFG_I2C_SPEED           100000  /* I2C speed */
  82 #define CFG_I2C_SLAVE           0x7F    /* I2C slave addr */
  83
  84 #define CFG_I2C_EEPROM_ADDR     0x50
  85 #define CFG_I2C_EEPROM_ADDR_LEN 2
  86 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
  87 #define CFG_ENV_OFFSET          0x000   /* environment starts at offset 0 */
  88 #define CFG_ENV_SIZE            0x800   /* 2KB should be more than enough */
  89
  90 #undef CFG_I2C_EEPROM_ADDR_OVERFLOW
  91 #define CFG_EEPROM_PAGE_WRITE_BITS 6    /* 64 bytes page write mode on 24C256 */
  92 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
  93
  94 /*
  95  * Size of malloc() pool
  96  */
  97 /*#define CONFIG_MALLOC_SIZE    (CFG_ENV_SIZE + 128*1024)*/
  98 #define CFG_GBL_DATA_SIZE       128             /* size in bytes reserved for initial data */
  99
 100 #define CFG_MONITOR_LEN         (256 * 1024)
 101 #define CFG_MALLOC_LEN          (1024 * 1024)   /* BUNZIP2 needs a lot of RAM */
 102
 103 /*
 104  * Hardware drivers
 105  */
 106 #define CONFIG_DRIVER_CS8900    1               /* we have a CS8900 on-board */
 107 #define CS8900_BASE             0x20000300
 108 #define CS8900_BUS16            1               /* the Linux driver does accesses as shorts */
 109
 110 #define CONFIG_DRIVER_S3C24X0_I2C       1       /* we use the buildin I2C controller */
 111
 112 /*
 113  * select serial console configuration
 114  */
 115 #define CONFIG_SERIAL1          1       /* we use SERIAL 1 on VCMA9 */
 116
 117 /************************************************************
 118  * USB support
 119  ************************************************************/
 120 #define CONFIG_USB_OHCI         1
 121 #define CONFIG_USB_KEYBOARD     1
 122 #define CONFIG_USB_STORAGE      1
 123 #define CONFIG_DOS_PARTITION    1
 124
 125 /* Enable needed helper functions */
 126 #define CFG_DEVICE_DEREGISTER           /* needs device_deregister */
 127
 128 /************************************************************
 129  * RTC
 130  ************************************************************/
 131 #define CONFIG_RTC_S3C24X0      1
 132
 133
 134 /* allow to overwrite serial and ethaddr */
 135 #define CONFIG_ENV_OVERWRITE
 136
 137 #define CONFIG_BAUDRATE         9600
 138
 139 #define CONFIG_BOOTDELAY        5
 140 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 141 #define CONFIG_BOOT_RETRY_TIME  -10     /* feature is avaiable but not enabled */
 142 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check console even if bootdelay = 0 */
 143
 144 #define CONFIG_NETMASK          255.255.255.0
 145 #define CONFIG_IPADDR           10.0.0.110
 146 #define CONFIG_SERVERIP         10.0.0.1
 147
 148 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 149 #define CONFIG_KGDB_BAUDRATE    115200          /* speed to run kgdb serial port */
 150 /* what's this ? it's not used anywhere */
 151 #define CONFIG_KGDB_SER_INDEX   1               /* which serial port to use */
 152 #endif
 153
 154 /*
 155  * Miscellaneous configurable options
 156  */
 157 #define CFG_LONGHELP                            /* undef to save memory         */
 158 #define CFG_PROMPT              "VCMA9 # "      /* Monitor Command Prompt       */
 159 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 160 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 161 #define CFG_MAXARGS             16              /* max number of command args   */
 162 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 163
 164 #define CFG_MEMTEST_START       0x30000000      /* memtest works on     */
 165 #define CFG_MEMTEST_END         0x30F80000      /* 15.5 MB in DRAM      */
 166
 167 #define CFG_ALT_MEMTEST
 168 #define CFG_LOAD_ADDR           0x30800000      /* default load address */
 169
 170
 171 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 172
 173 /* we configure PWM Timer 4 to 1us ~ 1MHz */
 174 /*#define       CFG_HZ                  1000000 */
 175 #define CFG_HZ                  1562500
 176
 177 /* valid baudrates */
 178 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 179
 180 /* support BZIP2 compression */
 181 #define CONFIG_BZIP2            1
 182
 183 /************************************************************
 184  * Ident
 185  ************************************************************/
 186 /*#define VERSION_TAG "released"*/
 187 #define VERSION_TAG "unstable"
 188 #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG
 189
 190 /*-----------------------------------------------------------------------
 191  * Stack sizes
 192  *
 193  * The stack sizes are set up in start.S using the settings below
 194  */
 195 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 196 #ifdef CONFIG_USE_IRQ
 197 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 198 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 199 #endif
 200
 201 /*-----------------------------------------------------------------------
 202  * Physical Memory Map
 203  */
 204 #define CONFIG_NR_DRAM_BANKS    1          /* we have 1 bank of DRAM */
 205 #define PHYS_SDRAM_1            0x30000000 /* SDRAM Bank #1 */
 206 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 207
 208 #define CFG_FLASH_BASE          PHYS_FLASH_1
 209
 210 /*-----------------------------------------------------------------------
 211  * FLASH and environment organization
 212  */
 213
 214 #define CONFIG_AMD_LV400        1       /* uncomment this if you have a LV400 flash */
 215 #if 0
 216 #define CONFIG_AMD_LV800        1       /* uncomment this if you have a LV800 flash */
 217 #endif
 218
 219 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks */
 220 #ifdef CONFIG_AMD_LV800
 221 #define PHYS_FLASH_SIZE         0x00100000 /* 1MB */
 222 #define CFG_MAX_FLASH_SECT      (19)    /* max number of sectors on one chip */
 223 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
 224 #endif
 225 #ifdef CONFIG_AMD_LV400
 226 #define PHYS_FLASH_SIZE         0x00080000 /* 512KB */
 227 #define CFG_MAX_FLASH_SECT      (11)    /* max number of sectors on one chip */
 228 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x070000) /* addr of environment */
 229 #endif
 230
 231 /* timeout values are in ticks */
 232 #define CFG_FLASH_ERASE_TOUT    (5*CFG_HZ) /* Timeout for Flash Erase */
 233 #define CFG_FLASH_WRITE_TOUT    (5*CFG_HZ) /* Timeout for Flash Write */
 234
 235 #if 0
 236 #define CFG_ENV_IS_IN_FLASH     1
 237 #define CFG_ENV_SIZE            0x10000 /* Total Size of Environment Sector */
 238 #endif
 239
 240
 241 #define CFG_JFFS2_FIRST_BANK    0
 242 #define CFG_JFFS2_NUM_BANKS     1
 243
 244 #define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
 245
 246 /*-----------------------------------------------------------------------
 247  * NAND flash settings
 248  */
 249 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 250
 251 #define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
 252 #define SECTORSIZE 512
 253
 254 #define ADDR_COLUMN 1
 255 #define ADDR_PAGE 2
 256 #define ADDR_COLUMN_PAGE 3
 257
 258 #define NAND_ChipID_UNKNOWN     0x00
 259 #define NAND_MAX_FLOORS 1
 260 #define NAND_MAX_CHIPS 1
 261
 262 #define NAND_WAIT_READY(nand)   NF_WaitRB()
 263
 264 #define NAND_DISABLE_CE(nand)   NF_SetCE(NFCE_HIGH)
 265 #define NAND_ENABLE_CE(nand)    NF_SetCE(NFCE_LOW)
 266
 267
 268 #define WRITE_NAND_COMMAND(d, adr)      NF_Cmd(d)
 269 #define WRITE_NAND_COMMANDW(d, adr)     NF_CmdW(d)
 270 #define WRITE_NAND_ADDRESS(d, adr)      NF_Addr(d)
 271 #define WRITE_NAND(d, adr)              NF_Write(d)
 272 #define READ_NAND(adr)                  NF_Read()
 273 /* the following functions are NOP's because S3C24X0 handles this in hardware */
 274 #define NAND_CTL_CLRALE(nandptr)
 275 #define NAND_CTL_SETALE(nandptr)
 276 #define NAND_CTL_CLRCLE(nandptr)
 277 #define NAND_CTL_SETCLE(nandptr)
 278
 279 #define CONFIG_MTD_NAND_VERIFY_WRITE    1
 280 #define CONFIG_MTD_NAND_ECC_JFFS2       1
 281
 282 #endif  /* CONFIG_COMMANDS & CFG_CMD_NAND */
 283
 284 #endif  /* __CONFIG_H */