include/configs/VOH405.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_VOH405           1       /* ...on a VOH405 board         */
  39
  40 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  41 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  42
  43 #define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
  44
  45 #define CONFIG_BAUDRATE         9600
  46 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  47
  48 #undef  CONFIG_BOOTARGS
  49 #undef  CONFIG_BOOTCOMMAND
  50
  51 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  52
  53 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
  54
  55 #define CONFIG_MII              1       /* MII PHY management           */
  56 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  57 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  58
  59 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  60
  61
  62 /*
  63  * BOOTP options
  64  */
  65 #define CONFIG_BOOTP_BOOTFILESIZE
  66 #define CONFIG_BOOTP_BOOTPATH
  67 #define CONFIG_BOOTP_GATEWAY
  68 #define CONFIG_BOOTP_HOSTNAME
  69
  70
  71 /*
  72  * Command line configuration.
  73  */
  74 #include <config_cmd_default.h>
  75
  76 #define CONFIG_CMD_DHCP
  77 #define CONFIG_CMD_PCI
  78 #define CONFIG_CMD_IRQ
  79 #define CONFIG_CMD_IDE
  80 #define CONFIG_CMD_FAT
  81 #define CONFIG_CMD_ELF
  82 #define CONFIG_CMD_NAND
  83 #define CONFIG_CMD_DATE
  84 #define CONFIG_CMD_I2C
  85 #define CONFIG_CMD_MII
  86 #define CONFIG_CMD_PING
  87 #define CONFIG_CMD_EEPROM
  88
  89
  90 #define CONFIG_MAC_PARTITION
  91 #define CONFIG_DOS_PARTITION
  92
  93 #define CONFIG_SUPPORT_VFAT
  94
  95 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  96
  97 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
  98 #define CFG_RTC_REG_BASE_ADDR    0xF0000500 /* RTC Base Address         */
  99
 100 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 101
 102 /*
 103  * Miscellaneous configurable options
 104  */
 105 #define CFG_LONGHELP                    /* undef to save memory         */
 106 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 107
 108 #undef  CFG_HUSH_PARSER                 /* use "hush" command parser    */
 109 #ifdef  CFG_HUSH_PARSER
 110 #define CFG_PROMPT_HUSH_PS2     "> "
 111 #endif
 112
 113 #if defined(CONFIG_CMD_KGDB)
 114 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 115 #else
 116 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 117 #endif
 118 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 119 #define CFG_MAXARGS     16              /* max number of command args   */
 120 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 121
 122 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
 123
 124 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 125
 126 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 127
 128 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 129 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 130
 131 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 132 #define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 133 #define CFG_BASE_BAUD       691200
 134 #define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 135
 136 /* The following table includes the supported baudrates */
 137 #define CFG_BAUDRATE_TABLE      \
 138         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 139          57600, 115200, 230400, 460800, 921600 }
 140
 141 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 142 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 143
 144 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 145
 146 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 147
 148 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 149
 150 #define CFG_RX_ETH_BUFFER       16      /* use 16 rx buffer on 405 emac */
 151
 152 /*-----------------------------------------------------------------------
 153  * NAND-FLASH stuff
 154  *-----------------------------------------------------------------------
 155  */
 156 #define CFG_NAND_BASE_LIST      { CFG_NAND_BASE }
 157 #define NAND_MAX_CHIPS          1
 158 #define CFG_MAX_NAND_DEVICE     1         /* Max number of NAND devices */
 159 #define NAND_BIG_DELAY_US       25
 160
 161 #define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
 162 #define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
 163 #define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 164 #define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 165
 166 #define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
 167
 168 /*-----------------------------------------------------------------------
 169  * PCI stuff
 170  *-----------------------------------------------------------------------
 171  */
 172 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 173 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 174 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 175
 176 #define CONFIG_PCI                      /* include pci support          */
 177 #define CONFIG_PCI_HOST PCI_HOST_HOST   /* select pci host function     */
 178 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 179                                         /* resource configuration       */
 180
 181 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 182
 183 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 184
 185 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 186 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 187 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 188 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 189 #define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 190 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 191 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 192 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 193 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 194
 195 /*-----------------------------------------------------------------------
 196  * IDE/ATA stuff
 197  *-----------------------------------------------------------------------
 198  */
 199 #undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
 200 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 201 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 202
 203 #define CFG_IDE_MAXBUS          2               /* max. 2 IDE busses    */
 204 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 205
 206 #define CONFIG_ATAPI            1       /* ATAPI for Travelstar         */
 207
 208 #define CFG_ATA_BASE_ADDR       0xF0100000
 209 #define CFG_ATA_IDE0_OFFSET     0x0000
 210 #define CFG_ATA_IDE1_OFFSET     0x0010
 211
 212 #define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O                  */
 213 #define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses  */
 214 #define CFG_ATA_ALT_OFFSET      0x0000  /* Offset for alternate registers       */
 215
 216 /*
 217  * For booting Linux, the board info and command line data
 218  * have to be in the first 8 MB of memory, since this is
 219  * the maximum mapped by the Linux kernel during initialization.
 220  */
 221 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 222 /*-----------------------------------------------------------------------
 223  * FLASH organization
 224  */
 225 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 226
 227 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 228 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 229
 230 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 231 #define CFG_FLASH_WRITE_TOUT    1000    /* Timeout for Flash Write (in ms)      */
 232
 233 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 234 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 235 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 236 /*
 237  * The following defines are added for buggy IOP480 byte interface.
 238  * All other boards should use the standard values (CPCI405 etc.)
 239  */
 240 #define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
 241 #define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
 242 #define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
 243
 244 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 245
 246 #if 0 /* test-only */
 247 #define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
 248 #define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
 249 #endif
 250
 251 /*-----------------------------------------------------------------------
 252  * Start addresses for the final memory configuration
 253  * (Set up by the startup code)
 254  * Please note that CFG_SDRAM_BASE _must_ start at 0
 255  */
 256 #define CFG_SDRAM_BASE          0x00000000
 257 #define CFG_FLASH_BASE          0xFFF80000
 258 #define CFG_MONITOR_BASE        TEXT_BASE
 259 #define CFG_MONITOR_LEN         (512 * 1024)    /* Reserve 512 kB for Monitor   */
 260 #define CFG_MALLOC_LEN          (2 * 1024*1024) /* Reserve 2 MB for malloc()    */
 261
 262 #if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
 263 # define CFG_RAMBOOT            1
 264 #else
 265 # undef CFG_RAMBOOT
 266 #endif
 267
 268 /*-----------------------------------------------------------------------
 269  * Environment Variable setup
 270  */
 271 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 272 #define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
 273 #define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
 274                                    /* total size of a CAT24WC16 is 2048 bytes */
 275
 276 #define CFG_NVRAM_BASE_ADDR     0xF0000500              /* NVRAM base address   */
 277 #define CFG_NVRAM_SIZE          242                     /* NVRAM size           */
 278
 279 /*-----------------------------------------------------------------------
 280  * I2C EEPROM (CAT24WC16) for environment
 281  */
 282 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 283 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 284 #define CFG_I2C_SLAVE           0x7F
 285
 286 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT24WC08             */
 287 #if 0 /* test-only */
 288 /* CAT24WC08/16... */
 289 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 290 /* mask of address bits that overflow into the "EEPROM chip address"    */
 291 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 292 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 293                                         /* 16 byte page write mode using*/
 294                                         /* last 4 bits of the address   */
 295 #else
 296 /* CAT24WC32/64... */
 297 #define CFG_I2C_EEPROM_ADDR_LEN 2       /* Bytes of address             */
 298 /* mask of address bits that overflow into the "EEPROM chip address"    */
 299 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x01
 300 #define CFG_EEPROM_PAGE_WRITE_BITS 5    /* The Catalyst CAT24WC32 has   */
 301                                         /* 32 byte page write mode using*/
 302                                         /* last 5 bits of the address   */
 303 #endif
 304 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 305 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 306
 307 /*-----------------------------------------------------------------------
 308  * Cache Configuration
 309  */
 310 #define CFG_DCACHE_SIZE         16384   /* For AMCC 405 CPUs, older 405 ppc's   */
 311                                         /* have only 8kB, 16kB is save here     */
 312 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 313 #if defined(CONFIG_CMD_KGDB)
 314 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 315 #endif
 316
 317 /*-----------------------------------------------------------------------
 318  * External Bus Controller (EBC) Setup
 319  */
 320
 321 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 322 #define DUART0_BA       0xF0000400          /* DUART Base Address               */
 323 #define DUART1_BA       0xF0000408          /* DUART Base Address               */
 324 #define RTC_BA          0xF0000500          /* RTC Base Address                 */
 325 #define VGA_BA          0xF1000000          /* Epson VGA Base Address           */
 326 #define CFG_NAND_BASE   0xF4000000          /* NAND FLASH Base Address          */
 327
 328 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 329 #define CFG_EBC_PB0AP           0x92015480
 330 /*#define CFG_EBC_PB0AP           0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
 331 #define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 332
 333 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
 334 #define CFG_EBC_PB1AP           0x92015480
 335 #define CFG_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
 336
 337 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 338 #define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 339 #define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 340
 341 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
 342 #define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 343 #define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 344
 345 /* Memory Bank 4 (Epson VGA) initialization                                     */
 346 #define CFG_EBC_PB4AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
 347 #define CFG_EBC_PB4CR   VGA_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
 348
 349 /*-----------------------------------------------------------------------
 350  * LCD Setup
 351  */
 352
 353 #define CFG_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
 354 #define CFG_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
 355 #define CFG_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
 356 #define CFG_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
 357
 358 #define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
 359
 360 /*-----------------------------------------------------------------------
 361  * FPGA stuff
 362  */
 363
 364 #define CFG_FPGA_BASE_ADDR 0xF0100100       /* FPGA internal Base Address       */
 365
 366 /* FPGA internal regs */
 367 #define CFG_FPGA_CTRL           0x000
 368
 369 /* FPGA Control Reg */
 370 #define CFG_FPGA_CTRL_CF_RESET  0x0001
 371 #define CFG_FPGA_CTRL_WDI       0x0002
 372 #define CFG_FPGA_CTRL_PS2_RESET 0x0020
 373
 374 #define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
 375 #define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
 376
 377 /* FPGA program pin configuration */
 378 #define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
 379 #define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
 380 #define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
 381 #define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
 382 #define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
 383
 384 /*-----------------------------------------------------------------------
 385  * Definitions for initial stack pointer and data area (in data cache)
 386  */
 387 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 388 #define CFG_TEMP_STACK_OCM        1
 389
 390 /* On Chip Memory location */
 391 #define CFG_OCM_DATA_ADDR       0xF8000000
 392 #define CFG_OCM_DATA_SIZE       0x1000
 393 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of SDRAM            */
 394 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM    */
 395
 396 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 397 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 398 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 399
 400 /*-----------------------------------------------------------------------
 401  * Definitions for GPIO setup (PPC405EP specific)
 402  *
 403  * GPIO0[0]     - External Bus Controller BLAST output
 404  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 405  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 406  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 407  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 408  * GPIO0[24-27] - UART0 control signal inputs/outputs
 409  * GPIO0[28-29] - UART1 data signal input/output
 410  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
 411  */
 412 #define CFG_GPIO0_OSRH          0x40000550
 413 #define CFG_GPIO0_OSRL          0x00000110
 414 #define CFG_GPIO0_ISR1H         0x00000000
 415 #define CFG_GPIO0_ISR1L         0x15555440
 416 #define CFG_GPIO0_TSRH          0x00000000
 417 #define CFG_GPIO0_TSRL          0x00000000
 418 #define CFG_GPIO0_TCR           0xF7FE0017
 419
 420 #define CFG_DUART_RST           (0x80000000 >> 14)
 421 #define CFG_LCD_ENDIAN          (0x80000000 >> 7)
 422 #define CFG_LCD0_RST            (0x80000000 >> 30)
 423 #define CFG_LCD1_RST            (0x80000000 >> 31)
 424
 425 /*
 426  * Internal Definitions
 427  *
 428  * Boot Flags
 429  */
 430 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 431 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 432
 433 /*
 434  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 435  * This value will be set if iic boot eprom is disabled.
 436  */
 437 #if 1
 438 #define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 439 #define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
 440 #endif
 441 #if 0
 442 #define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
 443 #define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
 444 #endif
 445 #if 0
 446 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 447 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 448 #endif
 449
 450 #endif  /* __CONFIG_H */