include/configs/VOH405.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  21 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  22 #define CONFIG_VOH405           1       /* ...on a VOH405 board         */
  23
  24 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  25
  26 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  27 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  28
  29 #define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
  30
  31 #define CONFIG_BAUDRATE         9600
  32 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  33
  34 #undef  CONFIG_BOOTARGS
  35 #undef  CONFIG_BOOTCOMMAND
  36
  37 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  38
  39 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  40
  41 #undef  CONFIG_HAS_ETH1
  42
  43 #define CONFIG_PPC4xx_EMAC
  44 #define CONFIG_MII              1       /* MII PHY management           */
  45 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  46 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  47 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  48
  49 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  50
  51
  52 /*
  53  * BOOTP options
  54  */
  55 #define CONFIG_BOOTP_BOOTFILESIZE
  56 #define CONFIG_BOOTP_BOOTPATH
  57 #define CONFIG_BOOTP_GATEWAY
  58 #define CONFIG_BOOTP_HOSTNAME
  59
  60
  61 /*
  62  * Command line configuration.
  63  */
  64 #include <config_cmd_default.h>
  65
  66 #define CONFIG_CMD_DHCP
  67 #define CONFIG_CMD_PCI
  68 #define CONFIG_CMD_IRQ
  69 #define CONFIG_CMD_IDE
  70 #define CONFIG_CMD_FAT
  71 #define CONFIG_CMD_ELF
  72 #define CONFIG_CMD_NAND
  73 #define CONFIG_CMD_DATE
  74 #define CONFIG_CMD_I2C
  75 #define CONFIG_CMD_MII
  76 #define CONFIG_CMD_PING
  77 #define CONFIG_CMD_EEPROM
  78
  79
  80 #define CONFIG_MAC_PARTITION
  81 #define CONFIG_DOS_PARTITION
  82
  83 #define CONFIG_SUPPORT_VFAT
  84
  85 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  86
  87 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
  88 #define CONFIG_SYS_RTC_REG_BASE_ADDR     0xF0000500 /* RTC Base Address         */
  89
  90 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  91
  92 /*
  93  * Miscellaneous configurable options
  94  */
  95 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  96
  97 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
  98
  99 #if defined(CONFIG_CMD_KGDB)
 100 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 101 #else
 102 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 103 #endif
 104 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 105 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 106 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 107
 108 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 109
 110 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 111
 112 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 113
 114 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 115 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 116
 117 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
 118 #define CONFIG_SYS_NS16550
 119 #define CONFIG_SYS_NS16550_SERIAL
 120 #define CONFIG_SYS_NS16550_REG_SIZE     1
 121 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 122
 123 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* no external serial clock used */
 124 #define CONFIG_SYS_BASE_BAUD       691200
 125
 126 /* The following table includes the supported baudrates */
 127 #define CONFIG_SYS_BAUDRATE_TABLE       \
 128         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 129          57600, 115200, 230400, 460800, 921600 }
 130
 131 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 132 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 133
 134 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 135
 136 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 137
 138 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 139
 140 /*-----------------------------------------------------------------------
 141  * NAND-FLASH stuff
 142  *-----------------------------------------------------------------------
 143  */
 144 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 145 #define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
 146 #define NAND_BIG_DELAY_US       25
 147
 148 #define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
 149 #define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
 150 #define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 151 #define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 152
 153 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
 154 #define CONFIG_SYS_NAND_QUIET          1
 155
 156 /*-----------------------------------------------------------------------
 157  * PCI stuff
 158  *-----------------------------------------------------------------------
 159  */
 160 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 161 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 162 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 163
 164 #define CONFIG_PCI                      /* include pci support          */
 165 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 166 #define CONFIG_PCI_HOST PCI_HOST_HOST   /* select pci host function     */
 167 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 168                                         /* resource configuration       */
 169
 170 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 171
 172 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 173
 174 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 175 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 176 #define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 177 #define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
 178 #define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 179 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 180 #define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
 181 #define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 182 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 183
 184 /*-----------------------------------------------------------------------
 185  * IDE/ATA stuff
 186  *-----------------------------------------------------------------------
 187  */
 188 #undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
 189 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 190 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 191
 192 #define CONFIG_SYS_IDE_MAXBUS           2               /* max. 2 IDE busses    */
 193 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 194
 195 #define CONFIG_SYS_ATA_BASE_ADDR        0xF0100000
 196 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 197 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0010
 198
 199 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O                  */
 200 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* Offset for normal register accesses  */
 201 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0000  /* Offset for alternate registers       */
 202
 203 /*
 204  * For booting Linux, the board info and command line data
 205  * have to be in the first 8 MB of memory, since this is
 206  * the maximum mapped by the Linux kernel during initialization.
 207  */
 208 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 209 /*-----------------------------------------------------------------------
 210  * FLASH organization
 211  */
 212 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 213
 214 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 215 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 216
 217 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 218 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 219
 220 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 221 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 222 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 223 /*
 224  * The following defines are added for buggy IOP480 byte interface.
 225  * All other boards should use the standard values (CPCI405 etc.)
 226  */
 227 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 228 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 229 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 230
 231 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 232
 233 /*-----------------------------------------------------------------------
 234  * Start addresses for the final memory configuration
 235  * (Set up by the startup code)
 236  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 237  */
 238 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 239 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 240 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 241 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Monitor   */
 242 #define CONFIG_SYS_MALLOC_LEN           (2 * 1024*1024) /* Reserve 2 MB for malloc()    */
 243
 244 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 245 # define CONFIG_SYS_RAMBOOT             1
 246 #else
 247 # undef CONFIG_SYS_RAMBOOT
 248 #endif
 249
 250 /*-----------------------------------------------------------------------
 251  * Environment Variable setup
 252  */
 253 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 254 #define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 255 #define CONFIG_ENV_SIZE         0x700   /* 2048 bytes may be used for env vars*/
 256                                    /* total size of a CAT24WC16 is 2048 bytes */
 257
 258 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xF0000500              /* NVRAM base address   */
 259 #define CONFIG_SYS_NVRAM_SIZE           242                     /* NVRAM size           */
 260
 261 /*-----------------------------------------------------------------------
 262  * I2C EEPROM (CAT24WC16) for environment
 263  */
 264 #define CONFIG_SYS_I2C
 265 #define CONFIG_SYS_I2C_PPC4XX
 266 #define CONFIG_SYS_I2C_PPC4XX_CH0
 267 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 268 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 269
 270 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT24WC08             */
 271 #define CONFIG_SYS_EEPROM_WREN         1
 272
 273 /* CAT24WC32/64... */
 274 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2        /* Bytes of address             */
 275 /* mask of address bits that overflow into the "EEPROM chip address"    */
 276 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x01
 277 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5     /* The Catalyst CAT24WC32 has   */
 278                                         /* 32 byte page write mode using*/
 279                                         /* last 5 bits of the address   */
 280 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 281
 282 /*-----------------------------------------------------------------------
 283  * External Bus Controller (EBC) Setup
 284  */
 285
 286 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 287 #define DUART0_BA       0xF0000400          /* DUART Base Address               */
 288 #define DUART1_BA       0xF0000408          /* DUART Base Address               */
 289 #define RTC_BA          0xF0000500          /* RTC Base Address                 */
 290 #define VGA_BA          0xF1000000          /* Epson VGA Base Address           */
 291 #define CONFIG_SYS_NAND_BASE    0xF4000000          /* NAND FLASH Base Address          */
 292
 293 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 294 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 295 /*#define CONFIG_SYS_EBC_PB0AP            0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
 296 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 297
 298 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
 299 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 300 #define CONFIG_SYS_EBC_PB1CR            0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
 301
 302 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 303 #define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 304 #define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 305
 306 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
 307 #define CONFIG_SYS_EBC_PB3AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 308 #define CONFIG_SYS_EBC_PB3CR            0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 309
 310 /* Memory Bank 4 (Epson VGA) initialization                                     */
 311 #define CONFIG_SYS_EBC_PB4AP    0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
 312 #define CONFIG_SYS_EBC_PB4CR    VGA_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
 313
 314 /*-----------------------------------------------------------------------
 315  * LCD Setup
 316  */
 317
 318 #define CONFIG_SYS_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
 319 #define CONFIG_SYS_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
 320 #define CONFIG_SYS_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
 321 #define CONFIG_SYS_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
 322
 323 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
 324
 325 /*-----------------------------------------------------------------------
 326  * FPGA stuff
 327  */
 328
 329 #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100        /* FPGA internal Base Address       */
 330
 331 /* FPGA internal regs */
 332 #define CONFIG_SYS_FPGA_CTRL            0x000
 333
 334 /* FPGA Control Reg */
 335 #define CONFIG_SYS_FPGA_CTRL_CF_RESET   0x0001
 336 #define CONFIG_SYS_FPGA_CTRL_WDI        0x0002
 337 #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
 338
 339 #define CONFIG_SYS_FPGA_SPARTAN2        1           /* using Xilinx Spartan 2 now    */
 340 #define CONFIG_SYS_FPGA_MAX_SIZE        128*1024    /* 128kByte is enough for XC2S50E*/
 341
 342 /* FPGA program pin configuration */
 343 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* FPGA program pin (ppc output) */
 344 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* FPGA clk pin (ppc output)     */
 345 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* FPGA data pin (ppc output)    */
 346 #define CONFIG_SYS_FPGA_INIT            0x00010000  /* FPGA init pin (ppc input)     */
 347 #define CONFIG_SYS_FPGA_DONE            0x00008000  /* FPGA done pin (ppc input)     */
 348
 349 /*-----------------------------------------------------------------------
 350  * Definitions for initial stack pointer and data area (in data cache)
 351  */
 352 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 353 #define CONFIG_SYS_TEMP_STACK_OCM         1
 354
 355 /* On Chip Memory location */
 356 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 357 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 358 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 359 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 360
 361 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 362 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 363
 364 /*-----------------------------------------------------------------------
 365  * Definitions for GPIO setup (PPC405EP specific)
 366  *
 367  * GPIO0[0]     - External Bus Controller BLAST output
 368  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 369  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 370  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 371  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 372  * GPIO0[24-27] - UART0 control signal inputs/outputs
 373  * GPIO0[28-29] - UART1 data signal input/output
 374  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
 375  */
 376 #define CONFIG_SYS_GPIO0_OSRL           0x00000550
 377 #define CONFIG_SYS_GPIO0_OSRH           0x00000110
 378 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000
 379 #define CONFIG_SYS_GPIO0_ISR1H          0x15555440
 380 #define CONFIG_SYS_GPIO0_TSRL           0x00000000
 381 #define CONFIG_SYS_GPIO0_TSRH           0x00000000
 382 #define CONFIG_SYS_GPIO0_TCR            0x777E0017
 383
 384 #define CONFIG_SYS_DUART_RST            (0x80000000 >> 14)
 385 #define CONFIG_SYS_LCD_ENDIAN           (0x80000000 >> 7)
 386 #define CONFIG_SYS_IIC_ON               (0x80000000 >> 8)
 387 #define CONFIG_SYS_LCD0_RST             (0x80000000 >> 30)
 388 #define CONFIG_SYS_LCD1_RST             (0x80000000 >> 31)
 389 #define CONFIG_SYS_EEPROM_WP            (0x80000000 >> 0)
 390
 391 /*
 392  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 393  * This value will be set if iic boot eprom is disabled.
 394  */
 395 #if 1
 396 #define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 397 #define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
 398 #endif
 399 #if 0
 400 #define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
 401 #define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
 402 #endif
 403 #if 0
 404 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 405 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 406 #endif
 407
 408 #endif  /* __CONFIG_H */