include/configs/VOH405.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_VOH405           1       /* ...on a VOH405 board         */
  39
  40 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  41
  42 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  43 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  44
  45 #define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
  46
  47 #define CONFIG_BAUDRATE         9600
  48 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  49
  50 #undef  CONFIG_BOOTARGS
  51 #undef  CONFIG_BOOTCOMMAND
  52
  53 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  54
  55 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  56
  57 #undef  CONFIG_HAS_ETH1
  58
  59 #define CONFIG_PPC4xx_EMAC
  60 #define CONFIG_MII              1       /* MII PHY management           */
  61 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  62 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  63 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  64
  65 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  66
  67
  68 /*
  69  * BOOTP options
  70  */
  71 #define CONFIG_BOOTP_BOOTFILESIZE
  72 #define CONFIG_BOOTP_BOOTPATH
  73 #define CONFIG_BOOTP_GATEWAY
  74 #define CONFIG_BOOTP_HOSTNAME
  75
  76
  77 /*
  78  * Command line configuration.
  79  */
  80 #include <config_cmd_default.h>
  81
  82 #define CONFIG_CMD_DHCP
  83 #define CONFIG_CMD_PCI
  84 #define CONFIG_CMD_IRQ
  85 #define CONFIG_CMD_IDE
  86 #define CONFIG_CMD_FAT
  87 #define CONFIG_CMD_ELF
  88 #define CONFIG_CMD_NAND
  89 #define CONFIG_CMD_DATE
  90 #define CONFIG_CMD_I2C
  91 #define CONFIG_CMD_MII
  92 #define CONFIG_CMD_PING
  93 #define CONFIG_CMD_EEPROM
  94
  95
  96 #define CONFIG_MAC_PARTITION
  97 #define CONFIG_DOS_PARTITION
  98
  99 #define CONFIG_SUPPORT_VFAT
 100
 101 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 102
 103 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
 104 #define CONFIG_SYS_RTC_REG_BASE_ADDR     0xF0000500 /* RTC Base Address         */
 105
 106 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 107
 108 /*
 109  * Miscellaneous configurable options
 110  */
 111 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 112 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 113
 114 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
 115
 116 #if defined(CONFIG_CMD_KGDB)
 117 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 118 #else
 119 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 120 #endif
 121 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 122 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 123 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 124
 125 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 126
 127 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 128
 129 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 130
 131 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 132 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 133
 134 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
 135 #define CONFIG_SYS_NS16550
 136 #define CONFIG_SYS_NS16550_SERIAL
 137 #define CONFIG_SYS_NS16550_REG_SIZE     1
 138 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 139
 140 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* no external serial clock used */
 141 #define CONFIG_SYS_BASE_BAUD       691200
 142
 143 /* The following table includes the supported baudrates */
 144 #define CONFIG_SYS_BAUDRATE_TABLE       \
 145         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 146          57600, 115200, 230400, 460800, 921600 }
 147
 148 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 149 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 150
 151 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 152
 153 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 154
 155 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 156
 157 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 158
 159 /*-----------------------------------------------------------------------
 160  * NAND-FLASH stuff
 161  *-----------------------------------------------------------------------
 162  */
 163 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 164 #define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
 165 #define NAND_BIG_DELAY_US       25
 166
 167 #define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
 168 #define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
 169 #define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 170 #define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 171
 172 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
 173 #define CONFIG_SYS_NAND_QUIET          1
 174
 175 /*-----------------------------------------------------------------------
 176  * PCI stuff
 177  *-----------------------------------------------------------------------
 178  */
 179 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 180 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 181 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 182
 183 #define CONFIG_PCI                      /* include pci support          */
 184 #define CONFIG_PCI_HOST PCI_HOST_HOST   /* select pci host function     */
 185 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 186                                         /* resource configuration       */
 187
 188 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 189
 190 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 191
 192 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 193 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 194 #define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 195 #define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
 196 #define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 197 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 198 #define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
 199 #define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 200 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 201
 202 /*-----------------------------------------------------------------------
 203  * IDE/ATA stuff
 204  *-----------------------------------------------------------------------
 205  */
 206 #undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
 207 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 208 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 209
 210 #define CONFIG_SYS_IDE_MAXBUS           2               /* max. 2 IDE busses    */
 211 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 212
 213 #define CONFIG_SYS_ATA_BASE_ADDR        0xF0100000
 214 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 215 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0010
 216
 217 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O                  */
 218 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* Offset for normal register accesses  */
 219 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0000  /* Offset for alternate registers       */
 220
 221 /*
 222  * For booting Linux, the board info and command line data
 223  * have to be in the first 8 MB of memory, since this is
 224  * the maximum mapped by the Linux kernel during initialization.
 225  */
 226 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 227 /*-----------------------------------------------------------------------
 228  * FLASH organization
 229  */
 230 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 231
 232 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 233 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 234
 235 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 236 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 237
 238 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 239 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 240 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 241 /*
 242  * The following defines are added for buggy IOP480 byte interface.
 243  * All other boards should use the standard values (CPCI405 etc.)
 244  */
 245 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 246 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 247 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 248
 249 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 250
 251 /*-----------------------------------------------------------------------
 252  * Start addresses for the final memory configuration
 253  * (Set up by the startup code)
 254  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 255  */
 256 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 257 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 258 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 259 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Monitor   */
 260 #define CONFIG_SYS_MALLOC_LEN           (2 * 1024*1024) /* Reserve 2 MB for malloc()    */
 261
 262 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 263 # define CONFIG_SYS_RAMBOOT             1
 264 #else
 265 # undef CONFIG_SYS_RAMBOOT
 266 #endif
 267
 268 /*-----------------------------------------------------------------------
 269  * Environment Variable setup
 270  */
 271 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 272 #define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 273 #define CONFIG_ENV_SIZE         0x700   /* 2048 bytes may be used for env vars*/
 274                                    /* total size of a CAT24WC16 is 2048 bytes */
 275
 276 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xF0000500              /* NVRAM base address   */
 277 #define CONFIG_SYS_NVRAM_SIZE           242                     /* NVRAM size           */
 278
 279 /*-----------------------------------------------------------------------
 280  * I2C EEPROM (CAT24WC16) for environment
 281  */
 282 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 283 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 284 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address */
 285 #define CONFIG_SYS_I2C_SLAVE            0x7F
 286
 287 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT24WC08             */
 288 #define CONFIG_SYS_EEPROM_WREN         1
 289
 290 /* CAT24WC32/64... */
 291 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2        /* Bytes of address             */
 292 /* mask of address bits that overflow into the "EEPROM chip address"    */
 293 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x01
 294 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5     /* The Catalyst CAT24WC32 has   */
 295                                         /* 32 byte page write mode using*/
 296                                         /* last 5 bits of the address   */
 297 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 298
 299 /*-----------------------------------------------------------------------
 300  * External Bus Controller (EBC) Setup
 301  */
 302
 303 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 304 #define DUART0_BA       0xF0000400          /* DUART Base Address               */
 305 #define DUART1_BA       0xF0000408          /* DUART Base Address               */
 306 #define RTC_BA          0xF0000500          /* RTC Base Address                 */
 307 #define VGA_BA          0xF1000000          /* Epson VGA Base Address           */
 308 #define CONFIG_SYS_NAND_BASE    0xF4000000          /* NAND FLASH Base Address          */
 309
 310 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 311 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 312 /*#define CONFIG_SYS_EBC_PB0AP            0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
 313 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 314
 315 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
 316 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 317 #define CONFIG_SYS_EBC_PB1CR            0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
 318
 319 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 320 #define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 321 #define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 322
 323 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
 324 #define CONFIG_SYS_EBC_PB3AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 325 #define CONFIG_SYS_EBC_PB3CR            0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 326
 327 /* Memory Bank 4 (Epson VGA) initialization                                     */
 328 #define CONFIG_SYS_EBC_PB4AP    0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
 329 #define CONFIG_SYS_EBC_PB4CR    VGA_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
 330
 331 /*-----------------------------------------------------------------------
 332  * LCD Setup
 333  */
 334
 335 #define CONFIG_SYS_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
 336 #define CONFIG_SYS_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
 337 #define CONFIG_SYS_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
 338 #define CONFIG_SYS_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
 339
 340 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
 341
 342 /*-----------------------------------------------------------------------
 343  * FPGA stuff
 344  */
 345
 346 #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100        /* FPGA internal Base Address       */
 347
 348 /* FPGA internal regs */
 349 #define CONFIG_SYS_FPGA_CTRL            0x000
 350
 351 /* FPGA Control Reg */
 352 #define CONFIG_SYS_FPGA_CTRL_CF_RESET   0x0001
 353 #define CONFIG_SYS_FPGA_CTRL_WDI        0x0002
 354 #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
 355
 356 #define CONFIG_SYS_FPGA_SPARTAN2        1           /* using Xilinx Spartan 2 now    */
 357 #define CONFIG_SYS_FPGA_MAX_SIZE        128*1024    /* 128kByte is enough for XC2S50E*/
 358
 359 /* FPGA program pin configuration */
 360 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* FPGA program pin (ppc output) */
 361 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* FPGA clk pin (ppc output)     */
 362 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* FPGA data pin (ppc output)    */
 363 #define CONFIG_SYS_FPGA_INIT            0x00010000  /* FPGA init pin (ppc input)     */
 364 #define CONFIG_SYS_FPGA_DONE            0x00008000  /* FPGA done pin (ppc input)     */
 365
 366 /*-----------------------------------------------------------------------
 367  * Definitions for initial stack pointer and data area (in data cache)
 368  */
 369 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 370 #define CONFIG_SYS_TEMP_STACK_OCM         1
 371
 372 /* On Chip Memory location */
 373 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 374 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 375 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 376 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 377
 378 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 379 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 380
 381 /*-----------------------------------------------------------------------
 382  * Definitions for GPIO setup (PPC405EP specific)
 383  *
 384  * GPIO0[0]     - External Bus Controller BLAST output
 385  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 386  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 387  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 388  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 389  * GPIO0[24-27] - UART0 control signal inputs/outputs
 390  * GPIO0[28-29] - UART1 data signal input/output
 391  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
 392  */
 393 #define CONFIG_SYS_GPIO0_OSRL           0x00000550
 394 #define CONFIG_SYS_GPIO0_OSRH           0x00000110
 395 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000
 396 #define CONFIG_SYS_GPIO0_ISR1H          0x15555440
 397 #define CONFIG_SYS_GPIO0_TSRL           0x00000000
 398 #define CONFIG_SYS_GPIO0_TSRH           0x00000000
 399 #define CONFIG_SYS_GPIO0_TCR            0x777E0017
 400
 401 #define CONFIG_SYS_DUART_RST            (0x80000000 >> 14)
 402 #define CONFIG_SYS_LCD_ENDIAN           (0x80000000 >> 7)
 403 #define CONFIG_SYS_IIC_ON               (0x80000000 >> 8)
 404 #define CONFIG_SYS_LCD0_RST             (0x80000000 >> 30)
 405 #define CONFIG_SYS_LCD1_RST             (0x80000000 >> 31)
 406 #define CONFIG_SYS_EEPROM_WP            (0x80000000 >> 0)
 407
 408 /*
 409  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 410  * This value will be set if iic boot eprom is disabled.
 411  */
 412 #if 1
 413 #define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 414 #define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
 415 #endif
 416 #if 0
 417 #define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
 418 #define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
 419 #endif
 420 #if 0
 421 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 422 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 423 #endif
 424
 425 #endif  /* __CONFIG_H */