include/configs/W7OLMC.h

   1 /*
   2  * (C) Copyright 2001
   3  * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405GP            1               /* This is a PPC405GP CPU       */
  21 #define CONFIG_4xx              1               /* ...member of PPC405 family   */
  22 #define CONFIG_W7O              1               /* ...on a Wave 7 Optics board  */
  23 #define CONFIG_W7OLMC           1               /* ...specifically an LMC       */
  24
  25 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  26
  27 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f      */
  28 #define CONFIG_MISC_INIT_F      1               /* and misc_init_f()            */
  29 #define CONFIG_MISC_INIT_R      1               /* and misc_init_r()            */
  30
  31 #define CONFIG_SYS_CLK_FREQ     33333333        /* external frequency to pll    */
  32
  33 #define CONFIG_BAUDRATE         9600
  34 #define CONFIG_BOOTDELAY        3               /* autoboot after 3 seconds     */
  35
  36 #if 1
  37 #define CONFIG_BOOTCOMMAND      "bootvx"        /* VxWorks boot command         */
  38 #else
  39 #define CONFIG_BOOTCOMMAND      "bootp"         /* autoboot command             */
  40 #endif
  41
  42 #undef CONFIG_BOOTARGS
  43
  44 #define CONFIG_LOADADDR         F0080000
  45
  46 #define CONFIG_ETHADDR          00:06:0D:00:00:00 /* Default, overridden at boot        */
  47 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  48 #define CONFIG_IPADDR           192.168.1.1
  49 #define CONFIG_NETMASK          255.255.255.0
  50 #define CONFIG_SERVERIP         192.168.1.2
  51
  52 #define CONFIG_LOADS_ECHO       1               /* echo on for serial download  */
  53 #undef CONFIG_SYS_LOADS_BAUD_CHANGE                     /* disallow baudrate change     */
  54
  55 #define CONFIG_PPC4xx_EMAC
  56 #define CONFIG_MII              1               /* MII PHY management           */
  57 #define CONFIG_PHY_ADDR         0               /* PHY address                  */
  58
  59 #define CONFIG_RTC_M48T35A      1               /* ST Electronics M48 timekeeper */
  60
  61 /*
  62  * BOOTP options
  63  */
  64 #define CONFIG_BOOTP_BOOTFILESIZE
  65 #define CONFIG_BOOTP_BOOTPATH
  66 #define CONFIG_BOOTP_GATEWAY
  67 #define CONFIG_BOOTP_HOSTNAME
  68
  69
  70 /*
  71  * Command line configuration.
  72  */
  73 #include <config_cmd_default.h>
  74
  75 #define CONFIG_CMD_PCI
  76 #define CONFIG_CMD_IRQ
  77 #define CONFIG_CMD_ASKENV
  78 #define CONFIG_CMD_DHCP
  79 #define CONFIG_CMD_BEDBUG
  80 #define CONFIG_CMD_DATE
  81 #define CONFIG_CMD_I2C
  82 #define CONFIG_CMD_EEPROM
  83 #define CONFIG_CMD_ELF
  84 #define CONFIG_CMD_BSP
  85 #define CONFIG_CMD_REGINFO
  86
  87 #undef CONFIG_WATCHDOG                          /* watchdog disabled            */
  88 #define CONFIG_HW_WATCHDOG                      /* HW Watchdog, board specific  */
  89
  90 #define CONFIG_SPD_EEPROM                       /* SPD EEPROM for SDRAM param.  */
  91 #define CONFIG_SPDDRAM_SILENT                   /* No output if spd fails       */
  92 /*
  93  * Miscellaneous configurable options
  94  */
  95 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
  96 #define CONFIG_SYS_PROMPT               "Wave7Optics> " /* Monitor Command Prompt       */
  97 #undef  CONFIG_SYS_HUSH_PARSER                          /* No hush parse for U-Boot       */
  98 #ifdef  CONFIG_SYS_HUSH_PARSER
  99 #endif
 100 #if defined(CONFIG_CMD_KGDB)
 101 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
 102 #else
 103 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 104 #endif
 105 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 106 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 107 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 108
 109 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on             */
 110 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM          */
 111
 112 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 113 #define CONFIG_SYS_NS16550
 114 #define CONFIG_SYS_NS16550_SERIAL
 115 #define CONFIG_SYS_NS16550_REG_SIZE     1
 116 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 117
 118 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK                     /* external serial clock */
 119 #define CONFIG_SYS_405_UART_ERRATA_59                   /* 405GP/CR Rev. D silicon */
 120 #define CONFIG_SYS_BASE_BAUD            384000
 121
 122
 123 /* The following table includes the supported baudrates */
 124 #define CONFIG_SYS_BAUDRATE_TABLE       {9600}
 125
 126 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address         */
 127 #define CONFIG_SYS_EXTBDINFO            1               /* use extended board_info (bd_t) */
 128
 129 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1 ms ticks */
 130
 131 /*-----------------------------------------------------------------------
 132  * PCI stuff
 133  *-----------------------------------------------------------------------
 134  */
 135 #define PCI_HOST_ADAPTER        0               /* configure as pci adapter     */
 136 #define PCI_HOST_FORCE          1               /* configure as pci host        */
 137 #define PCI_HOST_AUTO           2               /* detected via arbiter enable  */
 138
 139
 140 #define CONFIG_PCI                              /* include pci support          */
 141 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 142 #define CONFIG_PCI_HOST         PCI_HOST_AUTO   /* select pci host function     */
 143 #define CONFIG_PCI_PNP                          /* pci plug-and-play            */
 144 /* resource configuration       */
 145 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014           /* PCI Vendor ID: IBM           */
 146 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156           /* PCI Device ID: 405GP         */
 147 #define CONFIG_SYS_PCI_PTM1LA           0x00000000      /* point to sdram               */
 148 #define CONFIG_SYS_PCI_PTM1MS           0x80000001      /* 2GB, enable hard-wired to 1  */
 149 #define CONFIG_SYS_PCI_PTM1PCI          0x00000000      /* Host: use this pci address   */
 150 #define CONFIG_SYS_PCI_PTM2LA           0x00000000      /* disabled                     */
 151 #define CONFIG_SYS_PCI_PTM2MS           0x00000000      /* disabled                     */
 152 #define CONFIG_SYS_PCI_PTM2PCI          0x00000000      /* Host: use this pci address   */
 153
 154 /*-----------------------------------------------------------------------
 155  * Set up values for external bus controller
 156  * used by cpu_init.c
 157  *-----------------------------------------------------------------------
 158  */
 159  /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
 160 #undef CONFIG_USE_PERWE
 161
 162 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 163 #define CONFIG_SYS_TEMP_STACK_OCM        1
 164
 165 /* bank 0 is boot flash */
 166 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
 167 #define CONFIG_SYS_W7O_EBC_PB0AP   0x03050440
 168 /* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
 169 #define CONFIG_SYS_W7O_EBC_PB0CR   0xFFE38000
 170
 171 /* bank 1 is main flash */
 172 /* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
 173 #define CONFIG_SYS_EBC_PB1AP   0x05850240
 174 /* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
 175 #define CONFIG_SYS_EBC_PB1CR   0xF00FC000
 176
 177 /* bank 2 is RTC/NVRAM */
 178 /* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
 179 #define CONFIG_SYS_EBC_PB2AP   0x03000440
 180 /* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
 181 #define CONFIG_SYS_EBC_PB2CR   0xFC018000
 182
 183 /* bank 3 is FPGA 0 */
 184 /* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
 185 #define CONFIG_SYS_EBC_PB3AP   0x02000400
 186 /* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
 187 #define CONFIG_SYS_EBC_PB3CR   0xFD01A000
 188
 189 /* bank 4 is FPGA 1 */
 190 /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
 191 #define CONFIG_SYS_EBC_PB4AP   0x02000400
 192 /* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
 193 #define CONFIG_SYS_EBC_PB4CR   0xFD11A000
 194
 195 /* bank 5 is FPGA 2 */
 196 /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
 197 #define CONFIG_SYS_EBC_PB5AP   0x02000400
 198 /* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
 199 #define CONFIG_SYS_EBC_PB5CR   0xFD21A000
 200
 201 /* bank 6 is unused */
 202 /* PB6AP = 0 */
 203 #define CONFIG_SYS_EBC_PB6AP   0x00000000
 204 /* PB6CR = 0 */
 205 #define CONFIG_SYS_EBC_PB6CR   0x00000000
 206
 207 /* bank 7 is LED register */
 208 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
 209 #define CONFIG_SYS_W7O_EBC_PB7AP   0x03050440
 210 /* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
 211 #define CONFIG_SYS_W7O_EBC_PB7CR   0xFE01C000
 212
 213 /*-----------------------------------------------------------------------
 214  * Start addresses for the final memory configuration
 215  * (Set up by the startup code)
 216  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 217  */
 218 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 219 #define CONFIG_SYS_FLASH_BASE           0xFFFC0000
 220 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 221 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 222 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 223
 224 /*
 225  * For booting Linux, the board info and command line data
 226  * have to be in the first 8 MB of memory, since this is
 227  * the maximum mapped by the Linux kernel during initialization.
 228  */
 229 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 230 /*-----------------------------------------------------------------------
 231  * FLASH organization
 232  */
 233 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* max number of memory banks   */
 234 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max number of sec on 1 chip  */
 235
 236 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000          /* Timeout, Flash Erase, in ms  */
 237 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Timeout, Flash Write, in ms  */
 238 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use real Flash protection    */
 239
 240 #if 1 /* Use NVRAM for environment variables */
 241 /*-----------------------------------------------------------------------
 242  * NVRAM organization
 243  */
 244 #define CONFIG_ENV_IS_IN_NVRAM  1               /* use NVRAM for env vars       */
 245 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xfc000000      /* NVRAM base address           */
 246 #define CONFIG_SYS_NVRAM_SIZE           (32*1024)       /* NVRAM size                   */
 247 #define CONFIG_ENV_SIZE         0x1000          /* Size of Environment vars     */
 248 /*define CONFIG_ENV_ADDR                 \
 249         (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env  */
 250 #define CONFIG_ENV_ADDR         CONFIG_SYS_NVRAM_BASE_ADDR
 251
 252 #else /* Use Boot Flash for environment variables */
 253 /*-----------------------------------------------------------------------
 254  * Flash EEPROM for environment
 255  */
 256 #define CONFIG_ENV_IS_IN_FLASH 1
 257 #define CONFIG_ENV_OFFSET               0x00040000      /* Offset of Environment Sector */
 258 #define CONFIG_ENV_SIZE         0x10000         /* Total Size of env. sector    */
 259
 260 #define CONFIG_ENV_SECT_SIZE    0x10000         /* see README - env sec tot sze */
 261 #endif
 262
 263 /*-----------------------------------------------------------------------
 264  * I2C EEPROM (CAT24WC08) for environment
 265  */
 266 #define CONFIG_SYS_I2C
 267 #define CONFIG_SYS_I2C_PPC4XX
 268 #define CONFIG_SYS_I2C_PPC4XX_CH0
 269 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 270 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 271
 272 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 273 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address             */
 274 /* mask of address bits that overflow into the "EEPROM chip address"    */
 275 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 276 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 277                                         /* 16 byte page write mode using*/
 278                                         /* last 4 bits of the address   */
 279 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 280 /*-----------------------------------------------------------------------
 281  * Definitions for Serial Presence Detect EEPROM address
 282  * (to get SDRAM settings)
 283  */
 284 #define SPD_EEPROM_ADDRESS      0x50    /* XXX conflicting address!!! XXX */
 285
 286 /*
 287  * Init Memory Controller:
 288  */
 289 #define FLASH_BASE0_PRELIM      0xFFE00000      /* FLASH bank #0                */
 290 #define FLASH_BASE1_PRELIM      0xF0000000      /* FLASH bank #1                */
 291
 292 /* On Chip Memory location */
 293 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 294 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 295
 296 /*-----------------------------------------------------------------------
 297  * Definitions for initial stack pointer and data area (in RAM)
 298  */
 299 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 300 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 301 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 302 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 303
 304 #if defined(CONFIG_CMD_KGDB)
 305 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 306 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use     */
 307 #endif
 308
 309 /*
 310  * FPGA(s) configuration
 311  */
 312 #define CONFIG_SYS_FPGA_IMAGE_LEN       0x80000         /* 512KB FPGA image             */
 313 #define CONFIG_NUM_FPGAS        3               /* Number of FPGAs on board     */
 314 #define CONFIG_MAX_FPGAS        6               /* Maximum number of FPGAs      */
 315 #define CONFIG_FPGAS_BASE       0xFD000000L     /* Base address of FPGAs        */
 316 #define CONFIG_FPGAS_BANK_SIZE  0x00100000L     /* FPGAs' mmap bank size        */
 317
 318 #endif  /* __CONFIG_H */