include/configs/W7OLMC.h

   1 /*
   2  * (C) Copyright 2001
   3  * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405GP            1               /* This is a PPC405GP CPU       */
  37 #define CONFIG_4xx              1               /* ...member of PPC405 family   */
  38 #define CONFIG_W7O              1               /* ...on a Wave 7 Optics board  */
  39 #define CONFIG_W7OLMC           1               /* ...specifically an LMC       */
  40
  41 #define CONFIG_BOARD_PRE_INIT   1               /* Call board_pre_init  */
  42
  43 #define CONFIG_SYS_CLK_FREQ     33333333        /* external frequency to pll    */
  44
  45 #define CONFIG_BAUDRATE         9600
  46 #define CONFIG_BOOTDELAY        3               /* autoboot after 3 seconds     */
  47
  48 #if 1
  49 #define CONFIG_BOOTCOMMAND      "bootvx"        /* VxWorks boot command         */
  50 #else
  51 #define CONFIG_BOOTCOMMAND      "bootp"         /* autoboot command             */
  52 #endif
  53
  54 #undef CONFIG_BOOTARGS
  55
  56 #define CONFIG_LOADADDR         F0080000
  57
  58 #define CONFIG_ETHADDR          00:06:0D:00:00:00 /* Default, overridden at boot        */
  59 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  60 #define CONFIG_IPADDR           192.168.1.1
  61 #define CONFIG_NETMASK          255.255.255.0
  62 #define CONFIG_SERVERIP         192.168.1.2
  63
  64 #define CONFIG_LOADS_ECHO       1               /* echo on for serial download  */
  65 #undef CFG_LOADS_BAUD_CHANGE                    /* disallow baudrate change     */
  66
  67 #define CONFIG_MII              1               /* MII PHY management           */
  68 #define CONFIG_PHY_ADDR         0               /* PHY address                  */
  69
  70 #define CONFIG_RTC_M48T35A      1               /* ST Electronics M48 timekeeper */
  71
  72 #define CONFIG_COMMANDS         \
  73         (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
  74          CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
  75          CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO)
  76
  77 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  78 #include <cmd_confdefs.h>
  79
  80 #undef CONFIG_WATCHDOG                          /* watchdog disabled            */
  81 #define CONFIG_HW_WATCHDOG                      /* HW Watchdog, board specific  */
  82
  83 #define CONFIG_SPD_EEPROM                       /* SPD EEPROM for SDRAM param.  */
  84 #define CONFIG_SPDDRAM_SILENT                   /* No output if spd fails       */
  85 /*
  86  * Miscellaneous configurable options
  87  */
  88 #define CFG_LONGHELP                            /* undef to save memory         */
  89 #define CFG_PROMPT              "Wave7Optics> " /* Monitor Command Prompt       */
  90 #undef  CFG_HUSH_PARSER                         /* No hush parse for U-Boot       */
  91 #ifdef  CFG_HUSH_PARSER
  92 #define CFG_PROMPT_HUSH_PS2     "> "
  93 #endif
  94 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  95 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size      */
  96 #else
  97 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
  98 #endif
  99 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size      */
 100 #define CFG_MAXARGS             16              /* max number of command args   */
 101 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 102
 103 #define CFG_MEMTEST_START       0x0400000       /* memtest works on             */
 104 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM          */
 105
 106 #undef  CFG_EXT_SERIAL_CLOCK                    /* external serial clock */
 107 #define CFG_405_UART_ERRATA_59                  /* 405GP/CR Rev. D silicon */
 108 #define CFG_BASE_BAUD           384000
 109
 110
 111 /* The following table includes the supported baudrates */
 112 #define CFG_BAUDRATE_TABLE      {9600}
 113
 114 #define CFG_CLKS_IN_HZ          1               /* everything, incl board info, in Hz */
 115
 116 #define CFG_LOAD_ADDR           0x100000        /* default load address         */
 117 #define CFG_EXTBDINFO           1               /* use extended board_info (bd_t) */
 118
 119 #define CFG_HZ                  1000            /* decrementer freq: 1 ms ticks */
 120
 121 /*-----------------------------------------------------------------------
 122  * PCI stuff
 123  *-----------------------------------------------------------------------
 124  */
 125 #define PCI_HOST_ADAPTER        0               /* configure as pci adapter     */
 126 #define PCI_HOST_FORCE          1               /* configure as pci host        */
 127 #define PCI_HOST_AUTO           2               /* detected via arbiter enable  */
 128
 129
 130 #define CONFIG_PCI                              /* include pci support          */
 131 #define CONFIG_PCI_HOST         PCI_HOST_AUTO   /* select pci host function     */
 132 #define CONFIG_PCI_PNP                          /* pci plug-and-play            */
 133 /* resource configuration       */
 134 #define CFG_PCI_SUBSYS_VENDORID 0x1014          /* PCI Vendor ID: IBM           */
 135 #define CFG_PCI_SUBSYS_DEVICEID 0x0156          /* PCI Device ID: 405GP         */
 136 #define CFG_PCI_PTM1LA          0x00000000      /* point to sdram               */
 137 #define CFG_PCI_PTM1MS          0x80000001      /* 2GB, enable hard-wired to 1  */
 138 #define CFG_PCI_PTM1PCI         0x00000000      /* Host: use this pci address   */
 139 #define CFG_PCI_PTM2LA          0x00000000      /* disabled             */
 140 #define CFG_PCI_PTM2MS          0x00000000      /* disabled             */
 141 #define CFG_PCI_PTM2PCI         0x00000000      /* Host: use this pci address   */
 142
 143 /*-----------------------------------------------------------------------
 144  * Set up values for external bus controller
 145  * used by cpu_init.c
 146  *-----------------------------------------------------------------------
 147  */
 148  /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
 149 #undef CONFIG_USE_PERWE
 150
 151 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 152 #define CFG_TEMP_STACK_OCM        1
 153
 154 /* bank 0 is boot flash */
 155 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
 156 #define CFG_W7O_EBC_PB0AP   0x03050440
 157 /* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
 158 #define CFG_W7O_EBC_PB0CR   0xFFE38000
 159
 160 /* bank 1 is main flash */
 161 /* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
 162 #define CFG_EBC_PB1AP   0x05850240
 163 /* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
 164 #define CFG_EBC_PB1CR   0xF00FC000
 165
 166 /* bank 2 is RTC/NVRAM */
 167 /* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
 168 #define CFG_EBC_PB2AP   0x03000440
 169 /* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
 170 #define CFG_EBC_PB2CR   0xFC018000
 171
 172 /* bank 3 is FPGA 0 */
 173 /* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
 174 #define CFG_EBC_PB3AP   0x02000400
 175 /* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
 176 #define CFG_EBC_PB3CR   0xFD01A000
 177
 178 /* bank 4 is FPGA 1 */
 179 /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
 180 #define CFG_EBC_PB4AP   0x02000400
 181 /* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
 182 #define CFG_EBC_PB4CR   0xFD11A000
 183
 184 /* bank 5 is FPGA 2 */
 185 /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
 186 #define CFG_EBC_PB5AP   0x02000400
 187 /* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
 188 #define CFG_EBC_PB5CR   0xFD21A000
 189
 190 /* bank 6 is unused */
 191 /* pb6ap = 0 */
 192 #define CFG_EBC_PB6AP   0x00000000
 193 /* pb6cr = 0 */
 194 #define CFG_EBC_PB6CR   0x00000000
 195
 196 /* bank 7 is LED register */
 197 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
 198 #define CFG_W7O_EBC_PB7AP   0x03050440
 199 /* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
 200 #define CFG_W7O_EBC_PB7CR   0xFE01C000
 201
 202 /*-----------------------------------------------------------------------
 203  * Start addresses for the final memory configuration
 204  * (Set up by the startup code)
 205  * Please note that CFG_SDRAM_BASE _must_ start at 0
 206  */
 207 #define CFG_SDRAM_BASE          0x00000000
 208 #define CFG_FLASH_BASE          0xFFFC0000
 209 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 210 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
 211 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 212
 213 /*
 214  * For booting Linux, the board info and command line data
 215  * have to be in the first 8 MB of memory, since this is
 216  * the maximum mapped by the Linux kernel during initialization.
 217  */
 218 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 219 /*-----------------------------------------------------------------------
 220  * FLASH organization
 221  */
 222 #define CFG_MAX_FLASH_BANKS     2               /* max number of memory banks   */
 223 #define CFG_MAX_FLASH_SECT      256             /* max number of sec on 1 chip  */
 224
 225 #define CFG_FLASH_ERASE_TOUT    120000          /* Timeout, Flash Erase, in ms  */
 226 #define CFG_FLASH_WRITE_TOUT    500             /* Timeout, Flash Write, in ms  */
 227 #define CFG_FLASH_PROTECTION    1               /* Use real Flash protection    */
 228
 229 #if 1 /* Use NVRAM for environment variables */
 230 /*-----------------------------------------------------------------------
 231  * NVRAM organization
 232  */
 233 #define CFG_ENV_IS_IN_NVRAM     1               /* use NVRAM for env vars       */
 234 #define CFG_NVRAM_BASE_ADDR     0xfc000000      /* NVRAM base address           */
 235 #define CFG_NVRAM_SIZE          (32*1024)       /* NVRAM size                   */
 236 #define CFG_ENV_SIZE            0x1000          /* Size of Environment vars     */
 237 /*define CFG_ENV_ADDR            \
 238         (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env  */
 239 #define CFG_ENV_ADDR            CFG_NVRAM_BASE_ADDR
 240
 241 #else /* Use Boot Flash for environment variables */
 242 /*-----------------------------------------------------------------------
 243  * Flash EEPROM for environment
 244  */
 245 #define CFG_ENV_IS_IN_FLASH 1
 246 #define CFG_ENV_OFFSET          0x00040000      /* Offset of Environment Sector */
 247 #define CFG_ENV_SIZE            0x10000         /* Total Size of env. sector    */
 248
 249 #define CFG_ENV_SECT_SIZE       0x10000         /* see README - env sec tot sze */
 250 #endif
 251
 252 /*-----------------------------------------------------------------------
 253  * I2C EEPROM (CAT24WC08) for environment
 254  */
 255 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 256 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 257 #define CFG_I2C_SLAVE           0x7F
 258
 259 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08             */
 260 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 261 /* mask of address bits that overflow into the "EEPROM chip address"    */
 262 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 263 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 264 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 265                                         /* 16 byte page write mode using*/
 266                                         /* last 4 bits of the address   */
 267 #define CFG_I2C_MULTI_EEPROMS
 268 /*-----------------------------------------------------------------------
 269  * Definitions for Serial Presence Detect EEPROM address
 270  * (to get SDRAM settings)
 271  */
 272 #define SPD_EEPROM_ADDRESS      0x50    /* XXX conflicting address!!! XXX */
 273
 274 /*-----------------------------------------------------------------------
 275  * Cache Configuration
 276  */
 277 #define CFG_DCACHE_SIZE         8192            /* For IBM 405 CPUs                     */
 278 #define CFG_CACHELINE_SIZE      32              /* ...          */
 279 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 280 #define CFG_CACHELINE_SHIFT     5               /* log base 2 of the above val. */
 281 #endif
 282
 283 /*
 284  * Init Memory Controller:
 285  */
 286 #define FLASH_BASE0_PRELIM      0xFFE00000      /* FLASH bank #0                */
 287 #define FLASH_BASE1_PRELIM      0xF0000000      /* FLASH bank #1                */
 288
 289 /* On Chip Memory location */
 290 #define CFG_OCM_DATA_ADDR       0xF8000000
 291 #define CFG_OCM_DATA_SIZE       0x1000
 292
 293 /*-----------------------------------------------------------------------
 294  * Definitions for initial stack pointer and data area (in RAM)
 295  */
 296 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of SDRAM            */
 297 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM    */
 298 #define CFG_GBL_DATA_SIZE       64              /* size in bytes reserved for initial data */
 299 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 300 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 301
 302
 303 /*
 304  * Internal Definitions
 305  *
 306  * Boot Flags
 307  */
 308 #define BOOTFLAG_COLD           0x01            /* Normal Power-On: Boot from FLASH */
 309 #define BOOTFLAG_WARM           0x02            /* Software reboot              */
 310
 311 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 312 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 313 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use     */
 314 #endif
 315
 316 /*
 317  * FPGA(s) configuration
 318  */
 319 #define CFG_FPGA_IMAGE_LEN      0x80000         /* 512KB FPGA image             */
 320 #define CONFIG_NUM_FPGAS        3               /* Number of FPGAs on board     */
 321 #define CONFIG_MAX_FPGAS        6               /* Maximum number of FPGAs      */
 322 #define CONFIG_FPGAS_BASE       0xFD000000L     /* Base address of FPGAs        */
 323 #define CONFIG_FPGAS_BANK_SIZE  0x00100000L     /* FPGAs' mmap bank size        */
 324
 325 #endif  /* __CONFIG_H */