include/configs/W7OLMC.h

   1 /*
   2  * (C) Copyright 2001
   3  * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405GP            1               /* This is a PPC405GP CPU       */
  37 #define CONFIG_4xx              1               /* ...member of PPC405 family   */
  38 #define CONFIG_W7O              1               /* ...on a Wave 7 Optics board  */
  39 #define CONFIG_W7OLMC           1               /* ...specifically an LMC       */
  40
  41 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f      */
  42 #define CONFIG_MISC_INIT_F      1               /* and misc_init_f()            */
  43 #define CONFIG_MISC_INIT_R      1               /* and misc_init_r()            */
  44
  45 #define CONFIG_SYS_CLK_FREQ     33333333        /* external frequency to pll    */
  46
  47 #define CONFIG_BAUDRATE         9600
  48 #define CONFIG_BOOTDELAY        3               /* autoboot after 3 seconds     */
  49
  50 #if 1
  51 #define CONFIG_BOOTCOMMAND      "bootvx"        /* VxWorks boot command         */
  52 #else
  53 #define CONFIG_BOOTCOMMAND      "bootp"         /* autoboot command             */
  54 #endif
  55
  56 #undef CONFIG_BOOTARGS
  57
  58 #define CONFIG_LOADADDR         F0080000
  59
  60 #define CONFIG_ETHADDR          00:06:0D:00:00:00 /* Default, overridden at boot        */
  61 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  62 #define CONFIG_IPADDR           192.168.1.1
  63 #define CONFIG_NETMASK          255.255.255.0
  64 #define CONFIG_SERVERIP         192.168.1.2
  65
  66 #define CONFIG_LOADS_ECHO       1               /* echo on for serial download  */
  67 #undef CONFIG_SYS_LOADS_BAUD_CHANGE                     /* disallow baudrate change     */
  68
  69 #define CONFIG_PPC4xx_EMAC
  70 #define CONFIG_MII              1               /* MII PHY management           */
  71 #define CONFIG_PHY_ADDR         0               /* PHY address                  */
  72 #define CONFIG_NET_MULTI
  73
  74 #define CONFIG_RTC_M48T35A      1               /* ST Electronics M48 timekeeper */
  75
  76 /*
  77  * BOOTP options
  78  */
  79 #define CONFIG_BOOTP_BOOTFILESIZE
  80 #define CONFIG_BOOTP_BOOTPATH
  81 #define CONFIG_BOOTP_GATEWAY
  82 #define CONFIG_BOOTP_HOSTNAME
  83
  84
  85 /*
  86  * Command line configuration.
  87  */
  88 #include <config_cmd_default.h>
  89
  90 #define CONFIG_CMD_PCI
  91 #define CONFIG_CMD_IRQ
  92 #define CONFIG_CMD_ASKENV
  93 #define CONFIG_CMD_DHCP
  94 #define CONFIG_CMD_BEDBUG
  95 #define CONFIG_CMD_DATE
  96 #define CONFIG_CMD_I2C
  97 #define CONFIG_CMD_EEPROM
  98 #define CONFIG_CMD_ELF
  99 #define CONFIG_CMD_BSP
 100 #define CONFIG_CMD_REGINFO
 101
 102 #undef CONFIG_WATCHDOG                          /* watchdog disabled            */
 103 #define CONFIG_HW_WATCHDOG                      /* HW Watchdog, board specific  */
 104
 105 #define CONFIG_SPD_EEPROM                       /* SPD EEPROM for SDRAM param.  */
 106 #define CONFIG_SPDDRAM_SILENT                   /* No output if spd fails       */
 107 /*
 108  * Miscellaneous configurable options
 109  */
 110 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
 111 #define CONFIG_SYS_PROMPT               "Wave7Optics> " /* Monitor Command Prompt       */
 112 #undef  CONFIG_SYS_HUSH_PARSER                          /* No hush parse for U-Boot       */
 113 #ifdef  CONFIG_SYS_HUSH_PARSER
 114 #define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 115 #endif
 116 #if defined(CONFIG_CMD_KGDB)
 117 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
 118 #else
 119 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 120 #endif
 121 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 122 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 123 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 124
 125 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on             */
 126 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM          */
 127
 128 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK                     /* external serial clock */
 129 #define CONFIG_SYS_405_UART_ERRATA_59                   /* 405GP/CR Rev. D silicon */
 130 #define CONFIG_SYS_BASE_BAUD            384000
 131
 132
 133 /* The following table includes the supported baudrates */
 134 #define CONFIG_SYS_BAUDRATE_TABLE       {9600}
 135
 136 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address         */
 137 #define CONFIG_SYS_EXTBDINFO            1               /* use extended board_info (bd_t) */
 138
 139 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1 ms ticks */
 140
 141 /*-----------------------------------------------------------------------
 142  * PCI stuff
 143  *-----------------------------------------------------------------------
 144  */
 145 #define PCI_HOST_ADAPTER        0               /* configure as pci adapter     */
 146 #define PCI_HOST_FORCE          1               /* configure as pci host        */
 147 #define PCI_HOST_AUTO           2               /* detected via arbiter enable  */
 148
 149
 150 #define CONFIG_PCI                              /* include pci support          */
 151 #define CONFIG_PCI_HOST         PCI_HOST_AUTO   /* select pci host function     */
 152 #define CONFIG_PCI_PNP                          /* pci plug-and-play            */
 153 /* resource configuration       */
 154 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014           /* PCI Vendor ID: IBM           */
 155 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156           /* PCI Device ID: 405GP         */
 156 #define CONFIG_SYS_PCI_PTM1LA           0x00000000      /* point to sdram               */
 157 #define CONFIG_SYS_PCI_PTM1MS           0x80000001      /* 2GB, enable hard-wired to 1  */
 158 #define CONFIG_SYS_PCI_PTM1PCI          0x00000000      /* Host: use this pci address   */
 159 #define CONFIG_SYS_PCI_PTM2LA           0x00000000      /* disabled                     */
 160 #define CONFIG_SYS_PCI_PTM2MS           0x00000000      /* disabled                     */
 161 #define CONFIG_SYS_PCI_PTM2PCI          0x00000000      /* Host: use this pci address   */
 162
 163 /*-----------------------------------------------------------------------
 164  * Set up values for external bus controller
 165  * used by cpu_init.c
 166  *-----------------------------------------------------------------------
 167  */
 168  /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
 169 #undef CONFIG_USE_PERWE
 170
 171 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 172 #define CONFIG_SYS_TEMP_STACK_OCM        1
 173
 174 /* bank 0 is boot flash */
 175 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
 176 #define CONFIG_SYS_W7O_EBC_PB0AP   0x03050440
 177 /* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
 178 #define CONFIG_SYS_W7O_EBC_PB0CR   0xFFE38000
 179
 180 /* bank 1 is main flash */
 181 /* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
 182 #define CONFIG_SYS_EBC_PB1AP   0x05850240
 183 /* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
 184 #define CONFIG_SYS_EBC_PB1CR   0xF00FC000
 185
 186 /* bank 2 is RTC/NVRAM */
 187 /* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
 188 #define CONFIG_SYS_EBC_PB2AP   0x03000440
 189 /* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
 190 #define CONFIG_SYS_EBC_PB2CR   0xFC018000
 191
 192 /* bank 3 is FPGA 0 */
 193 /* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
 194 #define CONFIG_SYS_EBC_PB3AP   0x02000400
 195 /* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
 196 #define CONFIG_SYS_EBC_PB3CR   0xFD01A000
 197
 198 /* bank 4 is FPGA 1 */
 199 /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
 200 #define CONFIG_SYS_EBC_PB4AP   0x02000400
 201 /* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
 202 #define CONFIG_SYS_EBC_PB4CR   0xFD11A000
 203
 204 /* bank 5 is FPGA 2 */
 205 /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
 206 #define CONFIG_SYS_EBC_PB5AP   0x02000400
 207 /* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
 208 #define CONFIG_SYS_EBC_PB5CR   0xFD21A000
 209
 210 /* bank 6 is unused */
 211 /* PB6AP = 0 */
 212 #define CONFIG_SYS_EBC_PB6AP   0x00000000
 213 /* PB6CR = 0 */
 214 #define CONFIG_SYS_EBC_PB6CR   0x00000000
 215
 216 /* bank 7 is LED register */
 217 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
 218 #define CONFIG_SYS_W7O_EBC_PB7AP   0x03050440
 219 /* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
 220 #define CONFIG_SYS_W7O_EBC_PB7CR   0xFE01C000
 221
 222 /*-----------------------------------------------------------------------
 223  * Start addresses for the final memory configuration
 224  * (Set up by the startup code)
 225  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 226  */
 227 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 228 #define CONFIG_SYS_FLASH_BASE           0xFFFC0000
 229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 230 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 231 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 232
 233 /*
 234  * For booting Linux, the board info and command line data
 235  * have to be in the first 8 MB of memory, since this is
 236  * the maximum mapped by the Linux kernel during initialization.
 237  */
 238 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 239 /*-----------------------------------------------------------------------
 240  * FLASH organization
 241  */
 242 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* max number of memory banks   */
 243 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max number of sec on 1 chip  */
 244
 245 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000          /* Timeout, Flash Erase, in ms  */
 246 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Timeout, Flash Write, in ms  */
 247 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use real Flash protection    */
 248
 249 #if 1 /* Use NVRAM for environment variables */
 250 /*-----------------------------------------------------------------------
 251  * NVRAM organization
 252  */
 253 #define CONFIG_ENV_IS_IN_NVRAM  1               /* use NVRAM for env vars       */
 254 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xfc000000      /* NVRAM base address           */
 255 #define CONFIG_SYS_NVRAM_SIZE           (32*1024)       /* NVRAM size                   */
 256 #define CONFIG_ENV_SIZE         0x1000          /* Size of Environment vars     */
 257 /*define CONFIG_ENV_ADDR                 \
 258         (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env  */
 259 #define CONFIG_ENV_ADDR         CONFIG_SYS_NVRAM_BASE_ADDR
 260
 261 #else /* Use Boot Flash for environment variables */
 262 /*-----------------------------------------------------------------------
 263  * Flash EEPROM for environment
 264  */
 265 #define CONFIG_ENV_IS_IN_FLASH 1
 266 #define CONFIG_ENV_OFFSET               0x00040000      /* Offset of Environment Sector */
 267 #define CONFIG_ENV_SIZE         0x10000         /* Total Size of env. sector    */
 268
 269 #define CONFIG_ENV_SECT_SIZE    0x10000         /* see README - env sec tot sze */
 270 #endif
 271
 272 /*-----------------------------------------------------------------------
 273  * I2C EEPROM (CAT24WC08) for environment
 274  */
 275 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 276 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 277 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 278 #define CONFIG_SYS_I2C_SLAVE            0x7F
 279
 280 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 281 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address             */
 282 /* mask of address bits that overflow into the "EEPROM chip address"    */
 283 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 284 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 285                                         /* 16 byte page write mode using*/
 286                                         /* last 4 bits of the address   */
 287 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 288 /*-----------------------------------------------------------------------
 289  * Definitions for Serial Presence Detect EEPROM address
 290  * (to get SDRAM settings)
 291  */
 292 #define SPD_EEPROM_ADDRESS      0x50    /* XXX conflicting address!!! XXX */
 293
 294 /*
 295  * Init Memory Controller:
 296  */
 297 #define FLASH_BASE0_PRELIM      0xFFE00000      /* FLASH bank #0                */
 298 #define FLASH_BASE1_PRELIM      0xF0000000      /* FLASH bank #1                */
 299
 300 /* On Chip Memory location */
 301 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 302 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 303
 304 /*-----------------------------------------------------------------------
 305  * Definitions for initial stack pointer and data area (in RAM)
 306  */
 307 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 308 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM     */
 309 #define CONFIG_SYS_GBL_DATA_SIZE        64              /* size in bytes reserved for initial data */
 310 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 311 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 312
 313
 314 /*
 315  * Internal Definitions
 316  *
 317  * Boot Flags
 318  */
 319 #define BOOTFLAG_COLD           0x01            /* Normal Power-On: Boot from FLASH */
 320 #define BOOTFLAG_WARM           0x02            /* Software reboot              */
 321
 322 #if defined(CONFIG_CMD_KGDB)
 323 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 324 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use     */
 325 #endif
 326
 327 /*
 328  * FPGA(s) configuration
 329  */
 330 #define CONFIG_SYS_FPGA_IMAGE_LEN       0x80000         /* 512KB FPGA image             */
 331 #define CONFIG_NUM_FPGAS        3               /* Number of FPGAs on board     */
 332 #define CONFIG_MAX_FPGAS        6               /* Maximum number of FPGAs      */
 333 #define CONFIG_FPGAS_BASE       0xFD000000L     /* Base address of FPGAs        */
 334 #define CONFIG_FPGAS_BANK_SIZE  0x00100000L     /* FPGAs' mmap bank size        */
 335
 336 #endif  /* __CONFIG_H */