include/configs/W7OLMG.h

   1 /*
   2  * (C) Copyright 2001
   3  * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405GP            1               /* This is a PPC405GP CPU       */
  37 #define CONFIG_4xx              1               /* ...member of PPC405 family   */
  38 #define CONFIG_W7O              1               /* ...on a Wave 7 Optics board  */
  39 #define CONFIG_W7OLMG           1               /* ...specifically an LMG       */
  40
  41 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f      */
  42 #define CONFIG_MISC_INIT_F      1               /* and misc_init_f()            */
  43 #define CONFIG_MISC_INIT_R      1               /* and misc_init_r()            */
  44
  45 #define CONFIG_SYS_CLK_FREQ     33333333        /* external frequency to pll    */
  46
  47 #define CONFIG_BAUDRATE         9600
  48 #define CONFIG_BOOTDELAY        3               /* autoboot after 3 seconds     */
  49
  50 #if 1
  51 #define CONFIG_BOOTCOMMAND      "bootvx"        /* VxWorks boot command         */
  52 #else
  53 #define CONFIG_BOOTCOMMAND      "bootp"         /* autoboot command             */
  54 #endif
  55
  56 #undef CONFIG_BOOTARGS
  57
  58 #define CONFIG_LOADADDR         F0080000
  59
  60 #define CONFIG_ETHADDR          00:06:0D:00:00:00 /* Default, overridden at boot        */
  61 #define CONFIG_OVERWRITE_ETHADDR_ONCE
  62 #define CONFIG_IPADDR           192.168.1.1
  63 #define CONFIG_NETMASK          255.255.255.0
  64 #define CONFIG_SERVERIP         192.168.1.2
  65
  66 #define CONFIG_LOADS_ECHO       1               /* echo on for serial download  */
  67 #undef CONFIG_SYS_LOADS_BAUD_CHANGE                     /* disallow baudrate change     */
  68
  69 #define CONFIG_PPC4xx_EMAC
  70 #define CONFIG_MII              1               /* MII PHY management           */
  71 #define CONFIG_PHY_ADDR         0               /* PHY address                  */
  72 #define CONFIG_NET_MULTI
  73
  74 #define CONFIG_RTC_M48T35A      1               /* ST Electronics M48 timekeeper */
  75 #define CONFIG_DTT_LM75     1                /* ON Semi's LM75 */
  76 #define CONFIG_DTT_SENSORS  {2, 4}           /* Sensor addresses */
  77 #define CONFIG_SYS_DTT_MAX_TEMP 70
  78 #define CONFIG_SYS_DTT_LOW_TEMP -30
  79 #define CONFIG_SYS_DTT_HYSTERESIS       3
  80
  81
  82 /*
  83  * BOOTP options
  84  */
  85 #define CONFIG_BOOTP_BOOTFILESIZE
  86 #define CONFIG_BOOTP_BOOTPATH
  87 #define CONFIG_BOOTP_GATEWAY
  88 #define CONFIG_BOOTP_HOSTNAME
  89
  90
  91 /*
  92  * Command line configuration.
  93  */
  94 #include <config_cmd_default.h>
  95
  96 #define CONFIG_CMD_PCI
  97 #define CONFIG_CMD_IRQ
  98 #define CONFIG_CMD_ASKENV
  99 #define CONFIG_CMD_DHCP
 100 #define CONFIG_CMD_BEDBUG
 101 #define CONFIG_CMD_DATE
 102 #define CONFIG_CMD_I2C
 103 #define CONFIG_CMD_EEPROM
 104 #define CONFIG_CMD_ELF
 105 #define CONFIG_CMD_BSP
 106 #define CONFIG_CMD_REGINFO
 107 #define CONFIG_CMD_DTT
 108
 109
 110 #undef CONFIG_WATCHDOG                          /* watchdog disabled            */
 111 #define CONFIG_HW_WATCHDOG                      /* HW Watchdog, board specific  */
 112
 113 #define CONFIG_SPD_EEPROM                       /* SPD EEPROM for SDRAM param.  */
 114 #define CONFIG_SPDDRAM_SILENT                   /* No output if spd fails       */
 115 /*
 116  * Miscellaneous configurable options
 117  */
 118 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
 119 #define CONFIG_SYS_PROMPT               "Wave7Optics> " /* Monitor Command Prompt       */
 120 #undef  CONFIG_SYS_HUSH_PARSER                          /* No hush parse for U-Boot       */
 121 #ifdef  CONFIG_SYS_HUSH_PARSER
 122 #define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 123 #endif
 124 #if defined(CONFIG_CMD_KGDB)
 125 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
 126 #else
 127 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 128 #endif
 129 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 130 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 131 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 132
 133 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on             */
 134 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM          */
 135
 136 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK                     /* external serial clock */
 137 #define CONFIG_SYS_405_UART_ERRATA_59                   /* 405GP/CR Rev. D silicon */
 138 #define CONFIG_SYS_BASE_BAUD            384000
 139
 140
 141 /* The following table includes the supported baudrates */
 142 #define CONFIG_SYS_BAUDRATE_TABLE       {9600}
 143
 144 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address         */
 145 #define CONFIG_SYS_EXTBDINFO            1               /* use extended board_info (bd_t) */
 146
 147 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1 ms ticks */
 148
 149 /*-----------------------------------------------------------------------
 150  * PCI stuff
 151  *-----------------------------------------------------------------------
 152  */
 153 #define PCI_HOST_ADAPTER        0               /* configure as pci adapter     */
 154 #define PCI_HOST_FORCE          1               /* configure as pci host        */
 155 #define PCI_HOST_AUTO           2               /* detected via arbiter enable  */
 156
 157 #define CONFIG_PCI                              /* include pci support          */
 158 #define CONFIG_PCI_HOST         PCI_HOST_AUTO   /* select pci host function     */
 159 #define CONFIG_PCI_PNP                          /* pci plug-and-play            */
 160 /* resource configuration       */
 161 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014           /* PCI Vendor ID: IBM           */
 162 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156           /* PCI Device ID: 405GP         */
 163 #define CONFIG_SYS_PCI_PTM1LA           0x00000000      /* point to sdram               */
 164 #define CONFIG_SYS_PCI_PTM1MS           0x80000001      /* 2GB, enable hard-wired to 1  */
 165 #define CONFIG_SYS_PCI_PTM1PCI          0x00000000      /* Host: use this pci address   */
 166 #define CONFIG_SYS_PCI_PTM2LA           0x00000000      /* disabled                     */
 167 #define CONFIG_SYS_PCI_PTM2MS           0x00000000      /* disabled                     */
 168 #define CONFIG_SYS_PCI_PTM2PCI          0x00000000      /* Host: use this pci address   */
 169
 170 /*-----------------------------------------------------------------------
 171  * Set up values for external bus controller
 172  * used by cpu_init.c
 173  *-----------------------------------------------------------------------
 174  */
 175  /* use PerWE instead of PCI_INT ( these functions share a pin ) */
 176 #define CONFIG_USE_PERWE 1
 177
 178 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 179 #define CONFIG_SYS_TEMP_STACK_OCM        1
 180
 181 /* bank 0 is boot flash */
 182 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
 183 #define CONFIG_SYS_W7O_EBC_PB0AP   0x03050440
 184 /* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
 185 #define CONFIG_SYS_W7O_EBC_PB0CR   0xFFE38000
 186
 187 /* bank 1 is main flash */
 188 /* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
 189 #define CONFIG_SYS_EBC_PB1AP   0x04850240
 190 /* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
 191 #define CONFIG_SYS_EBC_PB1CR   0xF00FC000
 192
 193 /* bank 2 is RTC/NVRAM */
 194 /* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
 195 #define CONFIG_SYS_EBC_PB2AP   0x03000440
 196 /* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
 197 #define CONFIG_SYS_EBC_PB2CR   0xFC018000
 198
 199 /* bank 3 is FPGA 0 */
 200 /* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
 201 #define CONFIG_SYS_EBC_PB3AP   0x02000400
 202 /* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
 203 #define CONFIG_SYS_EBC_PB3CR   0xFD01A000
 204
 205 /* bank 4 is SAM 8 bit range */
 206 /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
 207 #define CONFIG_SYS_EBC_PB4AP   0x02840380
 208 /* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
 209 #define CONFIG_SYS_EBC_PB4CR   0xFE878000
 210
 211 /* bank 5 is SAM 16 bit range */
 212 /* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */
 213 #define CONFIG_SYS_EBC_PB5AP   0x05040d80
 214 /* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
 215 #define CONFIG_SYS_EBC_PB5CR   0xFD87A000
 216
 217 /* bank 6 is unused */
 218 /* PB6AP = 0 */
 219 #define CONFIG_SYS_EBC_PB6AP   0x00000000
 220 /* PB6CR = 0 */
 221 #define CONFIG_SYS_EBC_PB6CR   0x00000000
 222
 223 /* bank 7 is LED register */
 224 /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
 225 #define CONFIG_SYS_W7O_EBC_PB7AP   0x03050440
 226 /* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
 227 #define CONFIG_SYS_W7O_EBC_PB7CR   0xFE01C000
 228
 229 /*-----------------------------------------------------------------------
 230  * Start addresses for the final memory configuration
 231  * (Set up by the startup code)
 232  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 233  */
 234 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 235 #define CONFIG_SYS_FLASH_BASE           0xFFFC0000
 236 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 237 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 196 kB for Monitor   */
 238 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 239
 240 /*
 241  * For booting Linux, the board info and command line data
 242  * have to be in the first 8 MB of memory, since this is
 243  * the maximum mapped by the Linux kernel during initialization.
 244  */
 245 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 246 /*-----------------------------------------------------------------------
 247  * FLASH organization
 248  */
 249 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* max number of memory banks   */
 250 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max number of sec on 1 chip  */
 251
 252 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000          /* Timeout, Flash Erase, in ms  */
 253 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Timeout, Flash Write, in ms  */
 254 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use real Flash protection    */
 255
 256 #if 1 /* Use NVRAM for environment variables */
 257 /*-----------------------------------------------------------------------
 258  * NVRAM organization
 259  */
 260 #define CONFIG_ENV_IS_IN_NVRAM  1               /* use NVRAM for env vars       */
 261 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xfc000000      /* NVRAM base address           */
 262 #define CONFIG_SYS_NVRAM_SIZE           (32*1024)       /* NVRAM size                   */
 263 #define CONFIG_ENV_SIZE         0x1000          /* Size of Environment vars     */
 264 /*define CONFIG_ENV_ADDR                 \
 265         (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env  */
 266 #define CONFIG_ENV_ADDR         CONFIG_SYS_NVRAM_BASE_ADDR
 267
 268 #else /* Use Boot Flash for environment variables */
 269 /*-----------------------------------------------------------------------
 270  * Flash EEPROM for environment
 271  */
 272 #define CONFIG_ENV_IS_IN_FLASH 1
 273 #define CONFIG_ENV_OFFSET               0x00040000      /* Offset of Environment Sector */
 274 #define CONFIG_ENV_SIZE         0x10000         /* Total Size of env. sector    */
 275
 276 #define CONFIG_ENV_SECT_SIZE    0x10000         /* see README - env sec tot sze */
 277 #endif
 278
 279 /*-----------------------------------------------------------------------
 280  * I2C EEPROM (ATMEL 24C04N)
 281  */
 282 #define CONFIG_HARD_I2C         1               /* Hardware assisted I2C        */
 283 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 284 #define CONFIG_SYS_I2C_SPEED            400000          /* I2C speed and slave address */
 285 #define CONFIG_SYS_I2C_SLAVE            0x7F
 286
 287 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50            /* EEPROM ATMEL 24C04N          */
 288 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1               /* Bytes of address             */
 289 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 290 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 291 /*-----------------------------------------------------------------------
 292  * Definitions for Serial Presence Detect EEPROM address
 293  * (to get SDRAM settings)
 294  */
 295 #define SPD_EEPROM_ADDRESS      0x50    /* XXX conflicting address!!! XXX */
 296
 297 /*
 298  * Init Memory Controller:
 299  */
 300 #define FLASH_BASE0_PRELIM      0xFFE00000      /* FLASH bank #0                */
 301 #define FLASH_BASE1_PRELIM      0xF0000000      /* FLASH bank #1                */
 302
 303 /* On Chip Memory location */
 304 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 305 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 306
 307 /*-----------------------------------------------------------------------
 308  * Definitions for initial stack pointer and data area (in RAM)
 309  */
 310 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 311 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM     */
 312 #define CONFIG_SYS_GBL_DATA_SIZE        64              /* size in bytes reserved for initial data */
 313 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 314 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 315
 316
 317 /*
 318  * Internal Definitions
 319  *
 320  * Boot Flags
 321  */
 322 #define BOOTFLAG_COLD           0x01            /* Normal Power-On: Boot from FLASH */
 323 #define BOOTFLAG_WARM           0x02            /* Software reboot              */
 324
 325 #if defined(CONFIG_CMD_KGDB)
 326 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 327 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use     */
 328 #endif
 329
 330 /*
 331  * FPGA(s) configuration
 332  */
 333 #define CONFIG_SYS_FPGA_IMAGE_LEN       0x80000         /* 512KB FPGA image             */
 334 #define CONFIG_NUM_FPGAS        1               /* Number of FPGAs on board     */
 335 #define CONFIG_MAX_FPGAS        6               /* Maximum number of FPGAs      */
 336 #define CONFIG_FPGAS_BASE       0xFD000000L     /* Base address of FPGAs        */
 337 #define CONFIG_FPGAS_BANK_SIZE  0x00100000L     /* FPGAs' mmap bank size        */
 338
 339 #endif  /* __CONFIG_H */