include/configs/WUH405.h

   1 /*
   2  * (C) Copyright 2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19 #define CONFIG_IDENT_STRING     " $Name:  $"
  20
  21 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  22 #define CONFIG_WUH405           1       /* ...on a WUH405 board         */
  23
  24 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  25
  26 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  27 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  28
  29 #define CONFIG_SYS_CLK_FREQ     33333300 /* external frequency to pll   */
  30
  31 #define CONFIG_BAUDRATE         9600
  32 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  33
  34 #undef  CONFIG_BOOTARGS
  35 #undef  CONFIG_BOOTCOMMAND
  36
  37 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  38
  39 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  40 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  41
  42 #define CONFIG_PPC4xx_EMAC
  43 #define CONFIG_MII              1       /* MII PHY management           */
  44 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  45 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  46
  47 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  48
  49
  50 /*
  51  * BOOTP options
  52  */
  53 #define CONFIG_BOOTP_BOOTFILESIZE
  54 #define CONFIG_BOOTP_BOOTPATH
  55 #define CONFIG_BOOTP_GATEWAY
  56 #define CONFIG_BOOTP_HOSTNAME
  57
  58
  59 /*
  60  * Command line configuration.
  61  */
  62 #include <config_cmd_default.h>
  63
  64 #define CONFIG_CMD_DHCP
  65 #define CONFIG_CMD_IRQ
  66 #define CONFIG_CMD_ELF
  67 #define CONFIG_CMD_NAND
  68 #define CONFIG_CMD_DATE
  69 #define CONFIG_CMD_I2C
  70 #define CONFIG_CMD_MII
  71 #define CONFIG_CMD_PING
  72 #define CONFIG_CMD_EEPROM
  73
  74
  75 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  76
  77 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
  78 #define CONFIG_SYS_RTC_REG_BASE_ADDR     0xF0000500 /* RTC Base Address         */
  79
  80 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  81
  82 /*
  83  * Miscellaneous configurable options
  84  */
  85 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  86
  87 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
  88
  89 #if defined(CONFIG_CMD_KGDB)
  90 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  91 #else
  92 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  93 #endif
  94 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  95 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  96 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  97
  98 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
  99
 100 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 101
 102 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 103 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 104
 105 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
 106 #define CONFIG_SYS_NS16550
 107 #define CONFIG_SYS_NS16550_SERIAL
 108 #define CONFIG_SYS_NS16550_REG_SIZE     1
 109 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 110
 111 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 112 #define CONFIG_SYS_BASE_BAUD        691200
 113
 114 /* The following table includes the supported baudrates */
 115 #define CONFIG_SYS_BAUDRATE_TABLE       \
 116         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 117          57600, 115200, 230400, 460800, 921600 }
 118
 119 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 120 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 121
 122 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 123
 124 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 125
 126 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 127
 128 /*-----------------------------------------------------------------------
 129  * NAND-FLASH stuff
 130  *-----------------------------------------------------------------------
 131  */
 132 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 133 #define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
 134 #define NAND_BIG_DELAY_US       25
 135
 136 #define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
 137 #define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
 138 #define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 139 #define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 140
 141 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
 142
 143 /*-----------------------------------------------------------------------
 144  * PCI stuff
 145  *-----------------------------------------------------------------------
 146  */
 147 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 148 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 149 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 150
 151 #define CONFIG_PCI                      /* include pci support          */
 152 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 153 #define CONFIG_PCI_HOST PCI_HOST_HOST   /* select pci host function     */
 154 #undef  CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 155                                         /* resource configuration       */
 156
 157 #undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 158
 159 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 160 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405   /* PCI Device ID: CPCI-405      */
 161 #define CONFIG_SYS_PCI_CLASSCODE        0x0b20  /* PCI Class Code: Processor/PPC*/
 162 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 163 #define CONFIG_SYS_PCI_PTM1MS   0xfc000001      /* 64MB, enable hard-wired to 1 */
 164 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
 165 #define CONFIG_SYS_PCI_PTM2LA   0xffc00000      /* point to flash               */
 166 #define CONFIG_SYS_PCI_PTM2MS   0xffc00001      /* 4MB, enable                  */
 167 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000       /* Host: use this pci address   */
 168
 169 /*-----------------------------------------------------------------------
 170  * Start addresses for the final memory configuration
 171  * (Set up by the startup code)
 172  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 173  */
 174 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 175 #define CONFIG_SYS_FLASH_BASE           0xFFFC0000
 176 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 177 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 178 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Reserve 256 kB for malloc()  */
 179
 180 /*
 181  * For booting Linux, the board info and command line data
 182  * have to be in the first 8 MB of memory, since this is
 183  * the maximum mapped by the Linux kernel during initialization.
 184  */
 185 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 186 /*-----------------------------------------------------------------------
 187  * FLASH organization
 188  */
 189 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 190 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 191
 192 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 193 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 194
 195 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 196 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 197 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 198 /*
 199  * The following defines are added for buggy IOP480 byte interface.
 200  * All other boards should use the standard values (CPCI405 etc.)
 201  */
 202 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 203 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 204 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 205
 206 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 207
 208 #if 0 /* test-only */
 209 #define CONFIG_SYS_JFFS2_FIRST_BANK     0           /* use for JFFS2 */
 210 #define CONFIG_SYS_JFFS2_NUM_BANKS      1           /* ! second bank contains U-Boot */
 211 #endif
 212
 213 /*-----------------------------------------------------------------------
 214  * Environment Variable setup
 215  */
 216 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 217 #define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 218 #define CONFIG_ENV_SIZE         0x700   /* 2048 bytes may be used for env vars*/
 219                                    /* total size of a CAT24WC16 is 2048 bytes */
 220
 221 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xF0000500              /* NVRAM base address   */
 222 #define CONFIG_SYS_NVRAM_SIZE           242                     /* NVRAM size           */
 223
 224 /*-----------------------------------------------------------------------
 225  * I2C EEPROM (CAT24WC16) for environment
 226  */
 227 #define CONFIG_SYS_I2C
 228 #define CONFIG_SYS_I2C_PPC4XX
 229 #define CONFIG_SYS_I2C_PPC4XX_CH0
 230 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 231 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 232
 233 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 234 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 235 /* mask of address bits that overflow into the "EEPROM chip address"    */
 236 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 237 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 238                                         /* 16 byte page write mode using*/
 239                                         /* last 4 bits of the address   */
 240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 241
 242 /*
 243  * Init Memory Controller:
 244  *
 245  * BR0/1 and OR0/1 (FLASH)
 246  */
 247
 248 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 249
 250 /*-----------------------------------------------------------------------
 251  * External Bus Controller (EBC) Setup
 252  */
 253
 254 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 255 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 256 /*#define CONFIG_SYS_EBC_PB0AP            0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
 257 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 258
 259 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization                      */
 260 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 261 #define CONFIG_SYS_EBC_PB1CR            0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
 262
 263 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 264 #define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 265 #define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 266
 267 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
 268 #define CONFIG_SYS_EBC_PB3AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 269 #define CONFIG_SYS_EBC_PB3CR            0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 270
 271 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 272 #define DUART0_BA       0xF0000400          /* DUART Base Address               */
 273 #define DUART1_BA       0xF0000408          /* DUART Base Address               */
 274 #define DUART2_BA       0xF0000410          /* DUART Base Address               */
 275 #define DUART3_BA       0xF0000418          /* DUART Base Address               */
 276 #define RTC_BA          0xF0000500          /* RTC Base Address                 */
 277 #define CONFIG_SYS_NAND_BASE    0xF4000000
 278
 279 /*-----------------------------------------------------------------------
 280  * FPGA stuff
 281  */
 282 #define CONFIG_SYS_FPGA_SPARTAN2        1           /* using Xilinx Spartan 2 now    */
 283 #define CONFIG_SYS_FPGA_MAX_SIZE        128*1024    /* 128kByte is enough for XC2S50E*/
 284
 285 /* FPGA program pin configuration */
 286 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* FPGA program pin (ppc output) */
 287 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* FPGA clk pin (ppc output)     */
 288 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* FPGA data pin (ppc output)    */
 289 #define CONFIG_SYS_FPGA_INIT            0x00010000  /* FPGA init pin (ppc input)     */
 290 #define CONFIG_SYS_FPGA_DONE            0x00008000  /* FPGA done pin (ppc input)     */
 291
 292 /*-----------------------------------------------------------------------
 293  * Definitions for initial stack pointer and data area (in data cache)
 294  */
 295 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 296 #define CONFIG_SYS_TEMP_STACK_OCM         1
 297
 298 /* On Chip Memory location */
 299 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 300 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 301 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 302 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 303
 304 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 305 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 306
 307 /*-----------------------------------------------------------------------
 308  * Definitions for GPIO setup (PPC405EP specific)
 309  *
 310  * GPIO0[0]     - External Bus Controller BLAST output
 311  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 312  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 313  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 314  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 315  * GPIO0[24-27] - UART0 control signal inputs/outputs
 316  * GPIO0[28-29] - UART1 data signal input/output
 317  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 318  */
 319 #define CONFIG_SYS_GPIO0_OSRL           0x40000550
 320 #define CONFIG_SYS_GPIO0_OSRH           0x00000110
 321 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000
 322 #define CONFIG_SYS_GPIO0_ISR1H          0x15555445
 323 #define CONFIG_SYS_GPIO0_TSRL           0x00000000
 324 #define CONFIG_SYS_GPIO0_TSRH           0x00000000
 325 #define CONFIG_SYS_GPIO0_TCR            0xF7FE0014
 326
 327 #define CONFIG_SYS_DUART_RST            (0x80000000 >> 14)
 328
 329 /*
 330  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 331  * This value will be set if iic boot eprom is disabled.
 332  */
 333 #if 0
 334 #define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 335 #define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
 336 #endif
 337 #if 1
 338 #define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
 339 #define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
 340 #endif
 341 #if 0
 342 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 343 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 344 #endif
 345
 346 #endif  /* __CONFIG_H */