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EHCI: fix root hub device descriptor
[people/ms/u-boot.git] / include / configs / XPEDITE5170.h
1 /*
2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 * xpedite5170 board configuration file
26 */
27 #ifndef __CONFIG_H
28 #define __CONFIG_H
29
30 /*
31 * High Level Configuration Options
32 */
33 #define CONFIG_MPC86xx 1 /* MPC86xx */
34 #define CONFIG_MPC8641 1 /* MPC8641 specific */
35 #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
36 #define CONFIG_SYS_BOARD_NAME "XPedite5170"
37 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
38 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
39 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
40 #define CONFIG_ALTIVEC 1
41
42 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
43 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
44 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
45 #define CONFIG_PCIE1 1 /* PCIE controler 1 */
46 #define CONFIG_PCIE2 1 /* PCIE controler 2 */
47 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
48 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
49 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
50
51 /*
52 * DDR config
53 */
54 #define CONFIG_FSL_DDR2
55 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
56 #define CONFIG_DDR_SPD
57 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
58 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
59 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
60 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
61 #define CONFIG_NUM_DDR_CONTROLLERS 2
62 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
63 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
64 #define CONFIG_DDR_ECC
65 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
66 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
67 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
68 #define CONFIG_VERY_BIG_RAM
69 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
70
71 /*
72 * virtual address to be used for temporary mappings. There
73 * should be 128k free at this VA.
74 */
75 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
76
77 #ifndef __ASSEMBLY__
78 extern unsigned long get_board_sys_clk(unsigned long dummy);
79 #endif
80
81 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
82
83 /*
84 * L2CR setup
85 */
86 #define CONFIG_SYS_L2
87 #define L2_INIT 0
88 #define L2_ENABLE (L2CR_L2E)
89
90 /*
91 * Base addresses -- Note these are effective addresses where the
92 * actual resources get mapped (not physical addresses)
93 */
94 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
95 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
96 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
97 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
98 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
99 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
100 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
101 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
102
103 /*
104 * Diagnostics
105 */
106 #define CONFIG_SYS_ALT_MEMTEST
107 #define CONFIG_SYS_MEMTEST_START 0x10000000
108 #define CONFIG_SYS_MEMTEST_END 0x20000000
109
110 /*
111 * Memory map
112 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
113 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
114 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
115 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
116 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
117 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
118 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
119 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
120 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
121 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
122 */
123
124 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
125
126 /*
127 * NAND flash configuration
128 */
129 #define CONFIG_SYS_NAND_BASE 0xef800000
130 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
131 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
132 #define CONFIG_SYS_MAX_NAND_DEVICE 2
133 #define CONFIG_NAND_ACTL
134 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
135 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
136 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
137 #define CONFIG_SYS_NAND_ACTL_DELAY 25
138 #define CONFIG_SYS_NAND_QUIET_TEST
139 #define CONFIG_JFFS2_NAND
140
141 /*
142 * NOR flash configuration
143 */
144 #define CONFIG_SYS_FLASH_BASE 0xf8000000
145 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
146 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
147 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
148 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
149 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
150 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
151 #define CONFIG_FLASH_CFI_DRIVER
152 #define CONFIG_SYS_FLASH_CFI
153 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
154 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
155 {0xf7f00000, 0xc0000} }
156 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
157 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
158
159 /*
160 * Chip select configuration
161 */
162 /* NOR Flash 0 on CS0 */
163 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
164 BR_PS_16 |\
165 BR_V)
166 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
167 OR_GPCM_CSNT |\
168 OR_GPCM_XACS |\
169 OR_GPCM_ACS_DIV2 |\
170 OR_GPCM_SCY_8 |\
171 OR_GPCM_TRLX |\
172 OR_GPCM_EHTR |\
173 OR_GPCM_EAD)
174
175 /* NOR Flash 1 on CS1 */
176 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
177 BR_PS_16 |\
178 BR_V)
179 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
180
181 /* NAND flash on CS2 */
182 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
183 BR_PS_8 |\
184 BR_V)
185 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
186 OR_GPCM_BCTLD |\
187 OR_GPCM_CSNT |\
188 OR_GPCM_ACS_DIV4 |\
189 OR_GPCM_SCY_4 |\
190 OR_GPCM_TRLX |\
191 OR_GPCM_EHTR)
192
193 /* Optional NAND flash on CS3 */
194 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
195 BR_PS_8 |\
196 BR_V)
197 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
198
199 /*
200 * Use L1 as initial stack
201 */
202 #define CONFIG_SYS_INIT_RAM_LOCK 1
203 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
204 #define CONFIG_SYS_INIT_RAM_END 0x00004000
205
206 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
207 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
208 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
209
210 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
211 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
212
213 /*
214 * Serial Port
215 */
216 #define CONFIG_CONS_INDEX 1
217 #define CONFIG_SYS_NS16550
218 #define CONFIG_SYS_NS16550_SERIAL
219 #define CONFIG_SYS_NS16550_REG_SIZE 1
220 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
221 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
222 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
223 #define CONFIG_SYS_BAUDRATE_TABLE \
224 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
225 #define CONFIG_BAUDRATE 115200
226 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
227 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
228
229 /*
230 * Use the HUSH parser
231 */
232 #define CONFIG_SYS_HUSH_PARSER
233 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
234
235 /*
236 * Pass open firmware flat tree
237 */
238 #define CONFIG_OF_LIBFDT 1
239 #define CONFIG_OF_BOARD_SETUP 1
240 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
241
242 /*
243 * I2C
244 */
245 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
246 #define CONFIG_HARD_I2C /* I2C with hardware support */
247 #define CONFIG_SYS_I2C_SPEED 100000 /* M41T00 only supports 100 KHz */
248 #define CONFIG_SYS_I2C_SLAVE 0x7F
249 #define CONFIG_SYS_I2C_OFFSET 0x3000
250 #define CONFIG_SYS_I2C2_OFFSET 0x3100
251 #define CONFIG_I2C_MULTI_BUS
252
253 /* PEX8518 slave I2C interface */
254 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
255
256 /* I2C DS1631 temperature sensor */
257 #define CONFIG_SYS_I2C_DS1621_ADDR 0x48
258 #define CONFIG_DTT_DS1621
259 #define CONFIG_DTT_SENSORS { 0 }
260
261 /* I2C EEPROM - AT24C128B */
262 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
263 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
264 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
265 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
266
267 /* I2C RTC */
268 #define CONFIG_RTC_M41T11 1
269 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
270 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
271
272 /* GPIO/EEPROM/SRAM */
273 #define CONFIG_DS4510
274 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51
275
276 /* GPIO */
277 #define CONFIG_PCA953X
278 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
279 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
280 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
281 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
282 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
283
284 /*
285 * PU = pulled high, PD = pulled low
286 * I = input, O = output, IO = input/output
287 */
288 /* PCA9557 @ 0x18*/
289 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
290 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
291 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
292 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
293 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
294 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
295
296 /* PCA9557 @ 0x1c*/
297 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
298 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
299 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
300 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
301 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
302 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
303 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
304 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
305
306 /* PCA9557 @ 0x1e*/
307 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
308 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
309 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
310 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
311 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
312 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
313 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
314
315 /* PCA9557 @ 0x1f */
316 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
317 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
318 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
319 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
320
321 /*
322 * General PCI
323 * Memory space is mapped 1-1, but I/O space must start from 0.
324 */
325 /* PCIE1 - PEX8518 */
326 #define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
327 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
328 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
329 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
330 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
331 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
332
333 /* PCIE2 - VPX P1 */
334 #define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
335 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
336 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
337 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
338 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
339 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
340
341 /*
342 * Networking options
343 */
344 #define CONFIG_TSEC_ENET /* tsec ethernet support */
345 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
346 #define CONFIG_NET_MULTI 1
347 #define CONFIG_MII 1 /* MII PHY management */
348 #define CONFIG_ETHPRIME "eTSEC1"
349
350 #define CONFIG_TSEC1 1
351 #define CONFIG_TSEC1_NAME "eTSEC1"
352 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
353 #define TSEC1_PHY_ADDR 1
354 #define TSEC1_PHYIDX 0
355 #define CONFIG_HAS_ETH0
356
357 #define CONFIG_TSEC2 1
358 #define CONFIG_TSEC2_NAME "eTSEC2"
359 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
360 #define TSEC2_PHY_ADDR 2
361 #define TSEC2_PHYIDX 0
362 #define CONFIG_HAS_ETH1
363
364 /*
365 * BAT mappings
366 */
367 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
368 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
369 BATL_PP_RW |\
370 BATL_CACHEINHIBIT |\
371 BATL_GUARDEDSTORAGE)
372 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
373 BATU_BL_1M |\
374 BATU_VS |\
375 BATU_VP)
376 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
377 BATL_PP_RW |\
378 BATL_CACHEINHIBIT)
379 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
380 #endif
381
382 /*
383 * BAT0 2G Cacheable, non-guarded
384 * 0x0000_0000 2G DDR
385 */
386 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
387 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
388 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
389 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
390
391 /*
392 * BAT1 1G Cache-inhibited, guarded
393 * 0x8000_0000 1G PCI-Express 1 Memory
394 */
395 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
396 BATL_PP_RW |\
397 BATL_CACHEINHIBIT |\
398 BATL_GUARDEDSTORAGE)
399 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
400 BATU_BL_1G |\
401 BATU_VS |\
402 BATU_VP)
403 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
404 BATL_PP_RW |\
405 BATL_CACHEINHIBIT)
406 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
407
408 /*
409 * BAT2 512M Cache-inhibited, guarded
410 * 0xc000_0000 512M PCI-Express 2 Memory
411 */
412 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
413 BATL_PP_RW |\
414 BATL_CACHEINHIBIT |\
415 BATL_GUARDEDSTORAGE)
416 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
417 BATU_BL_512M |\
418 BATU_VS |\
419 BATU_VP)
420 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
421 BATL_PP_RW |\
422 BATL_CACHEINHIBIT)
423 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
424
425 /*
426 * BAT3 1M Cache-inhibited, guarded
427 * 0xe000_0000 1M CCSR
428 */
429 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
430 BATL_PP_RW |\
431 BATL_CACHEINHIBIT |\
432 BATL_GUARDEDSTORAGE)
433 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
434 BATU_BL_1M |\
435 BATU_VS |\
436 BATU_VP)
437 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
438 BATL_PP_RW |\
439 BATL_CACHEINHIBIT)
440 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
441
442 /*
443 * BAT4 32M Cache-inhibited, guarded
444 * 0xe200_0000 16M PCI-Express 1 I/O
445 * 0xe300_0000 16M PCI-Express 2 I/0
446 */
447 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
448 BATL_PP_RW |\
449 BATL_CACHEINHIBIT |\
450 BATL_GUARDEDSTORAGE)
451 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
452 BATU_BL_32M |\
453 BATU_VS |\
454 BATU_VP)
455 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
456 BATL_PP_RW |\
457 BATL_CACHEINHIBIT)
458 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
459
460 /*
461 * BAT5 128K Cacheable, non-guarded
462 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
463 */
464 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
465 BATL_PP_RW |\
466 BATL_MEMCOHERENCE)
467 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
468 BATU_BL_128K |\
469 BATU_VS |\
470 BATU_VP)
471 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
472 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
473
474 /*
475 * BAT6 256M Cache-inhibited, guarded
476 * 0xf000_0000 256M FLASH
477 */
478 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
479 BATL_PP_RW |\
480 BATL_CACHEINHIBIT |\
481 BATL_GUARDEDSTORAGE)
482 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
483 BATU_BL_256M |\
484 BATU_VS |\
485 BATU_VP)
486 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
487 BATL_PP_RW |\
488 BATL_MEMCOHERENCE)
489 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
490
491 /* Map the last 1M of flash where we're running from reset */
492 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
493 BATL_PP_RW |\
494 BATL_CACHEINHIBIT |\
495 BATL_GUARDEDSTORAGE)
496 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE |\
497 BATU_BL_1M |\
498 BATU_VS |\
499 BATU_VP)
500 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
501 BATL_PP_RW |\
502 BATL_MEMCOHERENCE)
503 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
504
505 /*
506 * BAT7 64M Cache-inhibited, guarded
507 * 0xe800_0000 64K NAND FLASH
508 * 0xe804_0000 128K DUART Registers
509 */
510 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
511 BATL_PP_RW |\
512 BATL_CACHEINHIBIT |\
513 BATL_GUARDEDSTORAGE)
514 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
515 BATU_BL_512K |\
516 BATU_VS |\
517 BATU_VP)
518 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
519 BATL_PP_RW |\
520 BATL_CACHEINHIBIT)
521 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
522
523 /*
524 * Command configuration.
525 */
526 #include <config_cmd_default.h>
527
528 #define CONFIG_CMD_ASKENV
529 #define CONFIG_CMD_DATE
530 #define CONFIG_CMD_DHCP
531 #define CONFIG_CMD_DS4510
532 #define CONFIG_CMD_DS4510_INFO
533 #define CONFIG_CMD_DTT
534 #define CONFIG_CMD_EEPROM
535 #define CONFIG_CMD_ELF
536 #define CONFIG_CMD_SAVEENV
537 #define CONFIG_CMD_FLASH
538 #define CONFIG_CMD_I2C
539 #define CONFIG_CMD_IRQ
540 #define CONFIG_CMD_JFFS2
541 #define CONFIG_CMD_MII
542 #define CONFIG_CMD_NAND
543 #define CONFIG_CMD_NET
544 #define CONFIG_CMD_PCA953X
545 #define CONFIG_CMD_PCA953X_INFO
546 #define CONFIG_CMD_PCI
547 #define CONFIG_CMD_PING
548 #define CONFIG_CMD_REGINFO
549 #define CONFIG_CMD_SNTP
550
551 /*
552 * Miscellaneous configurable options
553 */
554 #define CONFIG_SYS_LONGHELP /* undef to save memory */
555 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
556 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
557 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
558 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
559 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
560 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
561 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
562 #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
563 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
564 #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
565 #define CONFIG_PANIC_HANG /* do not reset board on panic */
566 #define CONFIG_PREBOOT /* enable preboot variable */
567 #define CONFIG_FIT 1
568 #define CONFIG_FIT_VERBOSE 1
569 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
570
571 /*
572 * For booting Linux, the board info and command line data
573 * have to be in the first 16 MB of memory, since this is
574 * the maximum mapped by the Linux kernel during initialization.
575 */
576 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
577 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
578
579 /*
580 * Boot Flags
581 */
582 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
583 #define BOOTFLAG_WARM 0x02 /* Software reboot */
584
585 /*
586 * Environment Configuration
587 */
588 #define CONFIG_ENV_IS_IN_FLASH 1
589 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
590 #define CONFIG_ENV_SIZE 0x8000
591 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
592
593 /*
594 * Flash memory map:
595 * fffc0000 - ffffffff Pri FDT (256KB)
596 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
597 * fff00000 - fff7ffff Pri U-Boot (512 KB)
598 * fef00000 - ffefffff Pri OS image (16MB)
599 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
600 *
601 * f7fc0000 - f7ffffff Sec FDT (256KB)
602 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
603 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
604 * f6f00000 - f7efffff Sec OS image (16MB)
605 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
606 */
607 #define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff00000)
608 #define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f00000)
609 #define CONFIG_FDT1_ENV_ADDR MK_STR(0xfffc0000)
610 #define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7fc0000)
611 #define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
612 #define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
613
614 #define CONFIG_PROG_UBOOT1 \
615 "$download_cmd $loadaddr $ubootfile; " \
616 "if test $? -eq 0; then " \
617 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
618 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
619 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
620 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
621 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
622 "if test $? -ne 0; then " \
623 "echo PROGRAM FAILED; " \
624 "else; " \
625 "echo PROGRAM SUCCEEDED; " \
626 "fi; " \
627 "else; " \
628 "echo DOWNLOAD FAILED; " \
629 "fi;"
630
631 #define CONFIG_PROG_UBOOT2 \
632 "$download_cmd $loadaddr $ubootfile; " \
633 "if test $? -eq 0; then " \
634 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
635 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
636 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
637 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
638 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
639 "if test $? -ne 0; then " \
640 "echo PROGRAM FAILED; " \
641 "else; " \
642 "echo PROGRAM SUCCEEDED; " \
643 "fi; " \
644 "else; " \
645 "echo DOWNLOAD FAILED; " \
646 "fi;"
647
648 #define CONFIG_BOOT_OS_NET \
649 "$download_cmd $osaddr $osfile; " \
650 "if test $? -eq 0; then " \
651 "if test -n $fdtaddr; then " \
652 "$download_cmd $fdtaddr $fdtfile; " \
653 "if test $? -eq 0; then " \
654 "bootm $osaddr - $fdtaddr; " \
655 "else; " \
656 "echo FDT DOWNLOAD FAILED; " \
657 "fi; " \
658 "else; " \
659 "bootm $osaddr; " \
660 "fi; " \
661 "else; " \
662 "echo OS DOWNLOAD FAILED; " \
663 "fi;"
664
665 #define CONFIG_PROG_OS1 \
666 "$download_cmd $osaddr $osfile; " \
667 "if test $? -eq 0; then " \
668 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
669 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
670 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
671 "if test $? -ne 0; then " \
672 "echo OS PROGRAM FAILED; " \
673 "else; " \
674 "echo OS PROGRAM SUCCEEDED; " \
675 "fi; " \
676 "else; " \
677 "echo OS DOWNLOAD FAILED; " \
678 "fi;"
679
680 #define CONFIG_PROG_OS2 \
681 "$download_cmd $osaddr $osfile; " \
682 "if test $? -eq 0; then " \
683 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
684 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
685 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
686 "if test $? -ne 0; then " \
687 "echo OS PROGRAM FAILED; " \
688 "else; " \
689 "echo OS PROGRAM SUCCEEDED; " \
690 "fi; " \
691 "else; " \
692 "echo OS DOWNLOAD FAILED; " \
693 "fi;"
694
695 #define CONFIG_PROG_FDT1 \
696 "$download_cmd $fdtaddr $fdtfile; " \
697 "if test $? -eq 0; then " \
698 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
699 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
700 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
701 "if test $? -ne 0; then " \
702 "echo FDT PROGRAM FAILED; " \
703 "else; " \
704 "echo FDT PROGRAM SUCCEEDED; " \
705 "fi; " \
706 "else; " \
707 "echo FDT DOWNLOAD FAILED; " \
708 "fi;"
709
710 #define CONFIG_PROG_FDT2 \
711 "$download_cmd $fdtaddr $fdtfile; " \
712 "if test $? -eq 0; then " \
713 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
714 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
715 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
716 "if test $? -ne 0; then " \
717 "echo FDT PROGRAM FAILED; " \
718 "else; " \
719 "echo FDT PROGRAM SUCCEEDED; " \
720 "fi; " \
721 "else; " \
722 "echo FDT DOWNLOAD FAILED; " \
723 "fi;"
724
725 #define CONFIG_EXTRA_ENV_SETTINGS \
726 "autoload=yes\0" \
727 "download_cmd=tftp\0" \
728 "console_args=console=ttyS0,115200\0" \
729 "root_args=root=/dev/nfs rw\0" \
730 "misc_args=ip=on\0" \
731 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
732 "bootfile=/home/user/file\0" \
733 "osfile=/home/user/uImage-XPedite5170\0" \
734 "fdtfile=/home/user/xpedite5170.dtb\0" \
735 "ubootfile=/home/user/u-boot.bin\0" \
736 "fdtaddr=c00000\0" \
737 "osaddr=0x1000000\0" \
738 "loadaddr=0x1000000\0" \
739 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
740 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
741 "prog_os1="CONFIG_PROG_OS1"\0" \
742 "prog_os2="CONFIG_PROG_OS2"\0" \
743 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
744 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
745 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
746 "bootcmd_flash1=run set_bootargs; " \
747 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
748 "bootcmd_flash2=run set_bootargs; " \
749 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
750 "bootcmd=run bootcmd_flash1\0"
751 #endif /* __CONFIG_H */
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