include/configs/Yukon8220.h

   1 /*
   2  * (C) Copyright 2004
   3  * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31 #define CONFIG_MPC8220          1
  32 #define CONFIG_YUKON8220        1       /* ... on Yukon board   */
  33
  34 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  35 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  36
  37 /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
  38    determine the CPU speed. */
  39 #define CONFIG_SYS_MPC8220_CLKIN        30000000/* ... running at 30MHz */
  40 #define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
  41
  42 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
  43 #define BOOTFLAG_WARM           0x02    /* Software reboot      */
  44
  45 /*
  46  * Serial console configuration
  47  */
  48
  49 /* Define this for PSC console
  50 #define CONFIG_PSC_CONSOLE      1
  51 */
  52
  53 #define CONFIG_EXTUART_CONSOLE  1
  54
  55 #ifdef CONFIG_EXTUART_CONSOLE
  56 #   define CONFIG_CONS_INDEX    1
  57 #   define CONFIG_SYS_NS16550_SERIAL
  58 #   define CONFIG_SYS_NS16550
  59 #   define CONFIG_SYS_NS16550_REG_SIZE 1
  60 #   define CONFIG_SYS_NS16550_COM1      (CONFIG_SYS_CPLD_BASE + 0x1008)
  61 #   define CONFIG_SYS_NS16550_CLK       18432000
  62 #endif
  63
  64 #define CONFIG_BAUDRATE         115200      /* ... at 115200 bps */
  65
  66 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  67
  68 #define CONFIG_TIMESTAMP                        /* Print image info with timestamp */
  69
  70
  71 /*
  72  * BOOTP options
  73  */
  74 #define CONFIG_BOOTP_BOOTFILESIZE
  75 #define CONFIG_BOOTP_BOOTPATH
  76 #define CONFIG_BOOTP_GATEWAY
  77 #define CONFIG_BOOTP_HOSTNAME
  78
  79
  80 /*
  81  * Command line configuration.
  82  */
  83 #include <config_cmd_default.h>
  84
  85 #define CONFIG_CMD_BOOTD
  86 #define CONFIG_CMD_CACHE
  87 #define CONFIG_CMD_DHCP
  88 #define CONFIG_CMD_DIAG
  89 #define CONFIG_CMD_EEPROM
  90 #define CONFIG_CMD_ELF
  91 #define CONFIG_CMD_I2C
  92 #define CONFIG_CMD_NET
  93 #define CONFIG_CMD_NFS
  94 #define CONFIG_CMD_PCI
  95 #define CONFIG_CMD_PING
  96 #define CONFIG_CMD_REGINFO
  97 #define CONFIG_CMD_SDRAM
  98 #define CONFIG_CMD_SNTP
  99
 100
 101 #define CONFIG_NET_MULTI
 102 #define CONFIG_MII
 103
 104 /*
 105  * Autobooting
 106  */
 107 #define CONFIG_BOOTDELAY        5    /* autoboot after 5 seconds */
 108 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
 109 #define CONFIG_ETHADDR          00:e0:0c:bc:e0:60
 110 #define CONFIG_HAS_ETH1
 111 #define CONFIG_ETH1ADDR         00:e0:0c:bc:e0:61
 112 #define CONFIG_IPADDR           192.162.1.2
 113 #define CONFIG_NETMASK          255.255.255.0
 114 #define CONFIG_SERVERIP         192.162.1.1
 115 #define CONFIG_GATEWAYIP        192.162.1.1
 116 #define CONFIG_HOSTNAME         yukon
 117 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 118
 119
 120 /*
 121  * I2C configuration
 122  */
 123 #define CONFIG_HARD_I2C         1
 124 #define CONFIG_SYS_I2C_MODULE           1
 125
 126 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 127 #define CONFIG_SYS_I2C_SLAVE            0x7F
 128
 129 /*
 130  * EEPROM configuration
 131  */
 132 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x52    /* 1011000xb */
 133 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 134 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 135 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
 136 /*
 137 #define CONFIG_ENV_IS_IN_EEPROM 1
 138 #define CONFIG_ENV_OFFSET               0
 139 #define CONFIG_ENV_SIZE         256
 140 */
 141
 142 /* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
 143    else undefined it will boot from Intel Strata flash */
 144 #define CONFIG_SYS_AMD_BOOT             1
 145
 146 /*
 147  * Flexbus Chipselect configuration
 148  */
 149 #if defined (CONFIG_SYS_AMD_BOOT)
 150 #define CONFIG_SYS_CS0_BASE             0xfff0
 151 #define CONFIG_SYS_CS0_MASK             0x00080000  /* 512 KB */
 152 #define CONFIG_SYS_CS0_CTRL             0x003f0d40
 153
 154 #define CONFIG_SYS_CS1_BASE             0xfe00
 155 #define CONFIG_SYS_CS1_MASK             0x01000000  /* 16 MB */
 156 #define CONFIG_SYS_CS1_CTRL             0x003f1540
 157 #else
 158 #define CONFIG_SYS_CS0_BASE             0xff00
 159 #define CONFIG_SYS_CS0_MASK             0x01000000  /* 16 MB */
 160 #define CONFIG_SYS_CS0_CTRL             0x003f1540
 161
 162 #define CONFIG_SYS_CS1_BASE             0xfe08
 163 #define CONFIG_SYS_CS1_MASK             0x00080000  /* 512 KB */
 164 #define CONFIG_SYS_CS1_CTRL             0x003f0d40
 165 #endif
 166
 167 #define CONFIG_SYS_CS2_BASE             0xf100
 168 #define CONFIG_SYS_CS2_MASK             0x00040000
 169 #define CONFIG_SYS_CS2_CTRL             0x003f1140
 170
 171 #define CONFIG_SYS_CS3_BASE             0xf200
 172 #define CONFIG_SYS_CS3_MASK             0x00040000
 173 #define CONFIG_SYS_CS3_CTRL             0x003f1100
 174
 175
 176 #define CONFIG_SYS_FLASH0_BASE          (CONFIG_SYS_CS0_BASE << 16)
 177 #define CONFIG_SYS_FLASH1_BASE          (CONFIG_SYS_CS1_BASE << 16)
 178
 179 #if defined (CONFIG_SYS_AMD_BOOT)
 180 #define CONFIG_SYS_AMD_BASE             CONFIG_SYS_FLASH0_BASE
 181 #define CONFIG_SYS_INTEL_BASE           CONFIG_SYS_FLASH1_BASE + 0xf00000
 182 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_AMD_BASE
 183 #else
 184 #define CONFIG_SYS_INTEL_BASE           CONFIG_SYS_FLASH0_BASE + 0xf00000
 185 #define CONFIG_SYS_AMD_BASE             CONFIG_SYS_FLASH1_BASE
 186 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_INTEL_BASE
 187 #endif
 188
 189 #define CONFIG_SYS_CPLD_BASE            (CONFIG_SYS_CS2_BASE << 16)
 190 #define CONFIG_SYS_FPGA_BASE            (CONFIG_SYS_CS3_BASE << 16)
 191
 192
 193 #define CONFIG_SYS_MAX_FLASH_BANKS      4       /* max num of memory banks      */
 194 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 195
 196 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 197 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 198 #define CONFIG_SYS_FLASH_LOCK_TOUT      5       /* Timeout for Flash Set Lock Bit (in ms) */
 199 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 200 #define CONFIG_SYS_FLASH_PROTECTION             /* "Real" (hardware) sectors protection */
 201
 202 #define PHYS_AMD_SECT_SIZE      0x00010000 /*  64 KB sectors (x2) */
 203 #define PHYS_INTEL_SECT_SIZE    0x00020000 /* 128 KB sectors (x2) */
 204
 205 #define CONFIG_SYS_FLASH_CHECKSUM
 206 /*
 207  * Environment settings
 208  */
 209 #define CONFIG_ENV_IS_IN_FLASH  1
 210 #if defined (CONFIG_SYS_AMD_BOOT)
 211 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
 212 #define CONFIG_ENV_SIZE         PHYS_AMD_SECT_SIZE
 213 #define CONFIG_ENV_SECT_SIZE    PHYS_AMD_SECT_SIZE
 214 #define CONFIG_ENV1_ADDR                (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
 215 #define CONFIG_ENV1_SIZE                PHYS_INTEL_SECT_SIZE
 216 #define CONFIG_ENV1_SECT_SIZE   PHYS_INTEL_SECT_SIZE
 217 #else
 218 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
 219 #define CONFIG_ENV_SIZE         PHYS_INTEL_SECT_SIZE
 220 #define CONFIG_ENV_SECT_SIZE    PHYS_INTEL_SECT_SIZE
 221 #define CONFIG_ENV1_ADDR                (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
 222 #define CONFIG_ENV1_SIZE                PHYS_AMD_SECT_SIZE
 223 #define CONFIG_ENV1_SECT_SIZE   PHYS_AMD_SECT_SIZE
 224 #endif
 225
 226 #define CONFIG_ENV_OVERWRITE    1
 227
 228 #if defined CONFIG_ENV_IS_IN_FLASH
 229 #undef CONFIG_ENV_IS_IN_NVRAM
 230 #undef CONFIG_ENV_IS_IN_EEPROM
 231 #elif defined CONFIG_ENV_IS_IN_NVRAM
 232 #undef CONFIG_ENV_IS_IN_FLASH
 233 #undef CONFIG_ENV_IS_IN_EEPROM
 234 #elif defined CONFIG_ENV_IS_IN_EEPROM
 235 #undef CONFIG_ENV_IS_IN_NVRAM
 236 #undef CONFIG_ENV_IS_IN_FLASH
 237 #endif
 238
 239 #ifndef CONFIG_SYS_JFFS2_FIRST_SECTOR
 240 #define CONFIG_SYS_JFFS2_FIRST_SECTOR   0
 241 #endif
 242 #ifndef CONFIG_SYS_JFFS2_FIRST_BANK
 243 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 244 #endif
 245 #ifndef CONFIG_SYS_JFFS2_NUM_BANKS
 246 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 247 #endif
 248 #define CONFIG_SYS_JFFS2_LAST_BANK (CONFIG_SYS_JFFS2_FIRST_BANK + CONFIG_SYS_JFFS2_NUM_BANKS - 1)
 249
 250 /*
 251  * Memory map
 252  */
 253 #define CONFIG_SYS_MBAR         0xF0000000
 254 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 255 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 256 #define CONFIG_SYS_SRAM_BASE            (CONFIG_SYS_MBAR + 0x20000)
 257 #define CONFIG_SYS_SRAM_SIZE            0x8000
 258
 259 /* Use SRAM until RAM will be available */
 260 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_MBAR + 0x20000)
 261 #define CONFIG_SYS_INIT_RAM_END 0x8000  /* End of used area in DPRAM */
 262
 263 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 264 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 265 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 266
 267 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 268 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 269 #   define CONFIG_SYS_RAMBOOT           1
 270 #endif
 271
 272 #define CONFIG_SYS_MONITOR_LEN          (256 << 10) /* Reserve 256 kB for Monitor   */
 273 #define CONFIG_SYS_MALLOC_LEN           (128 << 10) /* Reserve 128 kB for malloc()  */
 274 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)   /* Initial Memory map for Linux */
 275
 276 /* SDRAM configuration */
 277 #define CONFIG_SYS_SDRAM_TOTAL_BANKS            2
 278 #define CONFIG_SYS_SDRAM_SPD_I2C_ADDR           0x51            /* 7bit */
 279 #define CONFIG_SYS_SDRAM_SPD_SIZE               0x40
 280 #define CONFIG_SYS_SDRAM_CAS_LATENCY            4               /* (CL=2)x2 */
 281
 282 /* SDRAM drive strength register */
 283 #define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
 284                                          (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
 285                                          (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
 286                                          (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
 287                                          (DRIVE_STRENGTH_LOW  << SDRAMDS_SBD_SHIFT))
 288
 289 /*
 290  * Ethernet configuration
 291  */
 292 #define CONFIG_MPC8220_FEC      1
 293 #define CONFIG_FEC_10MBIT       1 /* Workaround for FEC 100Mbit problem */
 294 #define CONFIG_PHY_ADDR         0x18
 295
 296
 297 /*
 298  * Miscellaneous configurable options
 299  */
 300 #define CONFIG_SYS_LONGHELP                         /* undef to save memory     */
 301 #define CONFIG_SYS_PROMPT               "=> "       /* Monitor Command Prompt   */
 302 #if defined(CONFIG_CMD_KGDB)
 303 #define CONFIG_SYS_CBSIZE               1024        /* Console I/O Buffer Size  */
 304 #else
 305 #define CONFIG_SYS_CBSIZE               256         /* Console I/O Buffer Size  */
 306 #endif
 307 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 308 #define CONFIG_SYS_MAXARGS              16          /* max number of command args   */
 309 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
 310
 311 #define CONFIG_SYS_MEMTEST_START        0x00100000  /* memtest works on */
 312 #define CONFIG_SYS_MEMTEST_END          0x00f00000  /* 1 ... 15 MB in DRAM  */
 313
 314 #define CONFIG_SYS_LOAD_ADDR            0x100000    /* default load address */
 315
 316 #define CONFIG_SYS_HZ                   1000        /* decrementer freq: 1 ms ticks */
 317
 318 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8220 CPUs */
 319 #if defined(CONFIG_CMD_KGDB)
 320 #  define CONFIG_SYS_CACHELINE_SHIFT    5   /* log base 2 of the above value */
 321 #endif
 322
 323 /*
 324  * Various low-level settings
 325  */
 326 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 327 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 328
 329 #endif /* __CONFIG_H */