include/configs/Yukon8220.h

   1 /*
   2  * (C) Copyright 2004
   3  * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31 #define CONFIG_MPC8220          1
  32 #define CONFIG_YUKON8220        1       /* ... on Yukon board   */
  33
  34 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  35
  36 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  37 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  38
  39 /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
  40    determine the CPU speed. */
  41 #define CONFIG_SYS_MPC8220_CLKIN        30000000/* ... running at 30MHz */
  42 #define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
  43
  44 /*
  45  * Serial console configuration
  46  */
  47
  48 /* Define this for PSC console
  49 #define CONFIG_PSC_CONSOLE      1
  50 */
  51
  52 #define CONFIG_EXTUART_CONSOLE  1
  53
  54 #ifdef CONFIG_EXTUART_CONSOLE
  55 #   define CONFIG_CONS_INDEX    1
  56 #   define CONFIG_SYS_NS16550_SERIAL
  57 #   define CONFIG_SYS_NS16550
  58 #   define CONFIG_SYS_NS16550_REG_SIZE 1
  59 #   define CONFIG_SYS_NS16550_COM1      (CONFIG_SYS_CPLD_BASE + 0x1008)
  60 #   define CONFIG_SYS_NS16550_CLK       18432000
  61 #endif
  62
  63 #define CONFIG_BAUDRATE         115200      /* ... at 115200 bps */
  64
  65 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  66
  67 #define CONFIG_TIMESTAMP                        /* Print image info with timestamp */
  68
  69
  70 /*
  71  * BOOTP options
  72  */
  73 #define CONFIG_BOOTP_BOOTFILESIZE
  74 #define CONFIG_BOOTP_BOOTPATH
  75 #define CONFIG_BOOTP_GATEWAY
  76 #define CONFIG_BOOTP_HOSTNAME
  77
  78
  79 /*
  80  * Command line configuration.
  81  */
  82 #include <config_cmd_default.h>
  83
  84 #define CONFIG_CMD_BOOTD
  85 #define CONFIG_CMD_CACHE
  86 #define CONFIG_CMD_DHCP
  87 #define CONFIG_CMD_DIAG
  88 #define CONFIG_CMD_EEPROM
  89 #define CONFIG_CMD_ELF
  90 #define CONFIG_CMD_I2C
  91 #define CONFIG_CMD_NET
  92 #define CONFIG_CMD_NFS
  93 #define CONFIG_CMD_PCI
  94 #define CONFIG_CMD_PING
  95 #define CONFIG_CMD_REGINFO
  96 #define CONFIG_CMD_SDRAM
  97 #define CONFIG_CMD_SNTP
  98
  99
 100 #define CONFIG_MII
 101
 102 /*
 103  * Autobooting
 104  */
 105 #define CONFIG_BOOTDELAY        5    /* autoboot after 5 seconds */
 106 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
 107 #define CONFIG_ETHADDR          00:e0:0c:bc:e0:60
 108 #define CONFIG_HAS_ETH1
 109 #define CONFIG_ETH1ADDR         00:e0:0c:bc:e0:61
 110 #define CONFIG_IPADDR           192.162.1.2
 111 #define CONFIG_NETMASK          255.255.255.0
 112 #define CONFIG_SERVERIP         192.162.1.1
 113 #define CONFIG_GATEWAYIP        192.162.1.1
 114 #define CONFIG_HOSTNAME         yukon
 115 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 116
 117
 118 /*
 119  * I2C configuration
 120  */
 121 #define CONFIG_HARD_I2C         1
 122 #define CONFIG_SYS_I2C_MODULE           1
 123
 124 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 125 #define CONFIG_SYS_I2C_SLAVE            0x7F
 126
 127 /*
 128  * EEPROM configuration
 129  */
 130 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x52    /* 1011000xb */
 131 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 132 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 133 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
 134 /*
 135 #define CONFIG_ENV_IS_IN_EEPROM 1
 136 #define CONFIG_ENV_OFFSET               0
 137 #define CONFIG_ENV_SIZE         256
 138 */
 139
 140 /* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
 141    else undefined it will boot from Intel Strata flash */
 142 #define CONFIG_SYS_AMD_BOOT             1
 143
 144 /*
 145  * Flexbus Chipselect configuration
 146  */
 147 #if defined (CONFIG_SYS_AMD_BOOT)
 148 #define CONFIG_SYS_CS0_BASE             0xfff0
 149 #define CONFIG_SYS_CS0_MASK             0x00080000  /* 512 KB */
 150 #define CONFIG_SYS_CS0_CTRL             0x003f0d40
 151
 152 #define CONFIG_SYS_CS1_BASE             0xfe00
 153 #define CONFIG_SYS_CS1_MASK             0x01000000  /* 16 MB */
 154 #define CONFIG_SYS_CS1_CTRL             0x003f1540
 155 #else
 156 #define CONFIG_SYS_CS0_BASE             0xff00
 157 #define CONFIG_SYS_CS0_MASK             0x01000000  /* 16 MB */
 158 #define CONFIG_SYS_CS0_CTRL             0x003f1540
 159
 160 #define CONFIG_SYS_CS1_BASE             0xfe08
 161 #define CONFIG_SYS_CS1_MASK             0x00080000  /* 512 KB */
 162 #define CONFIG_SYS_CS1_CTRL             0x003f0d40
 163 #endif
 164
 165 #define CONFIG_SYS_CS2_BASE             0xf100
 166 #define CONFIG_SYS_CS2_MASK             0x00040000
 167 #define CONFIG_SYS_CS2_CTRL             0x003f1140
 168
 169 #define CONFIG_SYS_CS3_BASE             0xf200
 170 #define CONFIG_SYS_CS3_MASK             0x00040000
 171 #define CONFIG_SYS_CS3_CTRL             0x003f1100
 172
 173
 174 #define CONFIG_SYS_FLASH0_BASE          (CONFIG_SYS_CS0_BASE << 16)
 175 #define CONFIG_SYS_FLASH1_BASE          (CONFIG_SYS_CS1_BASE << 16)
 176
 177 #if defined (CONFIG_SYS_AMD_BOOT)
 178 #define CONFIG_SYS_AMD_BASE             CONFIG_SYS_FLASH0_BASE
 179 #define CONFIG_SYS_INTEL_BASE           CONFIG_SYS_FLASH1_BASE + 0xf00000
 180 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_AMD_BASE
 181 #else
 182 #define CONFIG_SYS_INTEL_BASE           CONFIG_SYS_FLASH0_BASE + 0xf00000
 183 #define CONFIG_SYS_AMD_BASE             CONFIG_SYS_FLASH1_BASE
 184 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_INTEL_BASE
 185 #endif
 186
 187 #define CONFIG_SYS_CPLD_BASE            (CONFIG_SYS_CS2_BASE << 16)
 188 #define CONFIG_SYS_FPGA_BASE            (CONFIG_SYS_CS3_BASE << 16)
 189
 190
 191 #define CONFIG_SYS_MAX_FLASH_BANKS      4       /* max num of memory banks      */
 192 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 193
 194 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 195 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 196 #define CONFIG_SYS_FLASH_LOCK_TOUT      5       /* Timeout for Flash Set Lock Bit (in ms) */
 197 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 198 #define CONFIG_SYS_FLASH_PROTECTION             /* "Real" (hardware) sectors protection */
 199
 200 #define PHYS_AMD_SECT_SIZE      0x00010000 /*  64 KB sectors (x2) */
 201 #define PHYS_INTEL_SECT_SIZE    0x00020000 /* 128 KB sectors (x2) */
 202
 203 #define CONFIG_SYS_FLASH_CHECKSUM
 204 /*
 205  * Environment settings
 206  */
 207 #define CONFIG_ENV_IS_IN_FLASH  1
 208 #if defined (CONFIG_SYS_AMD_BOOT)
 209 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
 210 #define CONFIG_ENV_SIZE         PHYS_AMD_SECT_SIZE
 211 #define CONFIG_ENV_SECT_SIZE    PHYS_AMD_SECT_SIZE
 212 #define CONFIG_ENV1_ADDR                (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
 213 #define CONFIG_ENV1_SIZE                PHYS_INTEL_SECT_SIZE
 214 #define CONFIG_ENV1_SECT_SIZE   PHYS_INTEL_SECT_SIZE
 215 #else
 216 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
 217 #define CONFIG_ENV_SIZE         PHYS_INTEL_SECT_SIZE
 218 #define CONFIG_ENV_SECT_SIZE    PHYS_INTEL_SECT_SIZE
 219 #define CONFIG_ENV1_ADDR                (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
 220 #define CONFIG_ENV1_SIZE                PHYS_AMD_SECT_SIZE
 221 #define CONFIG_ENV1_SECT_SIZE   PHYS_AMD_SECT_SIZE
 222 #endif
 223
 224 #define CONFIG_ENV_OVERWRITE    1
 225
 226 #if defined CONFIG_ENV_IS_IN_FLASH
 227 #undef CONFIG_ENV_IS_IN_NVRAM
 228 #undef CONFIG_ENV_IS_IN_EEPROM
 229 #elif defined CONFIG_ENV_IS_IN_NVRAM
 230 #undef CONFIG_ENV_IS_IN_FLASH
 231 #undef CONFIG_ENV_IS_IN_EEPROM
 232 #elif defined CONFIG_ENV_IS_IN_EEPROM
 233 #undef CONFIG_ENV_IS_IN_NVRAM
 234 #undef CONFIG_ENV_IS_IN_FLASH
 235 #endif
 236
 237 #ifndef CONFIG_SYS_JFFS2_FIRST_SECTOR
 238 #define CONFIG_SYS_JFFS2_FIRST_SECTOR   0
 239 #endif
 240 #ifndef CONFIG_SYS_JFFS2_FIRST_BANK
 241 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 242 #endif
 243 #ifndef CONFIG_SYS_JFFS2_NUM_BANKS
 244 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 245 #endif
 246 #define CONFIG_SYS_JFFS2_LAST_BANK (CONFIG_SYS_JFFS2_FIRST_BANK + CONFIG_SYS_JFFS2_NUM_BANKS - 1)
 247
 248 /*
 249  * Memory map
 250  */
 251 #define CONFIG_SYS_MBAR         0xF0000000
 252 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 253 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 254 #define CONFIG_SYS_SRAM_BASE            (CONFIG_SYS_MBAR + 0x20000)
 255 #define CONFIG_SYS_SRAM_SIZE            0x8000
 256
 257 /* Use SRAM until RAM will be available */
 258 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_MBAR + 0x20000)
 259 #define CONFIG_SYS_INIT_RAM_SIZE        0x8000  /* Size of used area in DPRAM */
 260
 261 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 262 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 263
 264 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 265 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 266 #   define CONFIG_SYS_RAMBOOT           1
 267 #endif
 268
 269 #define CONFIG_SYS_MONITOR_LEN          (256 << 10) /* Reserve 256 kB for Monitor   */
 270 #define CONFIG_SYS_MALLOC_LEN           (128 << 10) /* Reserve 128 kB for malloc()  */
 271 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)   /* Initial Memory map for Linux */
 272
 273 /* SDRAM configuration */
 274 #define CONFIG_SYS_SDRAM_TOTAL_BANKS            2
 275 #define CONFIG_SYS_SDRAM_SPD_I2C_ADDR           0x51            /* 7bit */
 276 #define CONFIG_SYS_SDRAM_SPD_SIZE               0x40
 277 #define CONFIG_SYS_SDRAM_CAS_LATENCY            4               /* (CL=2)x2 */
 278
 279 /* SDRAM drive strength register */
 280 #define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
 281                                          (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
 282                                          (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
 283                                          (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
 284                                          (DRIVE_STRENGTH_LOW  << SDRAMDS_SBD_SHIFT))
 285
 286 /*
 287  * Ethernet configuration
 288  */
 289 #define CONFIG_MPC8220_FEC      1
 290 #define CONFIG_FEC_10MBIT       1 /* Workaround for FEC 100Mbit problem */
 291 #define CONFIG_PHY_ADDR         0x18
 292
 293
 294 /*
 295  * Miscellaneous configurable options
 296  */
 297 #define CONFIG_SYS_LONGHELP                         /* undef to save memory     */
 298 #define CONFIG_SYS_PROMPT               "=> "       /* Monitor Command Prompt   */
 299 #if defined(CONFIG_CMD_KGDB)
 300 #define CONFIG_SYS_CBSIZE               1024        /* Console I/O Buffer Size  */
 301 #else
 302 #define CONFIG_SYS_CBSIZE               256         /* Console I/O Buffer Size  */
 303 #endif
 304 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 305 #define CONFIG_SYS_MAXARGS              16          /* max number of command args   */
 306 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
 307
 308 #define CONFIG_SYS_MEMTEST_START        0x00100000  /* memtest works on */
 309 #define CONFIG_SYS_MEMTEST_END          0x00f00000  /* 1 ... 15 MB in DRAM  */
 310
 311 #define CONFIG_SYS_LOAD_ADDR            0x100000    /* default load address */
 312
 313 #define CONFIG_SYS_HZ                   1000        /* decrementer freq: 1 ms ticks */
 314
 315 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8220 CPUs */
 316 #if defined(CONFIG_CMD_KGDB)
 317 #  define CONFIG_SYS_CACHELINE_SHIFT    5   /* log base 2 of the above value */
 318 #endif
 319
 320 /*
 321  * Various low-level settings
 322  */
 323 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 324 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 325
 326 #endif /* __CONFIG_H */