include/configs/ZPC1900.h

   1 /*
   2  * Copyright (C) 2003-2005 Arabella Software Ltd.
   3  * Yuli Barcohen <yuli@arabellasw.com>
   4  *
   5  * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
   6  * This port was developed and tested on Revision C board.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU      */
  31 #define CONFIG_ZPC1900          1       /* ...on Zephyr ZPC.1900 board */
  32 #define CPU_ID_STR              "MPC8265"
  33 #define CONFIG_CPM2             1       /* Has a CPM2 */
  34
  35 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
  36 #define CONFIG_ENV_OVERWRITE
  37
  38 /*
  39  * Select serial console configuration
  40  *
  41  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  42  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  43  * for SCC).
  44  */
  45 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  46 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  47 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  48 #define CONFIG_CONS_INDEX       1       /* SMC1 is used for console  */
  49
  50 /*
  51  * Select ethernet configuration
  52  *
  53  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  54  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  55  * SCC, 1-3 for FCC)
  56  *
  57  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  58  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  59  * must be unset.
  60  */
  61 #undef  CONFIG_ETHER_ON_SCC             /* Ethernet is not on SCC */
  62 #define CONFIG_ETHER_ON_FCC             /* Ethernet is on FCC     */
  63 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  64
  65 #ifdef CONFIG_ETHER_ON_FCC
  66
  67 #define CONFIG_ETHER_INDEX      2       /* FCC2 is used for Ethernet */
  68
  69 #if (CONFIG_ETHER_INDEX == 2)
  70 /*
  71  * - Rx clock is CLK13
  72  * - Tx clock is CLK14
  73  * - Select bus for bd/buffers (see 28-13)
  74  * - Full duplex
  75  */
  76 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  77 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  78 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  79 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
  80
  81 #endif /* CONFIG_ETHER_INDEX */
  82
  83 #define CONFIG_MII                      /* MII PHY management        */
  84 #define CONFIG_BITBANGMII               /* Bit-banged MDIO interface */
  85 /*
  86  * GPIO pins used for bit-banged MII communications
  87  */
  88 #define MDIO_PORT               2       /* Port C */
  89 #define MDIO_DECLARE            volatile ioport_t *iop = ioport_addr ( \
  90                                         (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
  91 #define MDC_DECLARE             MDIO_DECLARE
  92
  93 #define MDIO_ACTIVE             (iop->pdir |=  0x00400000)
  94 #define MDIO_TRISTATE           (iop->pdir &= ~0x00400000)
  95 #define MDIO_READ               ((iop->pdat &  0x00400000) != 0)
  96
  97 #define MDIO(bit)               if(bit) iop->pdat |=  0x00400000; \
  98                                 else    iop->pdat &= ~0x00400000
  99
 100 #define MDC(bit)                if(bit) iop->pdat |=  0x00200000; \
 101                                 else    iop->pdat &= ~0x00200000
 102
 103 #define MIIDELAY                udelay(1)
 104
 105 #endif /* CONFIG_ETHER_ON_FCC */
 106
 107 #ifndef CONFIG_8260_CLKIN
 108 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
 109 #endif
 110
 111 #define CONFIG_BAUDRATE         38400
 112
 113
 114 /*
 115  * BOOTP options
 116  */
 117 #define CONFIG_BOOTP_BOOTFILESIZE
 118 #define CONFIG_BOOTP_BOOTPATH
 119 #define CONFIG_BOOTP_GATEWAY
 120 #define CONFIG_BOOTP_HOSTNAME
 121
 122
 123 /*
 124  * Command line configuration.
 125  */
 126 #include <config_cmd_default.h>
 127
 128 #define CONFIG_CMD_ASKENV
 129 #define CONFIG_CMD_DHCP
 130 #define CONFIG_CMD_IMMAP
 131 #define CONFIG_CMD_MII
 132 #define CONFIG_CMD_PING
 133
 134
 135 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 136 #define CONFIG_BOOTCOMMAND      "dhcp;bootm"    /* autoboot command */
 137 #define CONFIG_BOOTARGS         "root=/dev/nfs rw ip=:::::eth0:dhcp"
 138
 139 #if defined(CONFIG_CMD_KGDB)
 140 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 141 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 142 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 143 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 144 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 145 #endif
 146
 147 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 148 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 149
 150 /*
 151  * Miscellaneous configurable options
 152  */
 153 #define CONFIG_SYS_HUSH_PARSER
 154 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 155 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 156 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 157 #if defined(CONFIG_CMD_KGDB)
 158 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 159 #else
 160 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 161 #endif
 162 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size  */
 163 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 164 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size  */
 165
 166 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 167 #define CONFIG_SYS_MEMTEST_END          0x03800000      /* 1 ... 56 MB in DRAM  */
 168
 169 #define CONFIG_SYS_LOAD_ADDR            0x400000        /* default load address */
 170
 171 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 172
 173 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 174
 175 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 176 #define CONFIG_SYS_SDRAM_SIZE           64
 177
 178 #define CONFIG_SYS_IMMR         0xF0000000
 179 #define CONFIG_SYS_LSDRAM_BASE          0xFC000000
 180 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 181 #define CONFIG_SYS_BCSR         0xFEA00000
 182 #define CONFIG_SYS_EEPROM               0xFEB00000
 183 #define CONFIG_SYS_FLSIMM_BASE          0xFF000000
 184
 185 #define CONFIG_SYS_FLASH_CFI
 186 #define CONFIG_FLASH_CFI_DRIVER
 187 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of flash banks       */
 188 #define CONFIG_SYS_MAX_FLASH_SECT       32      /* max num of sects on one chip */
 189
 190 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLSIMM_BASE }
 191
 192 #define BCSR_PCI_MODE           0x01
 193
 194 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 195 #define CONFIG_SYS_INIT_RAM_END 0x4000  /* End of used area in DPRAM    */
 196 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 197 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 198 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 199
 200 /* Hard reset configuration word */
 201 #define CONFIG_SYS_HRCW_MASTER          (HRCW_EBM | HRCW_BPS01| HRCW_CIP          |\
 202                                  HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
 203                                  HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10     |\
 204                                  HRCW_MODCK_H0111                          \
 205                                 ) /* 0x16848207 */
 206 /* No slaves */
 207 #define CONFIG_SYS_HRCW_SLAVE1          0
 208 #define CONFIG_SYS_HRCW_SLAVE2          0
 209 #define CONFIG_SYS_HRCW_SLAVE3          0
 210 #define CONFIG_SYS_HRCW_SLAVE4          0
 211 #define CONFIG_SYS_HRCW_SLAVE5          0
 212 #define CONFIG_SYS_HRCW_SLAVE6          0
 213 #define CONFIG_SYS_HRCW_SLAVE7          0
 214
 215 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 216 #define BOOTFLAG_WARM           0x02    /* Software reboot                  */
 217
 218 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
 219 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 220 #define CONFIG_SYS_RAMBOOT
 221 #endif
 222
 223 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 224 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve 4 MB for malloc()    */
 225 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 226
 227 #if !defined(CONFIG_ENV_IS_IN_FLASH) && !defined(CONFIG_ENV_IS_IN_NVRAM)
 228 #define CONFIG_ENV_IS_IN_NVRAM  1
 229 #endif
 230
 231 #ifdef CONFIG_ENV_IS_IN_FLASH
 232 #  define CONFIG_ENV_SECT_SIZE  0x10000
 233 #  define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 234 #else
 235 #  define CONFIG_ENV_ADDR               (CONFIG_SYS_EEPROM + 0x400)
 236 #  define CONFIG_ENV_SIZE               0x1000
 237 #  define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
 238 #endif
 239
 240 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU */
 241 #if defined(CONFIG_CMD_KGDB)
 242 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 243 #endif
 244
 245 #define CONFIG_SYS_HID0_INIT            (HID0_ICFI)
 246 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 247
 248 #define CONFIG_SYS_HID2         0
 249
 250 #define CONFIG_SYS_SIUMCR               0x42200000
 251 #define CONFIG_SYS_SYPCR                0xFFFFFFC3
 252 #define CONFIG_SYS_BCR                  0x90000000
 253 #define CONFIG_SYS_SCCR         SCCR_DFBRG01
 254
 255 #define CONFIG_SYS_RMR                  RMR_CSRE
 256 #define CONFIG_SYS_TMCNTSC              (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 257 #define CONFIG_SYS_PISCR                (PISCR_PS|PISCR_PTF|PISCR_PTE)
 258 #define CONFIG_SYS_RCCR         0
 259
 260 #define CONFIG_SYS_PSDMR                /* 0x834DA43B */0x014DA43A
 261 #define CONFIG_SYS_PSRT         0x0F/* 0x0C */
 262 #define CONFIG_SYS_LSDMR                0x0085A562
 263 #define CONFIG_SYS_LSRT         0x0F
 264 #define CONFIG_SYS_MPTPR                0x4000
 265
 266 #define CONFIG_SYS_PSDRAM_BR            (CONFIG_SYS_SDRAM_BASE | 0x00000041)
 267 #define CONFIG_SYS_PSDRAM_OR            0xFC0028C0
 268 #define CONFIG_SYS_LSDRAM_BR            (CONFIG_SYS_LSDRAM_BASE | 0x00001861)
 269 #define CONFIG_SYS_LSDRAM_OR            0xFF803480
 270
 271 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | 0x00000801)
 272 #define CONFIG_SYS_OR0_PRELIM           0xFFE00856
 273 #define CONFIG_SYS_BR5_PRELIM           (CONFIG_SYS_EEPROM | 0x00000801)
 274 #define CONFIG_SYS_OR5_PRELIM           0xFFFF03F6
 275 #define CONFIG_SYS_BR6_PRELIM           (CONFIG_SYS_FLSIMM_BASE | 0x00001801)
 276 #define CONFIG_SYS_OR6_PRELIM           0xFF000856
 277 #define CONFIG_SYS_BR7_PRELIM           (CONFIG_SYS_BCSR | 0x00000801)
 278 #define CONFIG_SYS_OR7_PRELIM           0xFFFF83F6
 279
 280 #define CONFIG_SYS_RESET_ADDRESS        0xC0000000
 281
 282 #endif /* __CONFIG_H */