include/configs/ZPC1900.h

   1 /*
   2  * Copyright (C) 2003-2005 Arabella Software Ltd.
   3  * Yuli Barcohen <yuli@arabellasw.com>
   4  *
   5  * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
   6  * This port was developed and tested on Revision C board.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU      */
  15 #define CONFIG_ZPC1900          1       /* ...on Zephyr ZPC.1900 board */
  16
  17 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  18
  19 #define CPU_ID_STR              "MPC8265"
  20 #define CONFIG_CPM2             1       /* Has a CPM2 */
  21
  22 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
  23 #define CONFIG_ENV_OVERWRITE
  24
  25 /*
  26  * Select serial console configuration
  27  *
  28  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  29  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  30  * for SCC).
  31  */
  32 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  33 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  34 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  35 #define CONFIG_CONS_INDEX       1       /* SMC1 is used for console  */
  36
  37 /*
  38  * Select ethernet configuration
  39  *
  40  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  41  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  42  * SCC, 1-3 for FCC)
  43  *
  44  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  45  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  46  * must be unset.
  47  */
  48 #undef  CONFIG_ETHER_ON_SCC             /* Ethernet is not on SCC */
  49 #define CONFIG_ETHER_ON_FCC             /* Ethernet is on FCC     */
  50 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  51
  52 #ifdef CONFIG_ETHER_ON_FCC
  53
  54 #define CONFIG_ETHER_INDEX      2       /* FCC2 is used for Ethernet */
  55
  56 #if (CONFIG_ETHER_INDEX == 2)
  57 /*
  58  * - Rx clock is CLK13
  59  * - Tx clock is CLK14
  60  * - Select bus for bd/buffers (see 28-13)
  61  * - Full duplex
  62  */
  63 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  64 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  65 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  66 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
  67
  68 #endif /* CONFIG_ETHER_INDEX */
  69
  70 #define CONFIG_MII                      /* MII PHY management        */
  71 #define CONFIG_BITBANGMII               /* Bit-banged MDIO interface */
  72 /*
  73  * GPIO pins used for bit-banged MII communications
  74  */
  75 #define MDIO_PORT               2       /* Port C */
  76 #define MDIO_DECLARE            volatile ioport_t *iop = ioport_addr ( \
  77                                         (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
  78 #define MDC_DECLARE             MDIO_DECLARE
  79
  80 #define MDIO_ACTIVE             (iop->pdir |=  0x00400000)
  81 #define MDIO_TRISTATE           (iop->pdir &= ~0x00400000)
  82 #define MDIO_READ               ((iop->pdat &  0x00400000) != 0)
  83
  84 #define MDIO(bit)               if(bit) iop->pdat |=  0x00400000; \
  85                                 else    iop->pdat &= ~0x00400000
  86
  87 #define MDC(bit)                if(bit) iop->pdat |=  0x00200000; \
  88                                 else    iop->pdat &= ~0x00200000
  89
  90 #define MIIDELAY                udelay(1)
  91
  92 #endif /* CONFIG_ETHER_ON_FCC */
  93
  94 #ifndef CONFIG_8260_CLKIN
  95 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
  96 #endif
  97
  98 #define CONFIG_BAUDRATE         38400
  99
 100
 101 /*
 102  * BOOTP options
 103  */
 104 #define CONFIG_BOOTP_BOOTFILESIZE
 105 #define CONFIG_BOOTP_BOOTPATH
 106 #define CONFIG_BOOTP_GATEWAY
 107 #define CONFIG_BOOTP_HOSTNAME
 108
 109
 110 /*
 111  * Command line configuration.
 112  */
 113 #include <config_cmd_default.h>
 114
 115 #define CONFIG_CMD_ASKENV
 116 #define CONFIG_CMD_DHCP
 117 #define CONFIG_CMD_IMMAP
 118 #define CONFIG_CMD_MII
 119 #define CONFIG_CMD_PING
 120
 121
 122 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 123 #define CONFIG_BOOTCOMMAND      "dhcp;bootm"    /* autoboot command */
 124 #define CONFIG_BOOTARGS         "root=/dev/nfs rw ip=:::::eth0:dhcp"
 125
 126 #if defined(CONFIG_CMD_KGDB)
 127 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 128 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 129 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 130 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 131 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 132 #endif
 133
 134 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 135 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 136
 137 /*
 138  * Miscellaneous configurable options
 139  */
 140 #define CONFIG_SYS_HUSH_PARSER
 141 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 142 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 143 #if defined(CONFIG_CMD_KGDB)
 144 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 145 #else
 146 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 147 #endif
 148 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size  */
 149 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 150 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size  */
 151
 152 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 153 #define CONFIG_SYS_MEMTEST_END          0x03800000      /* 1 ... 56 MB in DRAM  */
 154
 155 #define CONFIG_SYS_LOAD_ADDR            0x400000        /* default load address */
 156
 157 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 158
 159 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 160
 161 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 162 #define CONFIG_SYS_SDRAM_SIZE           64
 163
 164 #define CONFIG_SYS_IMMR         0xF0000000
 165 #define CONFIG_SYS_LSDRAM_BASE          0xFC000000
 166 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 167 #define CONFIG_SYS_BCSR         0xFEA00000
 168 #define CONFIG_SYS_EEPROM               0xFEB00000
 169 #define CONFIG_SYS_FLSIMM_BASE          0xFF000000
 170
 171 #define CONFIG_SYS_FLASH_CFI
 172 #define CONFIG_FLASH_CFI_DRIVER
 173 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of flash banks       */
 174 #define CONFIG_SYS_MAX_FLASH_SECT       32      /* max num of sects on one chip */
 175
 176 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLSIMM_BASE }
 177
 178 #define BCSR_PCI_MODE           0x01
 179
 180 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 181 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM   */
 182 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 183 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 184
 185 /* Hard reset configuration word */
 186 #define CONFIG_SYS_HRCW_MASTER          (HRCW_EBM | HRCW_BPS01| HRCW_CIP          |\
 187                                  HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
 188                                  HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10     |\
 189                                  HRCW_MODCK_H0111                          \
 190                                 ) /* 0x16848207 */
 191 /* No slaves */
 192 #define CONFIG_SYS_HRCW_SLAVE1          0
 193 #define CONFIG_SYS_HRCW_SLAVE2          0
 194 #define CONFIG_SYS_HRCW_SLAVE3          0
 195 #define CONFIG_SYS_HRCW_SLAVE4          0
 196 #define CONFIG_SYS_HRCW_SLAVE5          0
 197 #define CONFIG_SYS_HRCW_SLAVE6          0
 198 #define CONFIG_SYS_HRCW_SLAVE7          0
 199
 200 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 201
 202 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 203 #define CONFIG_SYS_RAMBOOT
 204 #endif
 205
 206 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 207 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve 4 MB for malloc()    */
 208 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 209
 210 #if !defined(CONFIG_ENV_IS_IN_FLASH) && !defined(CONFIG_ENV_IS_IN_NVRAM)
 211 #define CONFIG_ENV_IS_IN_NVRAM  1
 212 #endif
 213
 214 #ifdef CONFIG_ENV_IS_IN_FLASH
 215 #  define CONFIG_ENV_SECT_SIZE  0x10000
 216 #  define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 217 #else
 218 #  define CONFIG_ENV_ADDR               (CONFIG_SYS_EEPROM + 0x400)
 219 #  define CONFIG_ENV_SIZE               0x1000
 220 #  define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
 221 #endif
 222
 223 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU */
 224 #if defined(CONFIG_CMD_KGDB)
 225 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 226 #endif
 227
 228 #define CONFIG_SYS_HID0_INIT            (HID0_ICFI)
 229 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 230
 231 #define CONFIG_SYS_HID2         0
 232
 233 #define CONFIG_SYS_SIUMCR               0x42200000
 234 #define CONFIG_SYS_SYPCR                0xFFFFFFC3
 235 #define CONFIG_SYS_BCR                  0x90000000
 236 #define CONFIG_SYS_SCCR         SCCR_DFBRG01
 237
 238 #define CONFIG_SYS_RMR                  RMR_CSRE
 239 #define CONFIG_SYS_TMCNTSC              (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 240 #define CONFIG_SYS_PISCR                (PISCR_PS|PISCR_PTF|PISCR_PTE)
 241 #define CONFIG_SYS_RCCR         0
 242
 243 #define CONFIG_SYS_PSDMR                /* 0x834DA43B */0x014DA43A
 244 #define CONFIG_SYS_PSRT         0x0F/* 0x0C */
 245 #define CONFIG_SYS_LSDMR                0x0085A562
 246 #define CONFIG_SYS_LSRT         0x0F
 247 #define CONFIG_SYS_MPTPR                0x4000
 248
 249 #define CONFIG_SYS_PSDRAM_BR            (CONFIG_SYS_SDRAM_BASE | 0x00000041)
 250 #define CONFIG_SYS_PSDRAM_OR            0xFC0028C0
 251 #define CONFIG_SYS_LSDRAM_BR            (CONFIG_SYS_LSDRAM_BASE | 0x00001861)
 252 #define CONFIG_SYS_LSDRAM_OR            0xFF803480
 253
 254 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | 0x00000801)
 255 #define CONFIG_SYS_OR0_PRELIM           0xFFE00856
 256 #define CONFIG_SYS_BR5_PRELIM           (CONFIG_SYS_EEPROM | 0x00000801)
 257 #define CONFIG_SYS_OR5_PRELIM           0xFFFF03F6
 258 #define CONFIG_SYS_BR6_PRELIM           (CONFIG_SYS_FLSIMM_BASE | 0x00001801)
 259 #define CONFIG_SYS_OR6_PRELIM           0xFF000856
 260 #define CONFIG_SYS_BR7_PRELIM           (CONFIG_SYS_BCSR | 0x00000801)
 261 #define CONFIG_SYS_OR7_PRELIM           0xFFFF83F6
 262
 263 #define CONFIG_SYS_RESET_ADDRESS        0xC0000000
 264
 265 #endif /* __CONFIG_H */