include/configs/ZUMA.h

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 #define CONFIG_SYS_GT_6426x        GT_64260 /* with a 64260 system controller */
  16 #define CONFIG_ETHER_PORT_MII   /* use two MII ports */
  17 #define CONFIG_INTEL_LXT97X     /* Intel LXT97X phy */
  18
  19 #ifndef __ASSEMBLY__
  20 #include <galileo/core.h>
  21 #endif
  22
  23 #include "../board/evb64260/local.h"
  24
  25 #define CONFIG_EVB64260         1       /* this is an EVB64260 board    */
  26 #define CONFIG_ZUMA_V2          1       /* always define this for ZUMA v2 */
  27
  28 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  29
  30 /* #define CONFIG_ZUMA_V2_OLD   1 */    /* backwards compat for old V2 board */
  31
  32 #define CONFIG_BAUDRATE         38400   /* console baudrate = 38400     */
  33
  34 #define CONFIG_ECC                      /* enable ECC support */
  35
  36 #define CONFIG_750CX                    /* we have a 750CX/CXe (override local.h) */
  37
  38 /* which initialization functions to call for this board */
  39 #define CONFIG_MISC_INIT_R
  40 #define CONFIG_BOARD_EARLY_INIT_F
  41 #define CONFIG_SYS_BOARD_ASM_INIT
  42
  43 #define CONFIG_SYS_BOARD_NAME           "Zuma APv2"
  44
  45 #define CONFIG_SYS_HUSH_PARSER
  46
  47 /*
  48  * The following defines let you select what serial you want to use
  49  * for your console driver.
  50  *
  51  * what to do:
  52  * to use the DUART, undef CONFIG_MPSC.  If you have hacked a serial
  53  * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
  54  * to 0 below.
  55  *
  56  * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
  57  * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
  58  */
  59 #define CONFIG_MPSC
  60
  61 #define CONFIG_MPSC_PORT        0
  62
  63
  64 /* define this if you want to enable GT MAC filtering */
  65 #define CONFIG_GT_USE_MAC_HASH_TABLE
  66
  67 #if 1
  68 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  69 #else
  70 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  71 #endif
  72 #define CONFIG_ZERO_BOOTDELAY_CHECK
  73
  74 #undef  CONFIG_BOOTARGS
  75
  76 #define CONFIG_BOOTCOMMAND                                                      \
  77         "tftpboot && "                                                          \
  78         "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
  79         "ip=$ipaddr:$serverip:$gatewayip:"                              \
  80         "$netmask:$hostname:eth0:none panic=5 && bootm"
  81
  82 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
  83 #define CONFIG_SYS_LOADS_BAUD_CHANGE            /* allow baudrate changes       */
  84
  85 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  86 #undef  CONFIG_ALTIVEC                  /* undef to disable             */
  87
  88 /*
  89  * BOOTP options
  90  */
  91 #define CONFIG_BOOTP_SUBNETMASK
  92 #define CONFIG_BOOTP_GATEWAY
  93 #define CONFIG_BOOTP_HOSTNAME
  94 #define CONFIG_BOOTP_BOOTPATH
  95 #define CONFIG_BOOTP_BOOTFILESIZE
  96
  97 #define CONFIG_MII              /* enable MII commands */
  98
  99
 100 /*
 101  * Command line configuration.
 102  */
 103 #include <config_cmd_default.h>
 104
 105 #define CONFIG_CMD_ASKENV
 106 #define CONFIG_CMD_BSP
 107 #define CONFIG_CMD_JFFS2
 108 #define CONFIG_CMD_MII
 109 #define CONFIG_CMD_DATE
 110
 111
 112 /*
 113  * JFFS2 partitions
 114  *
 115  */
 116 /* No command line, one static partition, whole device */
 117 #undef CONFIG_CMD_MTDPARTS
 118 #define CONFIG_JFFS2_DEV                "nor0"
 119 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 120 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 121
 122 /* mtdparts command line support */
 123 /* Note: fake mtd_id used, no linux mtd map file */
 124 /*
 125 #define CONFIG_CMD_MTDPARTS
 126 #define MTDIDS_DEFAULT          "nor1=zuma-1,nor2=zuma-2"
 127 #define MTDPARTS_DEFAULT        "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
 128 */
 129
 130 /*
 131  * Miscellaneous configurable options
 132  */
 133 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 134 #if defined(CONFIG_CMD_KGDB)
 135 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 136 #else
 137 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 138 #endif
 139 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 140 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 141 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 142
 143 #define CONFIG_SYS_MEMTEST_START        0x00400000      /* memtest works on     */
 144 #define CONFIG_SYS_MEMTEST_END          0x00C00000      /* 4 ... 12 MB in DRAM  */
 145
 146 #define CONFIG_SYS_LOAD_ADDR            0x00300000      /* default load address */
 147
 148 #define CONFIG_SYS_BUS_CLK              133000000       /* 133 MHz              */
 149
 150 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 151
 152 /*
 153  * Low Level Configuration Settings
 154  * (address mappings, register initial values, etc.)
 155  * You should know what you are doing if you make changes here.
 156  */
 157
 158 /*-----------------------------------------------------------------------
 159  * Definitions for initial stack pointer and data area
 160  */
 161 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
 162 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 163 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 164 #define CONFIG_SYS_INIT_RAM_LOCK
 165
 166
 167 /*-----------------------------------------------------------------------
 168  * Start addresses for the final memory configuration
 169  * (Set up by the startup code)
 170  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 171  */
 172 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 173 #define CONFIG_SYS_FLASH_BASE           0xfff00000
 174 #define CONFIG_SYS_RESET_ADDRESS        0xfff00100
 175 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 176 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 177 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 256 kB for malloc */
 178
 179 /* areas to map different things with the GT in physical space */
 180 #define CONFIG_SYS_DRAM_BANKS           4
 181 #define CONFIG_SYS_DFL_GT_REGS          0x14000000      /* boot time GT_REGS */
 182
 183 /* What to put in the bats. */
 184 #define CONFIG_SYS_MISC_REGION_BASE     0xf0000000
 185
 186 /* Peripheral Device section */
 187 #define CONFIG_SYS_GT_REGS              0xf8000000      /* later mapped GT_REGS */
 188 #define CONFIG_SYS_DEV_BASE             0xf0000000
 189 #define CONFIG_SYS_DEV0_SIZE            _64M /* zuma flash @ 0xf000.0000*/
 190 #define CONFIG_SYS_DEV1_SIZE             _8M /* zuma IDE   @ 0xf400.0000 */
 191 #define CONFIG_SYS_DEV2_SIZE             _8M /* unused */
 192 #define CONFIG_SYS_DEV3_SIZE             _8M /* unused */
 193
 194 #define CONFIG_SYS_DEV0_PAR             0xc498243c
 195         /*     c    4     9     8     2     4     3     c */
 196         /* 33 22|2222|22 22|111 1|11 11|1 1  |     |      */
 197         /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
 198         /* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */
 199         /*  3| 0|.... ..| 1| 4 |  0 |  4 |   8 |   7 | 4  */
 200
 201 #define CONFIG_SYS_DEV1_PAR             0xc01b6ac5
 202         /*     c    0     1     b     6     a     c     5 */
 203         /* 33 22|2222|22 22|111 1|11 11|1 1  |     |      */
 204         /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
 205         /* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */
 206         /*  3| 0|.... ..| 1| 5 |  5 |  5 |   5 |   8 | 5  */
 207
 208
 209 #define CONFIG_SYS_8BIT_BOOT_PAR        0xc00b5e7c
 210
 211 #define CONFIG_SYS_MPP_CONTROL_0        0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */
 212 #define CONFIG_SYS_MPP_CONTROL_1        0x00000000 /* GPP[15:12] : GPP[11:8] */
 213 #define CONFIG_SYS_MPP_CONTROL_2        0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */
 214 #define CONFIG_SYS_MPP_CONTROL_3        0x00000000 /* GPP[31:28] (int[3:0]) */
 215                                            /* GPP[27:24] (27 is int4, rest are GPP) */
 216
 217 #define CONFIG_SYS_SERIAL_PORT_MUX      0x00001101 /* 11=MPSC1/MPSC0 01=ETH,  0=only MII */
 218 #define CONFIG_SYS_GPP_LEVEL_CONTROL    0xf8000000 /* interrupt inputs: GPP[31:27] */
 219
 220 #define CONFIG_SYS_SDRAM_CONFIG 0xe4e18200      /* 0x448 */
 221                                 /* idmas use buffer 1,1
 222                                    comm use buffer 1
 223                                    pci use buffer 0,0 (pci1->0 pci0->0)
 224                                    cpu use buffer 1 (R*18)
 225                                    normal load (see also ifdef HVL)
 226                                    standard SDRAM (see also ifdef REG)
 227                                    non staggered refresh */
 228                                 /* 31:26  25 23  20 19 18 16 */
 229                                 /* 111001 00 111 0  0  00 1 */
 230
 231                                 /* refresh count=0x200
 232                                    phy interleave disable (by default,
 233                                    set later by dram config..)
 234                                    virt interleave enable */
 235                                 /* 15 14 13:0 */
 236                                 /* 1  0  0x200 */
 237
 238 #define CONFIG_SYS_DEV0_SPACE           CONFIG_SYS_DEV_BASE
 239 #define CONFIG_SYS_DEV1_SPACE           (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
 240 #define CONFIG_SYS_DEV2_SPACE           (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
 241 #define CONFIG_SYS_DEV3_SPACE           (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
 242
 243 /*-----------------------------------------------------------------------
 244  * PCI stuff
 245  */
 246
 247 #define PCI_HOST_ADAPTER        0       /* configure ar pci adapter     */
 248 #define PCI_HOST_FORCE          1       /* configure as pci host        */
 249 #define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
 250
 251 #define CONFIG_PCI                      /* include pci support          */
 252 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 253 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 254
 255 /* PCI MEMORY MAP section */
 256 #define CONFIG_SYS_PCI0_MEM_BASE        0x80000000
 257 #define CONFIG_SYS_PCI0_MEM_SIZE        _128M
 258 #define CONFIG_SYS_PCI1_MEM_BASE        0x88000000
 259 #define CONFIG_SYS_PCI1_MEM_SIZE        _128M
 260
 261 #define CONFIG_SYS_PCI0_0_MEM_SPACE     (CONFIG_SYS_PCI0_MEM_BASE)
 262 #define CONFIG_SYS_PCI1_0_MEM_SPACE     (CONFIG_SYS_PCI1_MEM_BASE)
 263
 264 /* PCI I/O MAP section */
 265 #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
 266 #define CONFIG_SYS_PCI0_IO_SIZE _16M
 267 #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
 268 #define CONFIG_SYS_PCI1_IO_SIZE _16M
 269
 270 #define CONFIG_SYS_PCI0_IO_SPACE        (CONFIG_SYS_PCI0_IO_BASE)
 271 #define CONFIG_SYS_PCI0_IO_SPACE_PCI    0x00000000
 272 #define CONFIG_SYS_PCI1_IO_SPACE        (CONFIG_SYS_PCI1_IO_BASE)
 273 #define CONFIG_SYS_PCI1_IO_SPACE_PCI    0x00000000
 274
 275
 276 /*----------------------------------------------------------------------
 277  * Initial BAT mappings
 278  */
 279
 280 /* NOTES:
 281  * 1) GUARDED and WRITE_THRU not allowed in IBATS
 282  * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
 283  */
 284
 285 /* SDRAM */
 286 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 287 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 288 #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 289 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
 290
 291 /* init ram */
 292 #define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 293 #define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 294 #define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 295 #define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 296
 297 /* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */
 298 #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
 299 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
 300 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 301 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 302
 303 /* GT regs, bootrom, all the devices, PCI I/O */
 304 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
 305 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
 306 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 307 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 308
 309 /*
 310  * For booting Linux, the board info and command line data
 311  * have to be in the first 8 MB of memory, since this is
 312  * the maximum mapped by the Linux kernel during initialization.
 313  */
 314 #define CONFIG_SYS_BOOTMAPSZ            (8<<20) /* Initial Memory map for Linux */
 315
 316
 317 /*-----------------------------------------------------------------------
 318  * FLASH organization
 319  */
 320 #define CONFIG_SYS_MAX_FLASH_BANKS      3       /* max number of memory banks   */
 321 #define CONFIG_SYS_MAX_FLASH_SECT       130     /* max number of sectors on one chip */
 322
 323 #define CONFIG_SYS_EXTRA_FLASH_DEVICE   DEVICE0 /* extra flash at device 0 */
 324 #define CONFIG_SYS_EXTRA_FLASH_WIDTH    2       /* 16 bit */
 325
 326 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms) */
 327 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms) */
 328 #define CONFIG_SYS_FLASH_CFI            1
 329
 330 #define CONFIG_ENV_IS_IN_FLASH  1
 331 #define CONFIG_ENV_SIZE         0x1000  /* Total Size of Environment Sector */
 332 #define CONFIG_ENV_SECT_SIZE    0x10000 /* see README - env sect real size */
 333 #define CONFIG_ENV_ADDR         (0xfff80000 - CONFIG_ENV_SECT_SIZE)
 334
 335 /*-----------------------------------------------------------------------
 336  * Cache Configuration
 337  */
 338 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For all MPC74xx CPUs          */
 339 #if defined(CONFIG_CMD_KGDB)
 340 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of the above value */
 341 #endif
 342
 343 /*-----------------------------------------------------------------------
 344  * L2CR setup -- make sure this is right for your board!
 345  * look in include/74xx_7xx.h for the defines used here
 346  */
 347
 348 #define CONFIG_SYS_L2
 349
 350 #ifdef CONFIG_750CX
 351 #define L2_INIT         0
 352 #else
 353 #define L2_INIT         (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 354                         L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 355 #endif
 356
 357 #define L2_ENABLE       (L2_INIT | L2CR_L2E)
 358
 359 /*------------------------------------------------------------------------
 360  * Real time clock
 361  */
 362 #define CONFIG_RTC_DS1302
 363
 364
 365 /*------------------------------------------------------------------------
 366  * Galileo I2C driver
 367  */
 368 #define CONFIG_GT_I2C
 369
 370 #endif  /* __CONFIG_H */