include/configs/acadia.h

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /************************************************************************
   9  * acadia.h - configuration for AMCC Acadia (405EZ)
  10  ***********************************************************************/
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*-----------------------------------------------------------------------
  16  * High Level Configuration Options
  17  *----------------------------------------------------------------------*/
  18 #define CONFIG_ACADIA           1               /* Board is Acadia      */
  19 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  20 #define CONFIG_405EZ            1               /* Specifc 405EZ support*/
  21
  22 #ifndef CONFIG_SYS_TEXT_BASE
  23 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  24 #endif
  25
  26 /*
  27  * Include common defines/options for all AMCC eval boards
  28  */
  29 #define CONFIG_HOSTNAME         acadia
  30 #include "amcc-common.h"
  31
  32 /* Detect Acadia PLL input clock automatically via CPLD bit             */
  33 #define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_CPLD_BASE + 0) == 0x0c) ? \
  34                                 66666666 : 33333000)
  35
  36 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  37 #define CONFIG_MISC_INIT_F      1               /* Call misc_init_f     */
  38
  39 #define CONFIG_NO_SERIAL_EEPROM
  40 /*#undef CONFIG_NO_SERIAL_EEPROM*/
  41
  42 #ifdef CONFIG_NO_SERIAL_EEPROM
  43 /*----------------------------------------------------------------------------
  44  * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
  45  * assuming a 66MHz input clock to the 405EZ.
  46  *---------------------------------------------------------------------------*/
  47 /* #define PLLMR0_100_100_12 */
  48 #define PLLMR0_200_133_66
  49 /* #define PLLMR0_266_160_80 */
  50 /* #define PLLMR0_333_166_83 */
  51 #endif
  52
  53 /*-----------------------------------------------------------------------
  54  * Base addresses -- Note these are effective addresses where the
  55  * actual resources get mapped (not physical addresses)
  56  *----------------------------------------------------------------------*/
  57 #define CONFIG_SYS_FLASH_BASE           0xfe000000
  58 #define CONFIG_SYS_CPLD_BASE            0x80000000
  59 #define CONFIG_SYS_NAND_ADDR            0xd0000000
  60 #define CONFIG_SYS_USB_HOST             0xef603000      /* USB OHCI 1.1 controller      */
  61
  62 /*-----------------------------------------------------------------------
  63  * Initial RAM & stack pointer
  64  *----------------------------------------------------------------------*/
  65 #define CONFIG_SYS_TEMP_STACK_OCM       1               /* OCM as init ram      */
  66
  67 /* On Chip Memory location */
  68 #define CONFIG_SYS_OCM_DATA_ADDR        0xf8000000
  69 #define CONFIG_SYS_OCM_DATA_SIZE        0x4000                  /* 16K of onchip SRAM           */
  70 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR        /* inside of SRAM               */
  71 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE        /* Size of used area in RAM     */
  72
  73 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  74 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  75
  76 /*-----------------------------------------------------------------------
  77  * Serial Port
  78  *----------------------------------------------------------------------*/
  79 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  80 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK                     /* external serial clock */
  81 #define CONFIG_SYS_BASE_BAUD            691200
  82
  83 /*-----------------------------------------------------------------------
  84  * Environment
  85  *----------------------------------------------------------------------*/
  86 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  87 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
  88 #else
  89 #define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars        */
  90 #define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
  91 #endif
  92
  93 /*-----------------------------------------------------------------------
  94  * FLASH related
  95  *----------------------------------------------------------------------*/
  96 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  97 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
  98 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
  99
 100 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 101 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 102 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 103
 104 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 105 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 106
 107 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 108 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 109
 110 #else
 111 /*
 112  * No NOR-flash on Acadia when NAND-booting. We need to undef the
 113  * NOR device-tree fixup code as well, since flash_info is not defined
 114  * in this case.
 115  */
 116 #define CONFIG_SYS_NO_FLASH             1
 117 #undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 118 #endif
 119
 120 #ifdef CONFIG_ENV_IS_IN_FLASH
 121 #define CONFIG_ENV_SECT_SIZE    0x40000 /* size of one complete sector  */
 122 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 123 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 124
 125 /* Address and size of Redundant Environment Sector     */
 126 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 127 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 128 #endif
 129
 130 /*
 131  * IPL (Initial Program Loader, integrated inside CPU)
 132  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 133  *
 134  * SPL (Secondary Program Loader)
 135  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 136  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 137  * controller and the NAND controller so that the special U-Boot image can be
 138  * loaded from NAND to SDRAM.
 139  *
 140  * NUB (NAND U-Boot)
 141  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 142  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 143  *
 144  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 145  * set up. While still running from cache, I experienced problems accessing
 146  * the NAND controller. sr - 2006-08-25
 147  */
 148 #define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location                 */
 149 #define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                     */
 150 #define CONFIG_SYS_NAND_BOOT_SPL_DST    (CONFIG_SYS_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
 151 #define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr        */
 152 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr  */
 153 #define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 154
 155 /*
 156  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 157  */
 158 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (16 << 10)      /* Offset to RAM U-Boot image   */
 159 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (384 << 10)     /* Size of RAM U-Boot image     */
 160
 161 /*
 162  * Now the NAND chip has to be defined (no autodetection used!)
 163  */
 164 #define CONFIG_SYS_NAND_PAGE_SIZE       512             /* NAND chip page size          */
 165 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)      /* NAND chip block size         */
 166 #define CONFIG_SYS_NAND_PAGE_COUNT      32              /* NAND chip page count         */
 167 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   5               /* Location of bad block marker */
 168 #undef CONFIG_SYS_NAND_4_ADDR_CYCLE                     /* No fourth addr used (<=32MB) */
 169
 170 #define CONFIG_SYS_NAND_ECCSIZE 256
 171 #define CONFIG_SYS_NAND_ECCBYTES        3
 172 #define CONFIG_SYS_NAND_OOBSIZE 16
 173 #define CONFIG_SYS_NAND_ECCPOS          {0, 1, 2, 3, 6, 7}
 174
 175 #ifdef CONFIG_ENV_IS_IN_NAND
 176 /*
 177  * For NAND booting the environment is embedded in the U-Boot image. Please take
 178  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 179  */
 180 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 181 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 182 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 183 #endif
 184
 185 /*-----------------------------------------------------------------------
 186  * RAM (CRAM)
 187  *----------------------------------------------------------------------*/
 188 #define CONFIG_SYS_MBYTES_RAM           64              /* 64MB                 */
 189
 190 /*-----------------------------------------------------------------------
 191  * I2C
 192  *----------------------------------------------------------------------*/
 193 #define CONFIG_SYS_I2C_SPEED            400000          /* I2C speed and slave address  */
 194
 195 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 196 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa8>>1)
 197 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 198 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 199 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 200
 201 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 202 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 203 #define CONFIG_DTT_AD7414       1               /* use AD7414           */
 204 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 205 #define CONFIG_SYS_DTT_MAX_TEMP 70
 206 #define CONFIG_SYS_DTT_LOW_TEMP -30
 207 #define CONFIG_SYS_DTT_HYSTERESIS       3
 208
 209 /*-----------------------------------------------------------------------
 210  * Ethernet
 211  *----------------------------------------------------------------------*/
 212 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
 213 #define CONFIG_HAS_ETH0         1
 214
 215 /*
 216  * Default environment variables
 217  */
 218 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 219         CONFIG_AMCC_DEF_ENV                                             \
 220         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 221         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 222         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 223         CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
 224         "kernel_addr=fff10000\0"                                        \
 225         "ramdisk_addr=fff20000\0"                                       \
 226         "kozio=bootm ffc60000\0"                                        \
 227         ""
 228
 229 #define CONFIG_USB_OHCI
 230 #define CONFIG_USB_STORAGE
 231
 232 /* Partitions */
 233 #define CONFIG_MAC_PARTITION
 234 #define CONFIG_DOS_PARTITION
 235 #define CONFIG_ISO_PARTITION
 236
 237 #define CONFIG_SUPPORT_VFAT
 238
 239 /*
 240  * Commands additional to the ones defined in amcc-common.h
 241  */
 242 #define CONFIG_CMD_DTT
 243 #define CONFIG_CMD_NAND
 244 #define CONFIG_CMD_USB
 245
 246 /*
 247  * No NOR on Acadia when NAND-booting
 248  */
 249 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 250 #undef CONFIG_CMD_FLASH
 251 #undef CONFIG_CMD_IMLS
 252 #endif
 253
 254 /*-----------------------------------------------------------------------
 255  * NAND FLASH
 256  *----------------------------------------------------------------------*/
 257 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 258 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 259 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
 260
 261 /*-----------------------------------------------------------------------
 262  * External Bus Controller (EBC) Setup
 263  *----------------------------------------------------------------------*/
 264 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 265 #define CONFIG_SYS_NAND_CS              3
 266 /* Memory Bank 0 (Flash) initialization                                         */
 267 #define CONFIG_SYS_EBC_PB0AP            0x03337200
 268 #define CONFIG_SYS_EBC_PB0CR            0xfe0bc000
 269
 270 /* Memory Bank 3 (NAND-FLASH) initialization                                    */
 271 #define CONFIG_SYS_EBC_PB3AP            0x018003c0
 272 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 273
 274 /* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
 275 /* Memory Bank 1 (CRAM) initialization                                          */
 276 #define CONFIG_SYS_EBC_PB1AP            0x030400c0
 277 #define CONFIG_SYS_EBC_PB1CR            0x000bc000
 278
 279 /* Memory Bank 2 (CRAM) initialization                                          */
 280 #define CONFIG_SYS_EBC_PB2AP            0x030400c0
 281 #define CONFIG_SYS_EBC_PB2CR            0x020bc000
 282 #else
 283 #define CONFIG_SYS_NAND_CS              0               /* NAND chip connected to CSx   */
 284 /* Memory Bank 0 (NAND-FLASH) initialization                                    */
 285 #define CONFIG_SYS_EBC_PB0AP            0x018003c0
 286 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 287
 288 /*
 289  * When NAND-booting the CRAM EBC setup must be done in sync mode, since the
 290  * NAND-SPL already initialized the CRAM and EBC to sync mode.
 291  */
 292 /* Memory Bank 1 (CRAM) initialization                                          */
 293 #define CONFIG_SYS_EBC_PB1AP            0x9C0201C0
 294 #define CONFIG_SYS_EBC_PB1CR            0x000bc000
 295
 296 /* Memory Bank 2 (CRAM) initialization                                          */
 297 #define CONFIG_SYS_EBC_PB2AP            0x9C0201C0
 298 #define CONFIG_SYS_EBC_PB2CR            0x020bc000
 299 #endif
 300
 301 /* Memory Bank 4 (CPLD) initialization                                          */
 302 #define CONFIG_SYS_EBC_PB4AP            0x04006000
 303 #define CONFIG_SYS_EBC_PB4CR            (CONFIG_SYS_CPLD_BASE | 0x18000)
 304
 305 #define CONFIG_SYS_EBC_CFG              0xf8400000
 306
 307 /*-----------------------------------------------------------------------
 308  * GPIO Setup
 309  *----------------------------------------------------------------------*/
 310 #define CONFIG_SYS_GPIO_CRAM_CLK        8
 311 #define CONFIG_SYS_GPIO_CRAM_WAIT       9               /* GPIO-In              */
 312 #define CONFIG_SYS_GPIO_CRAM_ADV        10
 313 #define CONFIG_SYS_GPIO_CRAM_CRE        (32 + 21)       /* GPIO-Out             */
 314
 315 /*-----------------------------------------------------------------------
 316  * Definitions for GPIO_0 setup (PPC405EZ specific)
 317  *
 318  * GPIO0[0-2]   - External Bus Controller CS_4 - CS_6 Outputs
 319  * GPIO0[3]     - NAND FLASH Controller CE3 (NFCE3) Output
 320  * GPIO0[4]     - External Bus Controller Hold Input
 321  * GPIO0[5]     - External Bus Controller Priority Input
 322  * GPIO0[6]     - External Bus Controller HLDA Output
 323  * GPIO0[7]     - External Bus Controller Bus Request Output
 324  * GPIO0[8]     - CRAM Clk Output
 325  * GPIO0[9]     - External Bus Controller Ready Input
 326  * GPIO0[10]    - CRAM Adv Output
 327  * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
 328  * GPIO0[25]    - External DMA Request Input
 329  * GPIO0[26]    - External DMA EOT I/O
 330  * GPIO0[25]    - External DMA Ack_n Output
 331  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 332  * GPIO0[28-30] - Trace Outputs / PWM Inputs
 333  * GPIO0[31]    - PWM_8 I/O
 334  */
 335 #define CONFIG_SYS_GPIO0_TCR            0xC0A00000
 336 #define CONFIG_SYS_GPIO0_OSRL           0x50004400
 337 #define CONFIG_SYS_GPIO0_OSRH           0x02000055
 338 #define CONFIG_SYS_GPIO0_ISR1L          0x00001000
 339 #define CONFIG_SYS_GPIO0_ISR1H          0x00000055
 340 #define CONFIG_SYS_GPIO0_TSRL           0x02000000
 341 #define CONFIG_SYS_GPIO0_TSRH           0x00000055
 342
 343 /*-----------------------------------------------------------------------
 344  * Definitions for GPIO_1 setup (PPC405EZ specific)
 345  *
 346  * GPIO1[0-6]   - PWM_9 to PWM_15 I/O
 347  * GPIO1[7]     - PWM_DIV_CLK (Out) / IRQ4 Input
 348  * GPIO1[8]     - TS5 Output / DAC_IP_TRIG Input
 349  * GPIO1[9]     - TS6 Output / ADC_IP_TRIG Input
 350  * GPIO1[10-12] - UART0 Control Inputs
 351  * GPIO1[13]    - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
 352  * GPIO1[14]    - UART0_RTS_N Output/SPI_SS_2_N Output
 353  * GPIO1[15]    - SPI_SS_3_N Output/UART0_RI_N Input
 354  * GPIO1[16]    - SPI_SS_1_N Output
 355  * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
 356  */
 357 #define CONFIG_SYS_GPIO1_TCR            0xFFFF8414
 358 #define CONFIG_SYS_GPIO1_OSRL           0x40000110
 359 #define CONFIG_SYS_GPIO1_OSRH           0x55455555
 360 #define CONFIG_SYS_GPIO1_ISR1L          0x15555445
 361 #define CONFIG_SYS_GPIO1_ISR1H          0x00000000
 362 #define CONFIG_SYS_GPIO1_TSRL           0x00000000
 363 #define CONFIG_SYS_GPIO1_TSRH           0x00000000
 364
 365 #endif  /* __CONFIG_H */