include/configs/acadia.h

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************************************
  25  * acadia.h - configuration for AMCC Acadia (405EZ)
  26  ***********************************************************************/
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*-----------------------------------------------------------------------
  32  * High Level Configuration Options
  33  *----------------------------------------------------------------------*/
  34 #define CONFIG_ACADIA           1               /* Board is Acadia      */
  35 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  36 #define CONFIG_405EZ            1               /* Specifc 405EZ support*/
  37 /* Detect Acadia PLL input clock automatically via CPLD bit             */
  38 #define CONFIG_SYS_CLK_FREQ    ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \
  39                                 66666666 : 33333000)
  40
  41 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  42 #define CONFIG_MISC_INIT_F      1               /* Call misc_init_f     */
  43
  44 #define CONFIG_NO_SERIAL_EEPROM
  45 /*#undef CONFIG_NO_SERIAL_EEPROM*/
  46
  47 #ifdef CONFIG_NO_SERIAL_EEPROM
  48 /*----------------------------------------------------------------------------
  49  * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
  50  * assuming a 66MHz input clock to the 405EZ.
  51  *---------------------------------------------------------------------------*/
  52 /* #define PLLMR0_100_100_12 */
  53 #define PLLMR0_200_133_66
  54 /* #define PLLMR0_266_160_80 */
  55 /* #define PLLMR0_333_166_83 */
  56 #endif
  57
  58 /*-----------------------------------------------------------------------
  59  * Base addresses -- Note these are effective addresses where the
  60  * actual resources get mapped (not physical addresses)
  61  *----------------------------------------------------------------------*/
  62 #define CFG_MONITOR_LEN         (256 * 1024)/* Reserve 256 kB for Monitor       */
  63 #define CFG_MALLOC_LEN          (512 * 1024)/* Reserve 512 kB for malloc()      */
  64
  65 #define CFG_SDRAM_BASE          0x00000000
  66 #define CFG_FLASH_BASE          0xfe000000
  67 #define CFG_MONITOR_BASE        TEXT_BASE
  68 #define CFG_CPLD_BASE           0x80000000
  69 #define CFG_NAND_ADDR           0xd0000000
  70 #define CFG_USB_HOST            0xef603000      /* USB OHCI 1.1 controller      */
  71
  72 /*-----------------------------------------------------------------------
  73  * Initial RAM & stack pointer
  74  *----------------------------------------------------------------------*/
  75 #define CFG_TEMP_STACK_OCM      1               /* OCM as init ram      */
  76
  77 /* On Chip Memory location */
  78 #define CFG_OCM_DATA_ADDR       0xF8000000
  79 #define CFG_OCM_DATA_SIZE       0x4000                  /* 16K of onchip SRAM           */
  80 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR       /* inside of SRAM               */
  81 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE       /* End of used area in RAM      */
  82
  83 #define CFG_GBL_DATA_SIZE       128                     /* size for initial data        */
  84 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  85 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
  86
  87 /*-----------------------------------------------------------------------
  88  * Serial Port
  89  *----------------------------------------------------------------------*/
  90 #undef  CFG_EXT_SERIAL_CLOCK                    /* external serial clock */
  91 #define CFG_BASE_BAUD           691200
  92 #define CONFIG_BAUDRATE         115200
  93 #define CONFIG_SERIAL_MULTI     1
  94
  95 /* The following table includes the supported baudrates */
  96 #define CFG_BAUDRATE_TABLE      \
  97         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
  98
  99 /*-----------------------------------------------------------------------
 100  * Environment
 101  *----------------------------------------------------------------------*/
 102 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 103 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
 104 #else
 105 #define CFG_ENV_IS_IN_NAND      1       /* use NAND for environment vars        */
 106 #define CFG_ENV_IS_EMBEDDED     1       /* use embedded environment */
 107 #endif
 108
 109 /*-----------------------------------------------------------------------
 110  * FLASH related
 111  *----------------------------------------------------------------------*/
 112 #define CFG_FLASH_CFI                   /* The flash is CFI compatible  */
 113 #define CFG_FLASH_CFI_DRIVER            /* Use common CFI driver        */
 114
 115 #define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
 116 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 117 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
 118
 119 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 120 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 121
 122 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 123 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 124
 125 #ifdef CFG_ENV_IS_IN_FLASH
 126 #define CFG_ENV_SECT_SIZE       0x40000 /* size of one complete sector  */
 127 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 128 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 129
 130 /* Address and size of Redundant Environment Sector     */
 131 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 132 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 133 #endif
 134
 135 /*-----------------------------------------------------------------------
 136  * RAM (CRAM)
 137  *----------------------------------------------------------------------*/
 138 #define CFG_MBYTES_RAM          64              /* 64MB                 */
 139
 140 /*-----------------------------------------------------------------------
 141  * I2C
 142  *----------------------------------------------------------------------*/
 143 #define CONFIG_HARD_I2C         1               /* I2C with hardware support    */
 144 #undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 145 #define CFG_I2C_SPEED           400000          /* I2C speed and slave address  */
 146 #define CFG_I2C_SLAVE           0x7F
 147
 148 #define CFG_I2C_MULTI_EEPROMS
 149 #define CFG_I2C_EEPROM_ADDR     (0xa8>>1)
 150 #define CFG_I2C_EEPROM_ADDR_LEN 1
 151 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 152 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 153 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 154
 155 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 156 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 157 #define CONFIG_DTT_AD7414       1               /* use AD7414           */
 158 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 159 #define CFG_DTT_MAX_TEMP        70
 160 #define CFG_DTT_LOW_TEMP        -30
 161 #define CFG_DTT_HYSTERESIS      3
 162
 163 #if 0 /* test-only... */
 164 /*-----------------------------------------------------------------------
 165  * SPI stuff - Define to include SPI control
 166  *-----------------------------------------------------------------------
 167  */
 168 #define CONFIG_SPI
 169 #endif
 170
 171 /*-----------------------------------------------------------------------
 172  * Ethernet
 173  *----------------------------------------------------------------------*/
 174 #define CONFIG_MII              1       /* MII PHY management           */
 175 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
 176 #define CONFIG_NET_MULTI        1
 177 #define CFG_RX_ETH_BUFFER       16      /* # of rx buffers & descriptors*/
 178
 179 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
 180
 181 #define CONFIG_PREBOOT  "echo;" \
 182         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 183         "echo"
 184
 185 #undef  CONFIG_BOOTARGS
 186
 187 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 188         "netdev=eth0\0"                                                 \
 189         "hostname=acadia\0"                                             \
 190         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 191                 "nfsroot=${serverip}:${rootpath}\0"                     \
 192         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 193         "addip=setenv bootargs ${bootargs} "                            \
 194                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 195                 ":${hostname}:${netdev}:off panic=1\0"                  \
 196         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 197         "flash_nfs=run nfsargs addip addtty;"                           \
 198                 "bootm ${kernel_addr}\0"                                \
 199         "flash_self=run ramargs addip addtty;"                          \
 200                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 201         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 202                 "bootm\0"                                               \
 203         "rootpath=/opt/eldk/ppc_4xx\0"                          \
 204         "bootfile=acadia/uImage\0"                                      \
 205         "kernel_addr=fff10000\0"                                        \
 206         "ramdisk_addr=fff20000\0"                                       \
 207         "initrd_high=30000000\0"                                        \
 208         "load=tftp 200000 acadia/u-boot.bin\0"                          \
 209         "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"   \
 210                 "cp.b ${fileaddr} fffc0000 ${filesize};"                \
 211                 "setenv filesize;saveenv\0"                             \
 212         "upd=run load;run update\0"                                     \
 213         "kozio=bootm ffc60000\0"                                        \
 214         ""
 215 #define CONFIG_BOOTCOMMAND      "run flash_self"
 216
 217 #if 0
 218 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 219 #else
 220 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 221 #endif
 222
 223 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 224 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 225
 226 #define CONFIG_USB_OHCI
 227 #define CONFIG_USB_STORAGE
 228
 229 /* Partitions */
 230 #define CONFIG_MAC_PARTITION
 231 #define CONFIG_DOS_PARTITION
 232 #define CONFIG_ISO_PARTITION
 233
 234 #define CONFIG_SUPPORT_VFAT
 235
 236 #define CONFIG_COMMANDS       (CONFIG_CMD_DFL   |       \
 237                                CFG_CMD_ASKENV   |       \
 238                                CFG_CMD_DHCP     |       \
 239                                CFG_CMD_DTT      |       \
 240                                CFG_CMD_DIAG     |       \
 241                                CFG_CMD_EEPROM   |       \
 242                                CFG_CMD_ELF      |       \
 243                                CFG_CMD_FAT      |       \
 244                                CFG_CMD_I2C      |       \
 245                                CFG_CMD_IRQ      |       \
 246                                CFG_CMD_MII      |       \
 247                                CFG_CMD_NAND     |       \
 248                                CFG_CMD_NET      |       \
 249                                CFG_CMD_NFS      |       \
 250                                CFG_CMD_PCI      |       \
 251                                CFG_CMD_PING     |       \
 252                                CFG_CMD_REGINFO  |       \
 253                                CFG_CMD_USB)
 254
 255 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 256 #include <cmd_confdefs.h>
 257
 258 #undef CONFIG_WATCHDOG                                  /* watchdog disabled            */
 259
 260 /*-----------------------------------------------------------------------
 261  * Miscellaneous configurable options
 262  *----------------------------------------------------------------------*/
 263 #define CFG_LONGHELP                    /* undef to save memory         */
 264 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 265 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 266 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 267 #else
 268 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 269 #endif
 270 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 271 #define CFG_MAXARGS             16      /* max number of command args   */
 272 #define CFG_BARGSIZE            CFG_CBSIZE /* Boot Argument Buffer Size */
 273
 274 #define CFG_MEMTEST_START       0x0400000 /* memtest works on           */
 275 #define CFG_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM        */
 276
 277 #define CFG_LOAD_ADDR           0x100000  /* default load address       */
 278 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 279
 280 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 281
 282 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 283 #define CONFIG_LOOPW            1       /* enable loopw command         */
 284 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 285 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 286 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 287
 288 /*
 289  * For booting Linux, the board info and command line data
 290  * have to be in the first 8 MB of memory, since this is
 291  * the maximum mapped by the Linux kernel during initialization.
 292  */
 293 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 294
 295 /*-----------------------------------------------------------------------
 296  * NAND FLASH
 297  *----------------------------------------------------------------------*/
 298 #define CFG_MAX_NAND_DEVICE     1
 299 #define NAND_MAX_CHIPS          1
 300 #define CFG_NAND_BASE           (CFG_NAND_ADDR + CFG_NAND_CS)
 301 #define CFG_NAND_SELECT_DEVICE  1       /* nand driver supports mutipl. chips   */
 302
 303 /*-----------------------------------------------------------------------
 304  * Cache Configuration
 305  */
 306 #define CFG_DCACHE_SIZE         16384           /* For AMCC 405EZ CPU           */
 307 #define CFG_CACHELINE_SIZE      32              /* ...                          */
 308 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 309 #define CFG_CACHELINE_SHIFT     5               /* log base 2 of the above value*/
 310 #endif
 311
 312 /*-----------------------------------------------------------------------
 313  * External Bus Controller (EBC) Setup
 314  *----------------------------------------------------------------------*/
 315 #define CFG_NAND_CS             3               /* NAND chip connected to CSx   */
 316
 317 /* Memory Bank 0 (Flash) initialization                                         */
 318 #define CFG_EBC_PB0AP           0x03337200
 319 #define CFG_EBC_PB0CR           0xfe0bc000
 320
 321 /* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
 322 /* Memory Bank 1 (CRAM) initialization                                          */
 323 #define CFG_EBC_PB1AP           0x030400c0
 324 #define CFG_EBC_PB1CR           0x000bc000
 325
 326 /* Memory Bank 2 (CRAM) initialization                                          */
 327 #define CFG_EBC_PB2AP           0x030400c0
 328 #define CFG_EBC_PB2CR           0x020bc000
 329
 330 /* Memory Bank 3 (NAND-FLASH) initialization                                    */
 331 #define CFG_EBC_PB3AP           0x018003c0
 332 #define CFG_EBC_PB3CR           (CFG_NAND_ADDR | 0x1c000)
 333
 334 /* Memory Bank 4 (CPLD) initialization                                          */
 335 #define CFG_EBC_PB4AP           0x04006000
 336 #define CFG_EBC_PB4CR           (CFG_CPLD_BASE | 0x18000)
 337
 338 #define CFG_EBC_CFG             0xf8400000
 339
 340 /*-----------------------------------------------------------------------
 341  * GPIO Setup
 342  *----------------------------------------------------------------------*/
 343 #define CFG_GPIO_CRAM_CLK       8
 344 #define CFG_GPIO_CRAM_WAIT      9
 345 #define CFG_GPIO_CRAM_ADV       10
 346 #define CFG_GPIO_CRAM_CRE       (32 + 21)
 347
 348 /*-----------------------------------------------------------------------
 349  * Definitions for GPIO_0 setup (PPC405EZ specific)
 350  *
 351  * GPIO0[0-2]   - External Bus Controller CS_4 - CS_6 Outputs
 352  * GPIO0[3]     - NAND FLASH Controller CE3 (NFCE3) Output
 353  * GPIO0[4]     - External Bus Controller Hold Input
 354  * GPIO0[5]     - External Bus Controller Priority Input
 355  * GPIO0[6]     - External Bus Controller HLDA Output
 356  * GPIO0[7]     - External Bus Controller Bus Request Output
 357  * GPIO0[8]     - CRAM Clk Output
 358  * GPIO0[9]     - External Bus Controller Ready Input
 359  * GPIO0[10]    - CRAM Adv Output
 360  * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
 361  * GPIO0[25]    - External DMA Request Input
 362  * GPIO0[26]    - External DMA EOT I/O
 363  * GPIO0[25]    - External DMA Ack_n Output
 364  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 365  * GPIO0[28-30] - Trace Outputs / PWM Inputs
 366  * GPIO0[31]    - PWM_8 I/O
 367  */
 368 #define CFG_GPIO0_TCR           0xC0000000
 369 #define CFG_GPIO0_OSRL          0x50000000
 370 #define CFG_GPIO0_OSRH          0x02000055
 371 #define CFG_GPIO0_ISR1L         0x00000000
 372 #define CFG_GPIO0_ISR1H         0x00000055
 373 #define CFG_GPIO0_TSRL          0x02000000
 374 #define CFG_GPIO0_TSRH          0x00000055
 375
 376 /*-----------------------------------------------------------------------
 377  * Definitions for GPIO_1 setup (PPC405EZ specific)
 378  *
 379  * GPIO1[0-6]   - PWM_9 to PWM_15 I/O
 380  * GPIO1[7]     - PWM_DIV_CLK (Out) / IRQ4 Input
 381  * GPIO1[8]     - TS5 Output / DAC_IP_TRIG Input
 382  * GPIO1[9]     - TS6 Output / ADC_IP_TRIG Input
 383  * GPIO1[10-12] - UART0 Control Inputs
 384  * GPIO1[13]    - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
 385  * GPIO1[14]    - UART0_RTS_N Output/SPI_SS_2_N Output
 386  * GPIO1[15]    - SPI_SS_3_N Output/UART0_RI_N Input
 387  * GPIO1[16]    - SPI_SS_1_N Output
 388  * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
 389  */
 390 #define CFG_GPIO1_OSRH          0x55455555
 391 #define CFG_GPIO1_OSRL          0x40000110
 392 #define CFG_GPIO1_ISR1H         0x00000000
 393 #define CFG_GPIO1_ISR1L         0x15555445
 394 #define CFG_GPIO1_TSRH          0x00000000
 395 #define CFG_GPIO1_TSRL          0x00000000
 396 #define CFG_GPIO1_TCR           0xFFFF8014
 397
 398 /*
 399  * Internal Definitions
 400  *
 401  * Boot Flags
 402  */
 403 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 404 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 405
 406 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 407   #define CONFIG_KGDB_BAUDRATE  230400  /* speed to run kgdb serial port */
 408   #define CONFIG_KGDB_SER_INDEX 2       /* which serial port to use */
 409 #endif
 410
 411 #endif  /* __CONFIG_H */