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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/acadia.h
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /************************************************************************
25 * acadia.h - configuration for AMCC Acadia (405EZ)
26 ***********************************************************************/
31 /*-----------------------------------------------------------------------
32 * High Level Configuration Options
33 *----------------------------------------------------------------------*/
34 #define CONFIG_ACADIA 1 /* Board is Acadia */
35 #define CONFIG_4xx 1 /* ... PPC4xx family */
36 #define CONFIG_405EZ 1 /* Specifc 405EZ support*/
37 #undef CFG_DRAM_TEST /* Disable-takes long time */
38 #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
40 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
41 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
43 #define CONFIG_NO_SERIAL_EEPROM
44 /*#undef CONFIG_NO_SERIAL_EEPROM*/
46 #ifdef CONFIG_NO_SERIAL_EEPROM
48 /*----------------------------------------------------------------------------
49 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
50 * assuming a 66MHz input clock to the 405EZ.
51 *---------------------------------------------------------------------------*/
52 /* #define PLLMR0_100_100_12 */
53 #define PLLMR0_200_133_66
54 /* #define PLLMR0_266_160_80 */
55 /* #define PLLMR0_333_166_83 */
58 /*-----------------------------------------------------------------------
59 * Base addresses -- Note these are effective addresses where the
60 * actual resources get mapped (not physical addresses)
61 *----------------------------------------------------------------------*/
62 #define CFG_SDRAM_BASE 0x00000000
63 #define CFG_FLASH_BASE 0xFE000000
64 #define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */
65 #define CFG_MALLOC_LEN (384 * 1024)/* Reserve 128 kB for malloc() */
66 #define CFG_MONITOR_BASE TEXT_BASE
67 #define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
70 * Define here the location of the environment variables (FLASH).
71 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
72 * supported for backward compatibility.
74 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
75 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
77 #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
80 #define CONFIG_PREBOOT "echo;" \
81 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
84 #undef CONFIG_BOOTARGS
86 #define CONFIG_EXTRA_ENV_SETTINGS \
89 "nfsargs=setenv bootargs root=/dev/nfs rw " \
90 "nfsroot=${serverip}:${rootpath}\0" \
91 "ramargs=setenv bootargs root=/dev/ram rw\0" \
92 "addip=setenv bootargs ${bootargs} " \
93 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
94 ":${hostname}:${netdev}:off panic=1\0" \
95 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
96 "flash_nfs=run nfsargs addip addtty;" \
97 "bootm ${kernel_addr}\0" \
98 "flash_self=run ramargs addip addtty;" \
99 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
100 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
102 "rootpath=/opt/eldk/ppc_4xx\0" \
103 "bootfile=acadia/uImage\0" \
104 "kernel_addr=fff10000\0" \
105 "ramdisk_addr=fff20000\0" \
106 "initrd_high=30000000\0" \
107 "load=tftp 200000 acadia/u-boot.bin\0" \
108 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
109 "cp.b ${fileaddr} fffc0000 ${filesize};" \
110 "setenv filesize;saveenv\0" \
111 "upd=run load;run update\0" \
112 "kozio=bootm ffc60000\0" \
114 #define CONFIG_BOOTCOMMAND "run flash_self"
117 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
119 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
122 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
123 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
125 #define CONFIG_MII 1 /* MII PHY management */
126 #define CONFIG_PHY_ADDR 0 /* PHY address */
127 #define CONFIG_NET_MULTI 1
128 #define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
130 #define CONFIG_NETCONSOLE /* include NetConsole support */
132 #define CONFIG_USB_OHCI
133 #define CONFIG_USB_STORAGE
135 #if 0 /* test-only */
136 #define TEST_ONLY_NAND
139 #ifdef TEST_ONLY_NAND
140 #define CMD_NAND CFG_CMD_NAND
146 #define CONFIG_MAC_PARTITION
147 #define CONFIG_DOS_PARTITION
148 #define CONFIG_ISO_PARTITION
150 #define CONFIG_SUPPORT_VFAT
152 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
172 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
173 #include <cmd_confdefs.h>
175 #undef CONFIG_WATCHDOG /* watchdog disabled */
178 * Miscellaneous configurable options
180 #define CFG_LONGHELP /* undef to save memory */
181 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
182 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
183 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
185 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
187 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
188 #define CFG_MAXARGS 16 /* max number of command args */
189 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
191 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
192 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
194 #define CFG_LOAD_ADDR 0x100000 /* default load address */
195 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
197 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
199 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
200 #define CONFIG_LOOPW 1 /* enable loopw command */
201 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
202 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
203 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
205 /*-----------------------------------------------------------------------
207 *----------------------------------------------------------------------*/
208 #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
209 #define CFG_BASE_BAUD 691200
210 #define CONFIG_BAUDRATE 115200
212 /* The following table includes the supported baudrates */
213 #define CFG_BAUDRATE_TABLE \
214 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
216 /*-----------------------------------------------------------------------
218 *----------------------------------------------------------------------*/
219 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
220 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
221 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
222 #define CFG_I2C_SLAVE 0x7F
224 #define CFG_I2C_MULTI_EEPROMS
225 #define CFG_I2C_EEPROM_ADDR (0xa8>>1)
226 #define CFG_I2C_EEPROM_ADDR_LEN 1
227 #define CFG_EEPROM_PAGE_WRITE_ENABLE
228 #define CFG_EEPROM_PAGE_WRITE_BITS 3
229 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
231 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
232 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
233 #define CONFIG_DTT_AD7414 1 /* use AD7414 */
234 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
235 #define CFG_DTT_MAX_TEMP 70
236 #define CFG_DTT_LOW_TEMP -30
237 #define CFG_DTT_HYSTERESIS 3
239 #if 0 /* test-only... */
240 /*-----------------------------------------------------------------------
241 * SPI stuff - Define to include SPI control
242 *-----------------------------------------------------------------------
248 * For booting Linux, the board info and command line data
249 * have to be in the first 8 MB of memory, since this is
250 * the maximum mapped by the Linux kernel during initialization.
252 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
254 /*-----------------------------------------------------------------------
256 *----------------------------------------------------------------------*/
257 #define CFG_FLASH_CFI
258 #define CFG_FLASH_CFI_DRIVER
259 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
260 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
262 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
263 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
264 #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
266 #undef CFG_FLASH_CHECKSUM
267 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
268 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
270 #ifdef CFG_ENV_IS_IN_FLASH
271 #define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
272 #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
273 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
275 /* Address and size of Redundant Environment Sector */
276 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
277 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
280 #ifdef TEST_ONLY_NAND
281 /*-----------------------------------------------------------------------
283 *----------------------------------------------------------------------*/
284 #define CFG_MAX_NAND_DEVICE 1
285 #define NAND_MAX_CHIPS 1
286 #define CFG_NAND_BASE (CFG_NAND + CFG_NAND_CS)
287 #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
290 /*-----------------------------------------------------------------------
291 * Cache Configuration
293 #define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */
294 #define CFG_CACHELINE_SIZE 32 /* ... */
295 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
296 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
299 /*-----------------------------------------------------------------------
300 * Definitions for initial stack pointer and data area (in data cache)
302 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
303 #define CFG_TEMP_STACK_OCM 1
305 /* On Chip Memory location */
306 #define CFG_OCM_DATA_ADDR 0xF8000000
307 #define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
308 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */
309 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
311 #define CFG_GBL_DATA_SIZE 128 /* size for initial data */
312 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
313 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
315 /*-----------------------------------------------------------------------
316 * External Bus Controller (EBC) Setup
318 #define CFG_NAND 0xd0000000
319 #define CFG_NAND_CS 0 /* NAND chip connected to CSx */
321 /* Memory Bank 0 (Flash) initialization */
322 #define CFG_EBC_PB0AP 0x03337200
323 #define CFG_EBC_PB0CR 0xfe0bc000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=32bit */
325 /* Memory Bank 1 (CRAM) initialization */
326 #define CFG_EBC_PB1AP 0x030400c0
327 #define CFG_EBC_PB1CR 0x000bc000
329 /* Memory Bank 2 (CRAM) initialization */
330 #define CFG_EBC_PB2AP 0x030400c0
331 #define CFG_EBC_PB2CR 0x020bc000
333 /* Memory Bank 3 (NAND-FLASH) initialization */
334 #define CFG_EBC_PB3AP 0x018003c0
335 #define CFG_EBC_PB3CR (CFG_NAND | 0x1c000)
337 /* Memory Bank 4 (CPLD) initialization */
338 #define CFG_EBC_PB4AP 0x04006000
339 #define CFG_EBC_PB4CR 0x80018000 /* BAS=0x000,BS=16MB,BU=R/W,BW=32bit */
341 #define CFG_EBC_CFG 0xf8400000
343 /*-----------------------------------------------------------------------
344 * Definitions for GPIO_0 setup (PPC405EZ specific)
346 * GPIO0[0-3] - External Bus Controller CS_4 - CS_7 Outputs
347 * GPIO0[4] - External Bus Controller Hold Input
348 * GPIO0[5] - External Bus Controller Priority Input
349 * GPIO0[6] - External Bus Controller HLDA Output
350 * GPIO0[7] - External Bus Controller Bus Request Output
351 * GPIO0[8] - CRAM Clk Output
352 * GPIO0[9] - External Bus Controller Ready Input
353 * GPIO0[10] - CRAM Adv Output
354 * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
355 * GPIO0[25] - External DMA Request Input
356 * GPIO0[26] - External DMA EOT I/O
357 * GPIO0[25] - External DMA Ack_n Output
358 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
359 * GPIO0[28-30] - Trace Outputs / PWM Inputs
360 * GPIO0[31] - PWM_8 I/O
362 #define CFG_GPIO0_TCR 0xC0000000
363 #define CFG_GPIO0_OSRL 0x50000000
364 #define CFG_GPIO0_OSRH 0x00000055
365 #define CFG_GPIO0_ISR1L 0x00000000
366 #define CFG_GPIO0_ISR1H 0x00000055
367 #define CFG_GPIO0_TSRL 0x00000000
368 #define CFG_GPIO0_TSRH 0x00000055
370 /*-----------------------------------------------------------------------
371 * Definitions for GPIO_1 setup (PPC405EZ specific)
373 * GPIO1[0-6] - PWM_9 to PWM_15 I/O
374 * GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input
375 * GPIO1[8] - TS5 Output / DAC_IP_TRIG Input
376 * GPIO1[9] - TS6 Output / ADC_IP_TRIG Input
377 * GPIO1[10-12] - UART0 Control Inputs
378 * GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
379 * GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output
380 * GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input
381 * GPIO1[16] - SPI_SS_1_N Output
382 * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
384 #define CFG_GPIO1_OSRH 0x55455555
385 #define CFG_GPIO1_OSRL 0x40000110
386 #define CFG_GPIO1_ISR1H 0x00000000
387 #define CFG_GPIO1_ISR1L 0x15555445
388 #define CFG_GPIO1_TSRH 0x00000000
389 #define CFG_GPIO1_TSRL 0x00000000
390 #define CFG_GPIO1_TCR 0xFFFF8014
392 /*-----------------------------------------------------------------------
395 #define EPLD_BASE 0x80000000
396 #define EPLD_ETHRSTBOOT 0x10
397 #define EPLD_CTRL 0x14
398 #define EPLD_MUXOE 0x16
403 #define LOAK_INIT 0x494e4954 /* ASCII "INIT" */
404 #define LOAK_NONE 0x4e4f4e45 /* ASCII "NONE" */
405 #define LOAK_CRAM 0x4352414d /* ASCII "CRAM" */
406 #define LOAK_PSRAM 0x50535241 /* ASCII "PSRA" - PSRAM */
407 #define LOAK_OCM 0x4f434d20 /* ASCII "OCM " */
408 #define LOAK_ZERO 0x5a45524f /* ASCII "ZERO" */
409 #define LOAK_SPL 0x53504c20 /* ASCII "SPL" */
412 * Internal Definitions
416 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
417 #define BOOTFLAG_WARM 0x02 /* Software reboot */
419 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
420 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
421 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
424 #endif /* __CONFIG_H */