include/configs/ads5121.h

   1 /*
   2  * (C) Copyright 2007 DENX Software Engineering
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * ADS5121 board configuration file
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #define DEBUG
  31 #undef DEBUG
  32
  33 /*
  34  * Memory map for the ADS5121 board:
  35  *
  36  * 0x0000_0000 - 0x0FFF_FFFF    DDR RAM (256 MB)
  37  * 0x3000_0000 - 0x3001_FFFF    SRAM (128 KB)
  38  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
  39  * 0x8200_0000 - 0x8200_001F    CPLD (32 B)
  40  * 0xFC00_0000 - 0xFFFF_FFFF    NOR Boot FLASH (64 MB)
  41  */
  42
  43 /*
  44  * High Level Configuration Options
  45  */
  46 #define CONFIG_E300             1       /* E300 Family */
  47 #define CONFIG_MPC512X          1       /* MPC512X family */
  48
  49 #undef CONFIG_PCI
  50
  51 #define CFG_MPC512X_CLKIN       66000000        /* in Hz */
  52
  53 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f() */
  54
  55 #define CFG_IMMR                0x80000000
  56
  57 #define CFG_MEMTEST_START       0x00200000      /* memtest region */
  58 #define CFG_MEMTEST_END         0x00400000
  59
  60 /*
  61  * DDR Setup - manually set all parameters as there's no SPD etc.
  62  */
  63 #define CFG_DDR_SIZE            256             /* MB */
  64 #define CFG_DDR_BASE            0x00000000      /* DDR is system memory*/
  65 #define CFG_SDRAM_BASE          CFG_DDR_BASE
  66
  67 /* DDR Controller Configuration
  68  *
  69  * SYS_CFG:
  70  *      [31:31] MDDRC Soft Reset:       Diabled
  71  *      [30:30] DRAM CKE pin:           Enabled
  72  *      [29:29] DRAM CLK:               Enabled
  73  *      [28:28] Command Mode:           Enabled (For initialization only)
  74  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
  75  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
  76  *      [20:19] Read Test:              DON'T USE
  77  *      [18:18] Self Refresh:           Enabled
  78  *      [17:17] 16bit Mode:             Disabled
  79  *      [16:13] Ready Delay:            2
  80  *      [12:12] Half DQS Delay:         Disabled
  81  *      [11:11] Quarter DQS Delay:      Disabled
  82  *      [10:08] Write Delay:            2
  83  *      [07:07] Early ODT:              Disabled
  84  *      [06:06] On DIE Termination:     Disabled
  85  *      [05:05] FIFO Overflow Clear:    DON'T USE here
  86  *      [04:04] FIFO Underflow Clear:   DON'T USE here
  87  *      [03:03] FIFO Overflow Pending:  DON'T USE here
  88  *      [02:02] FIFO Underlfow Pending: DON'T USE here
  89  *      [01:01] FIFO Overlfow Enabled:  Enabled
  90  *      [00:00] FIFO Underflow Enabled: Enabled
  91  * TIME_CFG0
  92  *      [31:16] DRAM Refresh Time:      0 CSB clocks
  93  *      [15:8]  DRAM Command Time:      0 CSB clocks
  94  *      [07:00] DRAM Precharge Time:    0 CSB clocks
  95  * TIME_CFG1
  96  *      [31:26] DRAM tRFC:
  97  *      [25:21] DRAM tWR1:
  98  *      [20:17] DRAM tWRT1:
  99  *      [16:11] DRAM tDRR:
 100  *      [10:05] DRAM tRC:
 101  *      [04:00] DRAM tRAS:
 102  * TIME_CFG2
 103  *      [31:28] DRAM tRCD:
 104  *      [27:23] DRAM tFAW:
 105  *      [22:19] DRAM tRTW1:
 106  *      [18:15] DRAM tCCD:
 107  *      [14:10] DRAM tRTP:
 108  *      [09:05] DRAM tRP:
 109  *      [04:00] DRAM tRPA
 110  */
 111
 112 #define CFG_MDDRC_SYS_CFG       0xF8604200
 113 #define CFG_MDDRC_SYS_CFG_RUN   0xE8604200
 114 #define CFG_MDDRC_SYS_CFG_EN    0x30000000
 115 #define CFG_MDDRC_TIME_CFG0     0x0000281E
 116 #define CFG_MDDRC_TIME_CFG0_RUN 0x01F4281E
 117 #define CFG_MDDRC_TIME_CFG1     0x54EC1168
 118 #define CFG_MDDRC_TIME_CFG2     0x35210864
 119
 120 #define CFG_MICRON_NOP          0x01380000
 121 #define CFG_MICRON_PCHG_ALL     0x01100400
 122 #define CFG_MICRON_MR           0x01000022
 123 #define CFG_MICRON_EM2          0x01020000
 124 #define CFG_MICRON_EM3          0x01030000
 125 #define CFG_MICRON_EN_DLL       0x01010000
 126 #define CFG_MICRON_RST_DLL      0x01000932
 127 #define CFG_MICRON_RFSH         0x01080000
 128 #define CFG_MICRON_INIT_DEV_OP  0x01000832
 129 #define CFG_MICRON_OCD_DEFAULT  0x01010780
 130 #define CFG_MICRON_OCD_EXIT     0x01010400
 131
 132 /* DDR Priority Manager Configuration */
 133 #define CFG_MDDRCGRP_PM_CFG1    0x000777AA
 134 #define CFG_MDDRCGRP_PM_CFG2    0x00000055
 135 #define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000
 136 #define CFG_MDDRCGRP_LUT0_MU    0x11111117
 137 #define CFG_MDDRCGRP_LUT0_ML    0x7777777A
 138 #define CFG_MDDRCGRP_LUT1_MU    0x4444EEEE
 139 #define CFG_MDDRCGRP_LUT1_ML    0xEEEEEEEE
 140 #define CFG_MDDRCGRP_LUT2_MU    0x44444444
 141 #define CFG_MDDRCGRP_LUT2_ML    0x44444444
 142 #define CFG_MDDRCGRP_LUT3_MU    0x55555555
 143 #define CFG_MDDRCGRP_LUT3_ML    0x55555558
 144 #define CFG_MDDRCGRP_LUT4_MU    0x11111111
 145 #define CFG_MDDRCGRP_LUT4_ML    0x1111117C
 146 #define CFG_MDDRCGRP_LUT0_AU    0x33333377
 147 #define CFG_MDDRCGRP_LUT0_AL    0x7777EEEE
 148 #define CFG_MDDRCGRP_LUT1_AU    0x11111111
 149 #define CFG_MDDRCGRP_LUT1_AL    0x11111111
 150 #define CFG_MDDRCGRP_LUT2_AU    0x11111111
 151 #define CFG_MDDRCGRP_LUT2_AL    0x11111111
 152 #define CFG_MDDRCGRP_LUT3_AU    0x11111111
 153 #define CFG_MDDRCGRP_LUT3_AL    0x11111111
 154 #define CFG_MDDRCGRP_LUT4_AU    0x11111111
 155 #define CFG_MDDRCGRP_LUT4_AL    0x11111111
 156
 157 /*
 158  * NOR FLASH on the Local Bus
 159  */
 160 #define CFG_FLASH_CFI                           /* use the Common Flash Interface */
 161 #define CFG_FLASH_CFI_DRIVER                    /* use the CFI driver */
 162 #define CFG_FLASH_BASE          0xFC000000      /* start of FLASH   */
 163 #define CFG_FLASH_SIZE          0x04000000      /* max flash size in bytes */
 164 #define CFG_FLASH_USE_BUFFER_WRITE
 165
 166 #define CFG_MAX_FLASH_BANKS     1               /* number of banks */
 167 #define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
 168 #define CFG_MAX_FLASH_SECT      256             /* max sectors per device */
 169
 170 #undef CFG_FLASH_CHECKSUM
 171
 172 /*
 173  * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
 174  * window is 64KB
 175  */
 176 #define CFG_CPLD_BASE           0x82000000
 177 #define CFG_CPLD_SIZE           0x00010000      /* 64 KB */
 178
 179 #define CFG_SRAM_BASE           0x30000000
 180 #define CFG_SRAM_SIZE           0x00020000      /* 128 KB */
 181
 182 #define CFG_CS0_CFG             0x05059310      /* ALE active low, data size 4bytes */
 183 #define CFG_CS2_CFG             0x05059010      /* ALE active low, data size 1byte */
 184
 185 /* Use SRAM for initial stack */
 186 #define CFG_INIT_RAM_ADDR       CFG_SRAM_BASE           /* Initial RAM address */
 187 #define CFG_INIT_RAM_END        CFG_SRAM_SIZE           /* End of used area in RAM */
 188
 189 #define CFG_GBL_DATA_SIZE       0x100                   /* num bytes initial data */
 190 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 191 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 192
 193 #define CFG_MONITOR_BASE        TEXT_BASE               /* Start of monitor */
 194 #define CFG_MONITOR_LEN         (256 * 1024)            /* Reserve 256 kB for Mon */
 195 #define CFG_MALLOC_LEN          (512 * 1024)            /* Reserved for malloc */
 196
 197 /*
 198  * Serial Port
 199  */
 200 #define CONFIG_CONS_INDEX     1
 201 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 202
 203 /*
 204  * Serial console configuration
 205  */
 206 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 */
 207 #if CONFIG_PSC_CONSOLE != 3
 208 #error CONFIG_PSC_CONSOLE must be 3
 209 #endif
 210 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
 211 #define CFG_BAUDRATE_TABLE  \
 212         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 213
 214 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC3_TX_SIZE
 215 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC3_TX_ADDR
 216 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC3_RX_SIZE
 217 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC3_RX_ADDR
 218
 219 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 220 /* Use the HUSH parser */
 221 #define CFG_HUSH_PARSER
 222 #ifdef  CFG_HUSH_PARSER
 223 #define CFG_PROMPT_HUSH_PS2 "> "
 224 #endif
 225
 226 /* I2C */
 227 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 228 #undef CONFIG_SOFT_I2C                  /* so disable bit-banged I2C */
 229 #define CONFIG_I2C_MULTI_BUS
 230 #define CONFIG_I2C_CMD_TREE
 231 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address */
 232 #define CFG_I2C_SLAVE           0x7F
 233 #if 0
 234 #define CFG_I2C_NOPROBES        {{0,0x69}}      * Don't probe these addrs */
 235 #endif
 236
 237 /*
 238  * Ethernet configuration
 239  */
 240 #define CONFIG_MPC512x_FEC      1
 241 #define CONFIG_NET_MULTI
 242 #define CONFIG_PHY_ADDR         0x1
 243 #define CONFIG_MII              1       /* MII PHY management           */
 244
 245 #if 0
 246 /*
 247  * Configure on-board RTC
 248  */
 249 #define CONFIG_RTC_DS1374                       /* use ds1374 rtc via i2c       */
 250 #define CFG_I2C_RTC_ADDR                0x68    /* at address 0x68              */
 251 #endif
 252
 253 /*
 254  * Environment
 255  */
 256 #define CFG_ENV_IS_IN_FLASH     1
 257 /* This has to be a multiple of the Flash sector size */
 258 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 259 #define CFG_ENV_SIZE            0x2000
 260 #define CFG_ENV_SECT_SIZE       0x40000 /* one sector (256K) for env */
 261
 262 /* Address and size of Redundant Environment Sector     */
 263 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 264 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 265
 266 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 267 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 268
 269 #include <config_cmd_default.h>
 270
 271 #define CONFIG_CMD_ASKENV
 272 #define CONFIG_CMD_DHCP
 273 #define CONFIG_CMD_I2C
 274 #define CONFIG_CMD_MII
 275 #define CONFIG_CMD_NFS
 276 #define CONFIG_CMD_PING
 277 #define CONFIG_CMD_REGINFO
 278
 279 #if defined(CONFIG_PCI)
 280 #define CONFIG_CMD_PCI
 281 #endif
 282
 283 /*
 284  * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
 285  * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
 286  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
 287  * to chapter 36 of the MPC5121e Reference Manual.
 288  */
 289 #define CONFIG_WATCHDOG                 /* enable watchdog */
 290 #define CFG_WATCHDOG_VALUE 0xFFFF
 291
 292  /*
 293  * Miscellaneous configurable options
 294  */
 295 #define CFG_LONGHELP                    /* undef to save memory */
 296 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 297 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 298
 299 #ifdef CONFIG_CMD_KGDB
 300         #define CFG_CBSIZE      1024            /* Console I/O Buffer Size */
 301 #else
 302         #define CFG_CBSIZE      256             /* Console I/O Buffer Size */
 303 #endif
 304
 305
 306 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
 307 #define CFG_MAXARGS     16              /* max number of command args */
 308 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 309 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 310
 311 /*
 312  * For booting Linux, the board info and command line data
 313  * have to be in the first 8 MB of memory, since this is
 314  * the maximum mapped by the Linux kernel during initialization.
 315  */
 316 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 317
 318 /* Cache Configuration */
 319 #define CFG_DCACHE_SIZE         32768
 320 #define CFG_CACHELINE_SIZE      32
 321 #ifdef CONFIG_CMD_KGDB
 322 #define CFG_CACHELINE_SHIFT     5       /*log base 2 of the above value*/
 323 #endif
 324
 325 #define CFG_HID0_INIT   0x000000000
 326 #define CFG_HID0_FINAL  HID0_ENABLE_MACHINE_CHECK
 327 #define CFG_HID2        HID2_HBE
 328
 329 /*
 330  * Internal Definitions
 331  *
 332  * Boot Flags
 333  */
 334 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
 335 #define BOOTFLAG_WARM   0x02    /* Software reboot */
 336
 337 #ifdef CONFIG_CMD_KGDB
 338 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 339 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 340 #endif
 341
 342 /*
 343  * Environment Configuration
 344  */
 345 #define CONFIG_ENV_OVERWRITE
 346
 347 #define CONFIG_HOSTNAME         ads5121
 348 #define CONFIG_BOOTFILE         uImage
 349
 350 #define CONFIG_LOADADDR         200000  /* default location for tftp and bootm */
 351
 352 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 353 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 354
 355 #define CONFIG_BAUDRATE         115200
 356
 357 #define CONFIG_PREBOOT  "echo;" \
 358         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 359         "echo"
 360
 361 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 362         "netdev=eth0\0"                                                 \
 363         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 364                 "nfsroot=${serverip}:${rootpath}\0"                     \
 365         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 366         "addip=setenv bootargs ${bootargs} "                            \
 367                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 368                 ":${hostname}:${netdev}:off panic=1\0"                  \
 369         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 370         "flash_nfs=run nfsargs addip addtty;"                           \
 371                 "bootm ${kernel_addr}\0"                                \
 372         "flash_self=run ramargs addip addtty;"                          \
 373                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 374         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 375                 "bootm\0"                                               \
 376         "load=tftp 200000 /tftpboot/ads5121/u-boot.bin\0"               \
 377         "update=protect off FFF00000 +${filesize};"                     \
 378                 "era FFF00000 +${filesize};cp.b 200000 FFF00000 ${filesize}\0" \
 379         "upd=run load;run update\0"                                     \
 380         ""
 381
 382 #define CONFIG_NFSBOOTCOMMAND                                           \
 383         "setenv bootargs root=/dev/nfs rw "                             \
 384                 "nfsroot=$serverip:$rootpath "                          \
 385                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 386                 "console=$consoledev,$baudrate $othbootargs;"           \
 387         "tftp $loadaddr $bootfile;"                                     \
 388         "tftp $fdtaddr $fdtfile;"                                       \
 389         "bootm $loadaddr - $fdtaddr"
 390
 391 #define CONFIG_RAMBOOTCOMMAND                                           \
 392         "setenv bootargs root=/dev/ram rw "                             \
 393                 "console=$consoledev,$baudrate $othbootargs;"           \
 394         "tftp $ramdiskaddr $ramdiskfile;"                               \
 395         "tftp $loadaddr $bootfile;"                                     \
 396         "tftp $fdtaddr $fdtfile;"                                       \
 397         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 398
 399 #define CONFIG_BOOTCOMMAND      "run flash_self"
 400
 401 #endif  /* __CONFIG_H */