include/configs/ads5121.h

   1 /*
   2  * (C) Copyright 2007, 2008 DENX Software Engineering
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * ADS5121 board configuration file
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #define CONFIG_ADS5121 1
  31 /*
  32  * Memory map for the ADS5121 board:
  33  *
  34  * 0x0000_0000 - 0x0FFF_FFFF    DDR RAM (256 MB)
  35  * 0x3000_0000 - 0x3001_FFFF    SRAM (128 KB)
  36  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
  37  * 0x8200_0000 - 0x8200_001F    CPLD (32 B)
  38  * 0x8400_0000 - 0x82FF_FFFF    PCI I/O space (16 MB)
  39  * 0xA000_0000 - 0xAFFF_FFFF    PCI memory space (256 MB)
  40  * 0xB000_0000 - 0xBFFF_FFFF    PCI memory mapped I/O space (256 MB)
  41  * 0xFC00_0000 - 0xFFFF_FFFF    NOR Boot FLASH (64 MB)
  42  */
  43
  44 /*
  45  * High Level Configuration Options
  46  */
  47 #define CONFIG_E300             1       /* E300 Family */
  48 #define CONFIG_MPC512X          1       /* MPC512X family */
  49 #define CONFIG_FSL_DIU_FB       1       /* FSL DIU */
  50
  51 /* video */
  52 #undef CONFIG_VIDEO
  53
  54 #if defined(CONFIG_VIDEO)
  55 #define CONFIG_CFB_CONSOLE
  56 #define CONFIG_VGA_AS_SINGLE_DEVICE
  57 #endif
  58
  59 /* CONFIG_PCI is defined at config time */
  60
  61 #ifdef CONFIG_ADS5121_REV2
  62 #define CFG_MPC512X_CLKIN       66000000        /* in Hz */
  63 #else
  64 #define CFG_MPC512X_CLKIN       33333333        /* in Hz */
  65 #define CONFIG_PCI
  66 #endif
  67
  68 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f() */
  69 #define CONFIG_MISC_INIT_R
  70
  71 #define CFG_IMMR                0x80000000
  72 #define CFG_DIU_ADDR            (CFG_IMMR+0x2100)
  73
  74 #define CFG_MEMTEST_START       0x00200000      /* memtest region */
  75 #define CFG_MEMTEST_END         0x00400000
  76
  77 /*
  78  * DDR Setup - manually set all parameters as there's no SPD etc.
  79  */
  80 #ifdef CONFIG_ADS5121_REV2
  81 #define CFG_DDR_SIZE            256             /* MB */
  82 #else
  83 #define CFG_DDR_SIZE            512             /* MB */
  84 #endif
  85 #define CFG_DDR_BASE            0x00000000      /* DDR is system memory*/
  86 #define CFG_SDRAM_BASE          CFG_DDR_BASE
  87
  88 /* DDR Controller Configuration
  89  *
  90  * SYS_CFG:
  91  *      [31:31] MDDRC Soft Reset:       Diabled
  92  *      [30:30] DRAM CKE pin:           Enabled
  93  *      [29:29] DRAM CLK:               Enabled
  94  *      [28:28] Command Mode:           Enabled (For initialization only)
  95  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
  96  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
  97  *      [20:19] Read Test:              DON'T USE
  98  *      [18:18] Self Refresh:           Enabled
  99  *      [17:17] 16bit Mode:             Disabled
 100  *      [16:13] Ready Delay:            2
 101  *      [12:12] Half DQS Delay:         Disabled
 102  *      [11:11] Quarter DQS Delay:      Disabled
 103  *      [10:08] Write Delay:            2
 104  *      [07:07] Early ODT:              Disabled
 105  *      [06:06] On DIE Termination:     Disabled
 106  *      [05:05] FIFO Overflow Clear:    DON'T USE here
 107  *      [04:04] FIFO Underflow Clear:   DON'T USE here
 108  *      [03:03] FIFO Overflow Pending:  DON'T USE here
 109  *      [02:02] FIFO Underlfow Pending: DON'T USE here
 110  *      [01:01] FIFO Overlfow Enabled:  Enabled
 111  *      [00:00] FIFO Underflow Enabled: Enabled
 112  * TIME_CFG0
 113  *      [31:16] DRAM Refresh Time:      0 CSB clocks
 114  *      [15:8]  DRAM Command Time:      0 CSB clocks
 115  *      [07:00] DRAM Precharge Time:    0 CSB clocks
 116  * TIME_CFG1
 117  *      [31:26] DRAM tRFC:
 118  *      [25:21] DRAM tWR1:
 119  *      [20:17] DRAM tWRT1:
 120  *      [16:11] DRAM tDRR:
 121  *      [10:05] DRAM tRC:
 122  *      [04:00] DRAM tRAS:
 123  * TIME_CFG2
 124  *      [31:28] DRAM tRCD:
 125  *      [27:23] DRAM tFAW:
 126  *      [22:19] DRAM tRTW1:
 127  *      [18:15] DRAM tCCD:
 128  *      [14:10] DRAM tRTP:
 129  *      [09:05] DRAM tRP:
 130  *      [04:00] DRAM tRPA
 131  */
 132 #ifdef CONFIG_ADS5121_REV2
 133 #define CFG_MDDRC_SYS_CFG       0xF8604A00
 134 #define CFG_MDDRC_SYS_CFG_RUN   0xE8604A00
 135 #define CFG_MDDRC_TIME_CFG1     0x54EC1168
 136 #define CFG_MDDRC_TIME_CFG2     0x35210864
 137 #else
 138 #define CFG_MDDRC_SYS_CFG        0xFA804A00
 139 #define CFG_MDDRC_SYS_CFG_RUN    0xEA804A00
 140 #define CFG_MDDRC_TIME_CFG1      0x68EC1168
 141 #define CFG_MDDRC_TIME_CFG2      0x34310864
 142 #endif
 143 #define CFG_MDDRC_SYS_CFG_EN    0xF0000000
 144 #define CFG_MDDRC_TIME_CFG0     0x00003D2E
 145 #define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E
 146
 147 #define CFG_MICRON_NOP          0x01380000
 148 #define CFG_MICRON_PCHG_ALL     0x01100400
 149 #define CFG_MICRON_EM2          0x01020000
 150 #define CFG_MICRON_EM3          0x01030000
 151 #define CFG_MICRON_EN_DLL       0x01010000
 152 #define CFG_MICRON_RFSH         0x01080000
 153 #define CFG_MICRON_INIT_DEV_OP  0x01000432
 154 #define CFG_MICRON_OCD_DEFAULT  0x01010780
 155
 156 /* DDR Priority Manager Configuration */
 157 #define CFG_MDDRCGRP_PM_CFG1    0x00077777
 158 #define CFG_MDDRCGRP_PM_CFG2    0x00000000
 159 #define CFG_MDDRCGRP_HIPRIO_CFG 0x00000001
 160 #define CFG_MDDRCGRP_LUT0_MU    0xFFEEDDCC
 161 #define CFG_MDDRCGRP_LUT0_ML    0xBBAAAAAA
 162 #define CFG_MDDRCGRP_LUT1_MU    0x66666666
 163 #define CFG_MDDRCGRP_LUT1_ML    0x55555555
 164 #define CFG_MDDRCGRP_LUT2_MU    0x44444444
 165 #define CFG_MDDRCGRP_LUT2_ML    0x44444444
 166 #define CFG_MDDRCGRP_LUT3_MU    0x55555555
 167 #define CFG_MDDRCGRP_LUT3_ML    0x55555558
 168 #define CFG_MDDRCGRP_LUT4_MU    0x11111111
 169 #define CFG_MDDRCGRP_LUT4_ML    0x11111122
 170 #define CFG_MDDRCGRP_LUT0_AU    0xaaaaaaaa
 171 #define CFG_MDDRCGRP_LUT0_AL    0xaaaaaaaa
 172 #define CFG_MDDRCGRP_LUT1_AU    0x66666666
 173 #define CFG_MDDRCGRP_LUT1_AL    0x66666666
 174 #define CFG_MDDRCGRP_LUT2_AU    0x11111111
 175 #define CFG_MDDRCGRP_LUT2_AL    0x11111111
 176 #define CFG_MDDRCGRP_LUT3_AU    0x11111111
 177 #define CFG_MDDRCGRP_LUT3_AL    0x11111111
 178 #define CFG_MDDRCGRP_LUT4_AU    0x11111111
 179 #define CFG_MDDRCGRP_LUT4_AL    0x11111111
 180
 181 /*
 182  * NOR FLASH on the Local Bus
 183  */
 184 #undef CONFIG_BKUP_FLASH
 185 #define CFG_FLASH_CFI                           /* use the Common Flash Interface */
 186 #define CFG_FLASH_CFI_DRIVER                    /* use the CFI driver */
 187 #ifdef CONFIG_BKUP_FLASH
 188 #define CFG_FLASH_BASE          0xFF800000      /* start of FLASH   */
 189 #define CFG_FLASH_SIZE          0x00800000      /* max flash size in bytes */
 190 #else
 191 #define CFG_FLASH_BASE          0xFC000000      /* start of FLASH   */
 192 #define CFG_FLASH_SIZE          0x04000000      /* max flash size in bytes */
 193 #endif
 194 #define CFG_FLASH_USE_BUFFER_WRITE
 195 #define CFG_MAX_FLASH_BANKS     1               /* number of banks */
 196 #define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
 197 #define CFG_MAX_FLASH_SECT      256             /* max sectors per device */
 198
 199 #undef CFG_FLASH_CHECKSUM
 200
 201 /*
 202  * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
 203  * window is 64KB
 204  */
 205 #define CFG_CPLD_BASE           0x82000000
 206 #define CFG_CPLD_SIZE           0x00010000      /* 64 KB */
 207
 208 #define CFG_SRAM_BASE           0x30000000
 209 #define CFG_SRAM_SIZE           0x00020000      /* 128 KB */
 210
 211 #define CFG_CS0_CFG             0x05059310      /* ALE active low, data size 4bytes */
 212 #define CFG_CS2_CFG             0x05059010      /* ALE active low, data size 1byte */
 213
 214 /* Use SRAM for initial stack */
 215 #define CFG_INIT_RAM_ADDR       CFG_SRAM_BASE           /* Initial RAM address */
 216 #define CFG_INIT_RAM_END        CFG_SRAM_SIZE           /* End of used area in RAM */
 217
 218 #define CFG_GBL_DATA_SIZE       0x100                   /* num bytes initial data */
 219 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 220 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 221
 222 #define CFG_MONITOR_BASE        TEXT_BASE               /* Start of monitor */
 223 #define CFG_MONITOR_LEN         (256 * 1024)            /* Reserve 256 kB for Mon */
 224 #ifdef  CONFIG_FSL_DIU_FB
 225 #define CFG_MALLOC_LEN          (6 * 1024 * 1024)       /* Reserved for malloc */
 226 #else
 227 #define CFG_MALLOC_LEN          (512 * 1024)
 228 #endif
 229
 230 /*
 231  * Serial Port
 232  */
 233 #define CONFIG_CONS_INDEX     1
 234 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 235
 236 /*
 237  * Serial console configuration
 238  */
 239 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 */
 240 #if CONFIG_PSC_CONSOLE != 3
 241 #error CONFIG_PSC_CONSOLE must be 3
 242 #endif
 243 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
 244 #define CFG_BAUDRATE_TABLE  \
 245         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 246
 247 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC3_TX_SIZE
 248 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC3_TX_ADDR
 249 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC3_RX_SIZE
 250 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC3_RX_ADDR
 251
 252 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 253 /* Use the HUSH parser */
 254 #define CFG_HUSH_PARSER
 255 #ifdef  CFG_HUSH_PARSER
 256 #define CFG_PROMPT_HUSH_PS2 "> "
 257 #endif
 258
 259 /*
 260  * PCI
 261  */
 262 #ifdef CONFIG_PCI
 263
 264 /*
 265  * General PCI
 266  */
 267 #define CFG_PCI_MEM_BASE        0xA0000000
 268 #define CFG_PCI_MEM_PHYS        CFG_PCI_MEM_BASE
 269 #define CFG_PCI_MEM_SIZE        0x10000000      /* 256M */
 270 #define CFG_PCI_MMIO_BASE       (CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE)
 271 #define CFG_PCI_MMIO_PHYS       CFG_PCI_MMIO_BASE
 272 #define CFG_PCI_MMIO_SIZE       0x10000000      /* 256M */
 273 #define CFG_PCI_IO_BASE         0x00000000
 274 #define CFG_PCI_IO_PHYS         0x84000000
 275 #define CFG_PCI_IO_SIZE         0x01000000      /* 16M */
 276
 277
 278 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 279
 280 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 281
 282 #endif
 283
 284 /* I2C */
 285 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 286 #undef CONFIG_SOFT_I2C                  /* so disable bit-banged I2C */
 287 #define CONFIG_I2C_MULTI_BUS
 288 #define CONFIG_I2C_CMD_TREE
 289 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address */
 290 #define CFG_I2C_SLAVE           0x7F
 291 #if 0
 292 #define CFG_I2C_NOPROBES        {{0,0x69}}      /* Don't probe these addrs */
 293 #endif
 294
 295 /*
 296  * EEPROM configuration
 297  */
 298 #define CFG_I2C_EEPROM_ADDR_LEN         2       /* 16-bit EEPROM address */
 299 #define CFG_I2C_EEPROM_ADDR             0x50    /* Atmel: AT24C32A-10TQ-2.7 */
 300 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* 10ms of delay */
 301 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* 32-Byte Page Write Mode */
 302
 303 /*
 304  * Ethernet configuration
 305  */
 306 #define CONFIG_MPC512x_FEC      1
 307 #define CONFIG_NET_MULTI
 308 #define CONFIG_PHY_ADDR         0x1
 309 #define CONFIG_MII              1       /* MII PHY management           */
 310 #define CONFIG_FEC_AN_TIMEOUT   1
 311 #define CONFIG_HAS_ETH0
 312
 313 /*
 314  * Configure on-board RTC
 315  */
 316 #define CONFIG_RTC_M41T62                       /* use M41T62 rtc via i2 */
 317 #define CFG_I2C_RTC_ADDR                0x68    /* at address 0x68              */
 318
 319 /*
 320  * Environment
 321  */
 322 #define CFG_ENV_IS_IN_FLASH     1
 323 /* This has to be a multiple of the Flash sector size */
 324 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 325 #define CFG_ENV_SIZE            0x2000
 326 #ifdef CONFIG_BKUP_FLASH
 327 #define CFG_ENV_SECT_SIZE       0x20000 /* one sector (256K) for env */
 328 #else
 329 #define CFG_ENV_SECT_SIZE       0x40000 /* one sector (256K) for env */
 330 #endif
 331
 332 /* Address and size of Redundant Environment Sector     */
 333 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 334 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 335
 336 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 337 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 338
 339 #include <config_cmd_default.h>
 340
 341 #define CONFIG_CMD_ASKENV
 342 #define CONFIG_CMD_DHCP
 343 #define CONFIG_CMD_I2C
 344 #define CONFIG_CMD_MII
 345 #define CONFIG_CMD_NFS
 346 #define CONFIG_CMD_PING
 347 #define CONFIG_CMD_REGINFO
 348 #define CONFIG_CMD_EEPROM
 349 #define CONFIG_CMD_DATE
 350
 351 #if defined(CONFIG_PCI)
 352 #define CONFIG_CMD_PCI
 353 #endif
 354
 355 /*
 356  * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock.
 357  * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set
 358  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
 359  * to chapter 36 of the MPC5121e Reference Manual.
 360  */
 361 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
 362 #define CFG_WATCHDOG_VALUE 0xFFFF
 363
 364  /*
 365  * Miscellaneous configurable options
 366  */
 367 #define CFG_LONGHELP                    /* undef to save memory */
 368 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 369 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 370
 371 #ifdef CONFIG_CMD_KGDB
 372         #define CFG_CBSIZE      1024    /* Console I/O Buffer Size */
 373 #else
 374         #define CFG_CBSIZE      256     /* Console I/O Buffer Size */
 375 #endif
 376
 377
 378 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
 379 #define CFG_MAXARGS     16              /* max number of command args */
 380 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 381 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 382
 383 /*
 384  * For booting Linux, the board info and command line data
 385  * have to be in the first 8 MB of memory, since this is
 386  * the maximum mapped by the Linux kernel during initialization.
 387  */
 388 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 389
 390 /* Cache Configuration */
 391 #define CFG_DCACHE_SIZE         32768
 392 #define CFG_CACHELINE_SIZE      32
 393 #ifdef CONFIG_CMD_KGDB
 394 #define CFG_CACHELINE_SHIFT     5       /*log base 2 of the above value*/
 395 #endif
 396
 397 #define CFG_HID0_INIT   0x000000000
 398 #define CFG_HID0_FINAL  HID0_ENABLE_MACHINE_CHECK
 399 #define CFG_HID2        HID2_HBE
 400
 401 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 402
 403 /*
 404  * Internal Definitions
 405  *
 406  * Boot Flags
 407  */
 408 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 409 #define BOOTFLAG_WARM           0x02    /* Software reboot */
 410
 411 #ifdef CONFIG_CMD_KGDB
 412 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 413 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 414 #endif
 415
 416 /*
 417  * Environment Configuration
 418  */
 419 #define CONFIG_TIMESTAMP
 420
 421 #define CONFIG_HOSTNAME         ads5121
 422 #define CONFIG_BOOTFILE         ads5121/uImage
 423 #define CONFIG_ROOTPATH         /opt/eldk/pcc_6xx
 424
 425 #define CONFIG_LOADADDR         400000  /* default location for tftp and bootm */
 426
 427 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 428 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 429
 430 #define CONFIG_BAUDRATE         115200
 431
 432 #define CONFIG_PREBOOT  "echo;" \
 433         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 434         "echo"
 435
 436 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 437         "u-boot_addr_r=200000\0"                                        \
 438         "kernel_addr_r=300000\0"                                        \
 439         "fdt_addr_r=400000\0"                                           \
 440         "ramdisk_addr_r=500000\0"                                       \
 441         "u-boot_addr=FFF00000\0"                                        \
 442         "kernel_addr=FC040000\0"                                        \
 443         "fdt_addr=FC2C0000\0"                                           \
 444         "ramdisk_addr=FC300000\0"                                       \
 445         "ramdiskfile=ads5121/uRamdisk\0"                                \
 446         "fdtfile=ads5121/ads5121.dtb\0"                                 \
 447         "u-boot=ads5121/u-boot.bin\0"                                   \
 448         "netdev=eth0\0"                                                 \
 449         "consdev=ttyPSC0\0"                                             \
 450         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 451                 "nfsroot=${serverip}:${rootpath}\0"                     \
 452         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 453         "addip=setenv bootargs ${bootargs} "                            \
 454                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 455                 ":${hostname}:${netdev}:off panic=1\0"                  \
 456         "addtty=setenv bootargs ${bootargs} "                           \
 457                 "console=${consdev},${baudrate}\0"                      \
 458         "flash_nfs=run nfsargs addip addtty;"                           \
 459                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 460         "flash_self=run ramargs addip addtty;"                          \
 461                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 462         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 463                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 464                 "run nfsargs addip addtty;"                             \
 465                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 466         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
 467                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
 468                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 469                 "run ramargs addip addtty;"                             \
 470                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
 471         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 472         "update=protect off ${u-boot_addr} +${filesize};"               \
 473                 "era ${u-boot_addr} +${filesize};"                      \
 474                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
 475         "upd=run load update\0"                                         \
 476         ""
 477
 478 #define CONFIG_BOOTCOMMAND      "run flash_self"
 479
 480 #define CONFIG_OF_LIBFDT        1
 481 #define CONFIG_OF_BOARD_SETUP   1
 482 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
 483
 484 #define OF_CPU                  "PowerPC,5121@0"
 485 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 486 #define OF_TBCLK                (bd->bi_busfreq / 4)
 487 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
 488
 489 #endif  /* __CONFIG_H */