include/configs/alpr.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*-----------------------------------------------------------------------
  28  * High Level Configuration Options
  29  *----------------------------------------------------------------------*/
  30 #define CONFIG_ALPR             1           /* Board is ebony           */
  31 #define CONFIG_440GX            1           /* Specifc GX support       */
  32 #define CONFIG_440              1           /* ... PPC440 family        */
  33 #define CONFIG_4xx              1           /* ... PPC4xx family        */
  34 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_pre_init      */
  35 #define CONFIG_LAST_STAGE_INIT  1           /* call last_stage_init()   */
  36
  37 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  38
  39 #define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  40 #define CONFIG_4xx_DCACHE               /* Enable i- and d-cache        */
  41
  42 /*-----------------------------------------------------------------------
  43  * Base addresses -- Note these are effective addresses where the
  44  * actual resources get mapped (not physical addresses)
  45  *----------------------------------------------------------------------*/
  46 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0                  */
  47 #define CONFIG_SYS_FLASH_BASE           0xffe00000      /* start of FLASH               */
  48 #define CONFIG_SYS_MONITOR_BASE 0xfffc0000      /* start of monitor             */
  49 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory            */
  50 #define CONFIG_SYS_PCI_MEMSIZE          0x40000000      /* size of mapped pci memory    */
  51 #define CONFIG_SYS_ISRAM_BASE           0xc0000000      /* internal SRAM                */
  52 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs            */
  53 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  54 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  55 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  56
  57
  58 #define CONFIG_SYS_FPGA_BASE        (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
  59 #define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
  60
  61 /*-----------------------------------------------------------------------
  62  * Initial RAM & stack pointer (placed in internal SRAM)
  63  *----------------------------------------------------------------------*/
  64 #define CONFIG_SYS_TEMP_STACK_OCM  1
  65 #define CONFIG_SYS_OCM_DATA_ADDR   CONFIG_SYS_ISRAM_BASE
  66 #define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address        */
  67 #define CONFIG_SYS_INIT_RAM_END    0x2000           /* End of used area in RAM  */
  68 #define CONFIG_SYS_GBL_DATA_SIZE   128              /* num bytes initial data   */
  69
  70 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  71 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  72
  73 #define CONFIG_SYS_MONITOR_LEN      (256 * 1024)    /* Reserve 256 kB for Mon   */
  74 #define CONFIG_SYS_MALLOC_LEN       (128 * 1024)    /* Reserve 128 kB for malloc*/
  75
  76 /*-----------------------------------------------------------------------
  77  * Serial Port
  78  *----------------------------------------------------------------------*/
  79 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
  80 #define CONFIG_SYS_NS16550
  81 #define CONFIG_SYS_NS16550_SERIAL
  82 #define CONFIG_SYS_NS16550_REG_SIZE     1
  83 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  84
  85 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK
  86 #define CONFIG_BAUDRATE         115200
  87
  88 #define CONFIG_SYS_BAUDRATE_TABLE  \
  89     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  90
  91 /*-----------------------------------------------------------------------
  92  * FLASH related
  93  *----------------------------------------------------------------------*/
  94 #define CONFIG_SYS_FLASH_CFI            1       /* The flash is CFI compatible          */
  95 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use common CFI driver                */
  96 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
  97 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
  98 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
  99 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 100 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 101
 102 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
 103
 104 #define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector          */
 105 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 106 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 107
 108 /* Address and size of Redundant Environment Sector     */
 109 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 110 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 111
 112 /*-----------------------------------------------------------------------
 113  * DDR SDRAM
 114  *----------------------------------------------------------------------*/
 115 #undef CONFIG_SPD_EEPROM                /* Don't use SPD EEPROM for setup       */
 116 #define CONFIG_SDRAM_BANK0      1       /* init onboard DDR SDRAM bank 0        */
 117 #undef CONFIG_SDRAM_ECC                 /* enable ECC support                   */
 118 #define CONFIG_SYS_SDRAM_TABLE  { \
 119                 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
 120                 {(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)  */
 121
 122 /*-----------------------------------------------------------------------
 123  * I2C
 124  *----------------------------------------------------------------------*/
 125 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 126 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 127 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 128 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
 129 #define CONFIG_SYS_I2C_SLAVE            0x7F
 130 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs      */
 131
 132 /*-----------------------------------------------------------------------
 133  * I2C EEPROM (PCF8594C)
 134  *----------------------------------------------------------------------*/
 135 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x54    /* EEPROM PCF8594C              */
 136 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 137 /* mask of address bits that overflow into the "EEPROM chip address"    */
 138 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 139 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3     /* The Philips PCF8594C has     */
 140                                         /* 8 byte page write mode using */
 141                                         /* last 3 bits of the address   */
 142 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   40   /* and takes up to 40 msec */
 143
 144 #define CONFIG_PREBOOT  "echo;" \
 145         "echo Type \"run kernelx\" to boot the system;"                 \
 146         "echo"
 147
 148 #undef  CONFIG_BOOTARGS
 149
 150 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 151         "netdev=eth3\0"                                                 \
 152         "hostname=alpr\0"                                               \
 153         "fdt_file=alpr/alpr.dtb\0"                                      \
 154         "fdt_addr=400000\0"                                             \
 155         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 156                 "nfsroot=${serverip}:${rootpath} ${init}\0"             \
 157         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 158         "addip=setenv bootargs ${bootargs} "                            \
 159                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 160                 ":${hostname}:${netdev}:off panic=1\0"                  \
 161         "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
 162                 "mem=193M\0"                                            \
 163         "flash_nfs=run nfsargs addip addtty;"                           \
 164                 "bootm ${kernel_addr}\0"                                \
 165         "flash_self=run ramargs addip addtty;"                          \
 166                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 167         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 168                 "bootm\0"                                               \
 169         "net_nfs_fdt=tftp 200000 ${bootfile};"                          \
 170                 "tftp ${fdt_addr} ${fdt_file};"                         \
 171                 "run nfsargs addip addtty;"                             \
 172                 "bootm 200000 - ${fdt_addr}\0"                          \
 173         "rootpath=/opt/projects/alpr/nfs_root\0"                        \
 174         "bootfile=/alpr/uImage\0"                                       \
 175         "kernel_addr=fff00000\0"                                        \
 176         "ramdisk_addr=fff10000\0"                                       \
 177         "load=tftp 100000 /alpr/u-boot/u-boot.bin\0"                    \
 178         "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"   \
 179                 "cp.b 100000 fffc0000 40000;"                           \
 180                 "setenv filesize;saveenv\0"                             \
 181         "upd=run load update\0"                                         \
 182         "ethprime=ppc_4xx_eth3\0"                                       \
 183         "ethact=ppc_4xx_eth3\0"                                         \
 184         "autoload=no\0"                                                 \
 185         "ipconfig=dhcp;setenv serverip 11.0.0.152\0"                    \
 186         "load_fpga=fpga load 0 ffe00000 10dd9a\0"                       \
 187         "mtdargs=setenv bootargs root=/dev/mtdblock6 rw "               \
 188                 "rootfstype=jffs2 init=/sbin/init\0"                    \
 189         "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
 190                 ";bootm 200000\0"                                       \
 191         "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
 192                 "addtty;bootm 200000\0"                                 \
 193         "kernel1=setenv actkernel 'kernel1';run load_fpga "             \
 194                 "kernel1_mtd\0"                                         \
 195         "kernel2=setenv actkernel 'kernel2';run load_fpga "             \
 196                 "kernel2_mtd\0"                                         \
 197         ""
 198
 199 #define CONFIG_BOOTCOMMAND      "run kernel2"
 200
 201 #define CONFIG_BOOTDELAY        2       /* autoboot after 5 seconds     */
 202
 203 #define CONFIG_BAUDRATE         115200
 204
 205 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 206 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 207
 208 #define CONFIG_PPC4xx_EMAC
 209 #define CONFIG_MII              1       /* MII PHY management           */
 210 #define CONFIG_NET_MULTI        1
 211 #define CONFIG_PHY_ADDR         0x02    /* dummy setting, no EMAC0 used */
 212 #define CONFIG_PHY1_ADDR        0x03    /* dummy setting, no EMAC1 used */
 213 #define CONFIG_PHY2_ADDR        0x01    /* PHY address for EMAC2        */
 214 #define CONFIG_PHY3_ADDR        0x02    /* PHY address for EMAC3        */
 215 #define CONFIG_HAS_ETH0
 216 #define CONFIG_HAS_ETH1
 217 #define CONFIG_HAS_ETH2
 218 #define CONFIG_HAS_ETH3
 219 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 220 #define CONFIG_M88E1111_PHY     1       /* needed for PHY specific setup*/
 221 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 222 #define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 223
 224 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
 225
 226
 227 /*
 228  * BOOTP options
 229  */
 230 #define CONFIG_BOOTP_BOOTFILESIZE
 231 #define CONFIG_BOOTP_BOOTPATH
 232 #define CONFIG_BOOTP_GATEWAY
 233 #define CONFIG_BOOTP_HOSTNAME
 234
 235
 236 /*
 237  * Command line configuration.
 238  */
 239 #include <config_cmd_default.h>
 240
 241 #define CONFIG_CMD_DHCP
 242 #define CONFIG_CMD_EEPROM
 243 #define CONFIG_CMD_FPGA
 244 #define CONFIG_CMD_I2C
 245 #undef CONFIG_CMD_LOADB
 246 #undef CONFIG_CMD_LOADS
 247 #define CONFIG_CMD_MII
 248 #define CONFIG_CMD_NAND
 249 #define CONFIG_CMD_NET
 250 #undef CONFIG_CMD_NFS
 251 #define CONFIG_CMD_PCI
 252
 253 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 254
 255 /*
 256  * Miscellaneous configurable options
 257  */
 258 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 259 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 260 #if defined(CONFIG_CMD_KGDB)
 261 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 262 #else
 263 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 264 #endif
 265 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 266 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 267 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 268
 269 #define CONFIG_SYS_ALT_MEMTEST          1       /* Enable more extensive memtest*/
 270 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 271 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 272
 273 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 274 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 275
 276 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 277
 278 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 279 #define CONFIG_LOOPW            1       /* enable loopw command         */
 280 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 281 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 282 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 283
 284 #define CONFIG_SYS_4xx_RESET_TYPE       0x2     /* use chip reset on this board */
 285
 286 /*-----------------------------------------------------------------------
 287  * PCI stuff
 288  *-----------------------------------------------------------------------
 289  */
 290 /* General PCI */
 291 #define CONFIG_PCI                      /* include pci support          */
 292 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 293 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 294 #define CONFIG_SYS_PCI_TARGBASE    0x80000000   /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 295 #define CONFIG_PCI_BOOTDELAY    1       /* enable pci bootdelay variable*/
 296
 297 /* Board-specific PCI */
 298 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 299 #define CONFIG_SYS_PCI_MASTER_INIT
 300
 301 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
 302 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever */
 303
 304 /*-----------------------------------------------------------------------
 305  * FPGA stuff
 306  *-----------------------------------------------------------------------*/
 307 #define CONFIG_FPGA
 308 #define CONFIG_FPGA_ALTERA
 309 #define CONFIG_FPGA_CYCLON2
 310 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 311 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 312 #define CONFIG_FPGA_COUNT       1               /* Ich habe 2 ... aber in
 313                                         Reihe geschaltet -> sollte gehen,
 314                                         aufpassen mit Datasize ist jetzt
 315                                         halt doppelt so gross ... Seite 306
 316                                         ist das mit den multiple Device in PS
 317                                         Mode erklaert ...*/
 318
 319 /* FPGA program pin configuration */
 320 #define CONFIG_SYS_GPIO_CLK             18      /* FPGA clk pin (cpu output)            */
 321 #define CONFIG_SYS_GPIO_DATA            19      /* FPGA data pin (cpu output)           */
 322 #define CONFIG_SYS_GPIO_STATUS          20      /* FPGA status pin (cpu input)          */
 323 #define CONFIG_SYS_GPIO_CONFIG          21      /* FPGA CONFIG pin (cpu output)         */
 324 #define CONFIG_SYS_GPIO_CON_DON 22      /* FPGA CONFIG_DONE pin (cpu input)     */
 325
 326 #define CONFIG_SYS_GPIO_SEL_DPR 14      /* cpu output */
 327 #define CONFIG_SYS_GPIO_SEL_AVR 15      /* cpu output */
 328 #define CONFIG_SYS_GPIO_PROG_EN 23      /* cpu output */
 329
 330 /*-----------------------------------------------------------------------
 331  * Definitions for GPIO setup
 332  *-----------------------------------------------------------------------*/
 333 #define CONFIG_SYS_GPIO_SHUTDOWN        (0x80000000 >> 6)
 334 #define CONFIG_SYS_GPIO_SSD_EMPTY       (0x80000000 >> 9)
 335 #define CONFIG_SYS_GPIO_EREADY          (0x80000000 >> 26)
 336 #define CONFIG_SYS_GPIO_REV0            (0x80000000 >> 14)
 337 #define CONFIG_SYS_GPIO_REV1            (0x80000000 >> 15)
 338
 339 /*-----------------------------------------------------------------------
 340  * NAND-FLASH stuff
 341  *-----------------------------------------------------------------------*/
 342 #define CONFIG_SYS_MAX_NAND_DEVICE      4
 343 #define CONFIG_SYS_NAND_BASE            0xF0000000      /* NAND FLASH Base Address      */
 344 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2,   \
 345                                   CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
 346 #define CONFIG_SYS_NAND_QUIET_TEST      1       /* don't warn upon unknown NAND flash   */
 347
 348 /*-----------------------------------------------------------------------
 349  * External Bus Controller (EBC) Setup
 350  *----------------------------------------------------------------------*/
 351 #define CONFIG_SYS_FLASH                CONFIG_SYS_FLASH_BASE
 352
 353 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 354 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 355 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
 356
 357 /* Memory Bank 1 (NAND-FLASH) initialization                                    */
 358 #define CONFIG_SYS_EBC_PB1AP            0x01840380      /* TWT=3                        */
 359 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
 360
 361 /*
 362  * For booting Linux, the board info and command line data
 363  * have to be in the first 8 MB of memory, since this is
 364  * the maximum mapped by the Linux kernel during initialization.
 365  */
 366 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 367
 368 /*
 369  * Internal Definitions
 370  *
 371  * Boot Flags
 372  */
 373 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 374 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 375
 376 #if defined(CONFIG_CMD_KGDB)
 377 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 378 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 379 #endif
 380
 381 /* pass open firmware flat tree */
 382 #define CONFIG_OF_LIBFDT        1
 383 #define CONFIG_OF_BOARD_SETUP   1
 384
 385 #endif  /* __CONFIG_H */