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git.ipfire.org Git - thirdparty/u-boot.git/blob - include/configs/alt.h
2 * include/configs/alt.h
3 * This file is alt board configuration.
5 * Copyright (C) 2014 Renesas Electronics Corporation
7 * SPDX-License-Identifier: GPL-2.0
14 #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Alt"
16 #include "rcar-gen2-common.h"
18 #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
19 #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
21 #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
23 #define STACK_AREA_SIZE 0xC000
24 #define LOW_LEVEL_MERAM_STACK \
25 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
28 #define RCAR_GEN2_SDRAM_BASE 0x40000000
29 #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
30 #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
36 #define CONFIG_SH_QSPI
37 #define CONFIG_SPI_FLASH_QUAD
40 #define CONFIG_SH_ETHER_USE_PORT 0
41 #define CONFIG_SH_ETHER_PHY_ADDR 0x1
42 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
43 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
44 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
45 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64
46 #define CONFIG_BITBANGMII
47 #define CONFIG_BITBANGMII_MULTI
50 #define RMOBILE_XTAL_CLK 20000000u
51 #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
52 #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
53 #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
54 #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
56 #define CONFIG_SYS_TMU_CLK_DIV 4
59 #define CONFIG_SYS_I2C
60 #define CONFIG_SYS_I2C_SH
61 #define CONFIG_SYS_I2C_SLAVE 0x7F
62 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
63 #define CONFIG_SYS_I2C_SH_SPEED0 400000
64 #define CONFIG_SYS_I2C_SH_SPEED1 400000
65 #define CONFIG_SYS_I2C_SH_SPEED2 400000
66 #define CONFIG_SH_I2C_DATA_HIGH 4
67 #define CONFIG_SH_I2C_DATA_LOW 5
68 #define CONFIG_SH_I2C_CLOCK 10000000
70 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
73 #define CONFIG_USB_EHCI_RMOBILE
74 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
77 #define CONFIG_SH_MMCIF
78 #define CONFIG_SH_MMCIF_ADDR 0xee200000
79 #define CONFIG_SH_MMCIF_CLK 48000000
81 /* Module stop status bits */
83 #define CONFIG_SMSTP0_ENA 0x00400000
85 #define CONFIG_SMSTP2_ENA 0x00002000
87 #define CONFIG_SMSTP4_ENA 0x00000180
89 #define CONFIG_SMSTP7_ENA 0x00080000
92 #define CONFIG_SH_SDHI_FREQ 97500000