include/configs/am3517_crane.h

   1 /*
   2  * am3517_crane.h - Default configuration for AM3517 CraneBoard.
   3  *
   4  * Author: Srinath.R <srinath@mistralsolutions.com>
   5  *
   6  * Based on include/configs/am3517evm.h
   7  *
   8  * Copyright (C) 2011 Mistral Solutions pvt Ltd
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 /*
  29  * High Level Configuration Options
  30  */
  31 #define CONFIG_OMAP             1       /* in a TI OMAP core */
  32 #define CONFIG_OMAP34XX         1       /* which is a 34XX */
  33 #define CONFIG_OMAP3_AM3517CRANE        1       /* working with CRANEBOARD */
  34
  35 #define CONFIG_EMIF4    /* The chip has EMIF4 controller */
  36
  37 #include <asm/arch/cpu.h>               /* get chip and board defs */
  38 #include <asm/arch/omap3.h>
  39
  40 /*
  41  * Display CPU and Board information
  42  */
  43 #define CONFIG_DISPLAY_CPUINFO          1
  44 #define CONFIG_DISPLAY_BOARDINFO        1
  45
  46 /* Clock Defines */
  47 #define V_OSCK                  26000000        /* Clock output from T2 */
  48 #define V_SCLK                  (V_OSCK >> 1)
  49
  50 #define CONFIG_MISC_INIT_R
  51
  52 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  53 #define CONFIG_SETUP_MEMORY_TAGS        1
  54 #define CONFIG_INITRD_TAG               1
  55 #define CONFIG_REVISION_TAG             1
  56
  57 /*
  58  * Size of malloc() pool
  59  */
  60 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
  61 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
  62                                                 /* initial data */
  63 /*
  64  * DDR related
  65  */
  66 #define CONFIG_SYS_CS0_SIZE             (256 * 1024 * 1024)
  67
  68 /*
  69  * Hardware drivers
  70  */
  71
  72 /*
  73  * NS16550 Configuration
  74  */
  75 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  76
  77 #define CONFIG_SYS_NS16550
  78 #define CONFIG_SYS_NS16550_SERIAL
  79 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  80 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  81
  82 /*
  83  * select serial console configuration
  84  */
  85 #define CONFIG_CONS_INDEX               3
  86 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  87 #define CONFIG_SERIAL3                  3       /* UART3 on CRANEBOARD */
  88
  89 /* allow to overwrite serial and ethaddr */
  90 #define CONFIG_ENV_OVERWRITE
  91 #define CONFIG_BAUDRATE                 115200
  92 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  93                                         115200}
  94 #define CONFIG_GENERIC_MMC              1
  95 #define CONFIG_MMC                      1
  96 #define CONFIG_OMAP_HSMMC               1
  97 #define CONFIG_DOS_PARTITION            1
  98
  99 /*
 100  * USB configuration
 101  * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
 102  * Enable CONFIG_MUSB_UDC for Device functionalities.
 103  */
 104 #define CONFIG_USB_AM35X                1
 105 #define CONFIG_MUSB_HCD                 1
 106
 107 #ifdef CONFIG_USB_AM35X
 108
 109 #ifdef CONFIG_MUSB_HCD
 110 #define CONFIG_CMD_USB
 111
 112 #define CONFIG_USB_STORAGE
 113 #define CONGIG_CMD_STORAGE
 114 #define CONFIG_CMD_FAT
 115
 116 #ifdef CONFIG_USB_KEYBOARD
 117 #define CONFIG_SYS_USB_EVENT_POLL
 118 #define CONFIG_PREBOOT "usb start"
 119 #endif /* CONFIG_USB_KEYBOARD */
 120
 121 #endif /* CONFIG_MUSB_HCD */
 122
 123 #ifdef CONFIG_MUSB_UDC
 124 /* USB device configuration */
 125 #define CONFIG_USB_DEVICE               1
 126 #define CONFIG_USB_TTY                  1
 127 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
 128 /* Change these to suit your needs */
 129 #define CONFIG_USBD_VENDORID            0x0451
 130 #define CONFIG_USBD_PRODUCTID           0x5678
 131 #define CONFIG_USBD_MANUFACTURER        "Texas Instruments"
 132 #define CONFIG_USBD_PRODUCT_NAME        "AM3517CRANE"
 133 #endif /* CONFIG_MUSB_UDC */
 134
 135 #endif /* CONFIG_USB_AM35X */
 136
 137 /* commands to include */
 138 #include <config_cmd_default.h>
 139
 140 #define CONFIG_CMD_EXT2         /* EXT2 Support                 */
 141 #define CONFIG_CMD_FAT          /* FAT support                  */
 142 #define CONFIG_CMD_JFFS2        /* JFFS2 Support                */
 143
 144 #define CONFIG_CMD_I2C          /* I2C serial bus support       */
 145 #define CONFIG_CMD_MMC          /* MMC support                  */
 146 #define CONFIG_CMD_NAND         /* NAND support                 */
 147 #define CONFIG_CMD_DHCP
 148 #undef CONFIG_CMD_PING
 149
 150 #undef CONFIG_CMD_FLASH         /* flinfo, erase, protect       */
 151 #undef CONFIG_CMD_FPGA          /* FPGA configuration Support   */
 152 #undef CONFIG_CMD_IMI           /* iminfo                       */
 153 #undef CONFIG_CMD_IMLS          /* List all found images        */
 154
 155 #define CONFIG_SYS_NO_FLASH
 156 #define CONFIG_HARD_I2C                 1
 157 #define CONFIG_SYS_I2C_SPEED            100000
 158 #define CONFIG_SYS_I2C_SLAVE            1
 159 #define CONFIG_DRIVER_OMAP34XX_I2C      1
 160
 161 #undef CONFIG_CMD_NET
 162 #undef CONFIG_CMD_NFS
 163 /*
 164  * Board NAND Info.
 165  */
 166 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 167                                                         /* to access nand */
 168 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 169                                                         /* to access */
 170                                                         /* nand at CS0 */
 171
 172 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of */
 173                                                         /* NAND devices */
 174
 175 #define CONFIG_JFFS2_NAND
 176 /* nand device jffs2 lives on */
 177 #define CONFIG_JFFS2_DEV                "nand0"
 178 /* start of jffs2 partition */
 179 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 180 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* sz of jffs2 part */
 181
 182 /* Environment information */
 183 #define CONFIG_BOOTDELAY        10
 184
 185 #define CONFIG_BOOTFILE         "uImage"
 186
 187 #define CONFIG_EXTRA_ENV_SETTINGS \
 188         "loadaddr=0x82000000\0" \
 189         "console=ttyS2,115200n8\0" \
 190         "mmcdev=0\0" \
 191         "mmcargs=setenv bootargs console=${console} " \
 192                 "root=/dev/mmcblk0p2 rw " \
 193                 "rootfstype=ext3 rootwait\0" \
 194         "nandargs=setenv bootargs console=${console} " \
 195                 "root=/dev/mtdblock4 rw " \
 196                 "rootfstype=jffs2\0" \
 197         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 198         "bootscript=echo Running bootscript from mmc ...; " \
 199                 "source ${loadaddr}\0" \
 200         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 201         "mmcboot=echo Booting from mmc ...; " \
 202                 "run mmcargs; " \
 203                 "bootm ${loadaddr}\0" \
 204         "nandboot=echo Booting from nand ...; " \
 205                 "run nandargs; " \
 206                 "nand read ${loadaddr} 280000 400000; " \
 207                 "bootm ${loadaddr}\0" \
 208
 209 #define CONFIG_BOOTCOMMAND \
 210         "mmc dev ${mmcdev}; if mmc rescan; then " \
 211                 "if run loadbootscript; then " \
 212                         "run bootscript; " \
 213                 "else " \
 214                         "if run loaduimage; then " \
 215                                 "run mmcboot; " \
 216                         "else run nandboot; " \
 217                         "fi; " \
 218                 "fi; " \
 219         "else run nandboot; fi"
 220
 221 #define CONFIG_AUTO_COMPLETE    1
 222 /*
 223  * Miscellaneous configurable options
 224  */
 225 #define V_PROMPT                        "AM3517_CRANE # "
 226
 227 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 228 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 229 #define CONFIG_SYS_PROMPT               V_PROMPT
 230 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 231 /* Print Buffer Size */
 232 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 233                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 234 #define CONFIG_SYS_MAXARGS              32      /* max number of command */
 235                                                 /* args */
 236 /* Boot Argument Buffer Size */
 237 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 238 /* memtest works on */
 239 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)
 240 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 241                                         0x01F00000) /* 31MB */
 242
 243 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0) /* default load */
 244                                                                 /* address */
 245
 246 /*
 247  * AM3517 has 12 GP timers, they can be driven by the system clock
 248  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 249  * This rate is divided by a local divisor.
 250  */
 251 #define CONFIG_SYS_TIMERBASE            OMAP34XX_GPT2
 252 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 253 #define CONFIG_SYS_HZ                   1000
 254
 255 /*-----------------------------------------------------------------------
 256  * Physical Memory Map
 257  */
 258 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 259 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 260 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 261
 262 /*-----------------------------------------------------------------------
 263  * FLASH and environment organization
 264  */
 265
 266 /* **** PISMO SUPPORT *** */
 267
 268 /* Configure the PISMO */
 269 #define PISMO1_NAND_SIZE                GPMC_SIZE_128M
 270 #define PISMO1_ONEN_SIZE                GPMC_SIZE_128M
 271
 272 #define CONFIG_SYS_MAX_FLASH_SECT       520     /* max number of sectors */
 273                                                 /* on one chip */
 274 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of flash banks */
 275 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 276
 277 #define CONFIG_SYS_FLASH_BASE           PISMO1_NAND_BASE
 278
 279 /* Monitor at start of flash */
 280 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 281
 282 #define CONFIG_NAND_OMAP_GPMC
 283 #define GPMC_NAND_ECC_LP_x16_LAYOUT     1
 284 #define CONFIG_ENV_IS_IN_NAND           1
 285 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 286
 287 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB sector */
 288 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 289 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 290
 291 /*-----------------------------------------------------------------------
 292  * CFI FLASH driver setup
 293  */
 294 /* timeout values are in ticks */
 295 #define CONFIG_SYS_FLASH_ERASE_TOUT     (100 * CONFIG_SYS_HZ)
 296 #define CONFIG_SYS_FLASH_WRITE_TOUT     (100 * CONFIG_SYS_HZ)
 297
 298 /* Flash banks JFFS2 should use */
 299 #define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 300                                         CONFIG_SYS_MAX_NAND_DEVICE)
 301 #define CONFIG_SYS_JFFS2_MEM_NAND
 302 /* use flash_info[2] */
 303 #define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 304 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 305
 306 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 307 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 308 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 309 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 310                                          CONFIG_SYS_INIT_RAM_SIZE - \
 311                                          GENERATED_GBL_DATA_SIZE)
 312
 313 /* Defines for SPL */
 314 #define CONFIG_SPL
 315 #define CONFIG_SPL_FRAMEWORK
 316 #define CONFIG_SPL_BOARD_INIT
 317 #define CONFIG_SPL_NAND_SIMPLE
 318 #define CONFIG_SPL_TEXT_BASE            0x40200800
 319 #define CONFIG_SPL_MAX_SIZE             (54 * 1024)     /* 8 KB for stack */
 320 #define CONFIG_SPL_STACK                LOW_LEVEL_SRAM_STACK
 321
 322 #define CONFIG_SPL_BSS_START_ADDR       0x80000000
 323 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 324
 325 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 326 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
 327 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
 328 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
 329
 330 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 331 #define CONFIG_SPL_LIBDISK_SUPPORT
 332 #define CONFIG_SPL_I2C_SUPPORT
 333 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 334 #define CONFIG_SPL_MMC_SUPPORT
 335 #define CONFIG_SPL_FAT_SUPPORT
 336 #define CONFIG_SPL_SERIAL_SUPPORT
 337 #define CONFIG_SPL_NAND_SUPPORT
 338 #define CONFIG_SPL_NAND_BASE
 339 #define CONFIG_SPL_NAND_DRIVERS
 340 #define CONFIG_SPL_NAND_ECC
 341 #define CONFIG_SPL_POWER_SUPPORT
 342 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
 343
 344 /* NAND boot config */
 345 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 346 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 347 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 348 #define CONFIG_SYS_NAND_OOBSIZE         64
 349 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 350 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 351 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
 352                                                 10, 11, 12, 13}
 353 #define CONFIG_SYS_NAND_ECCSIZE         512
 354 #define CONFIG_SYS_NAND_ECCBYTES        3
 355 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 356 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 357
 358 /*
 359  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 360  * 64 bytes before this address should be set aside for u-boot.img's
 361  * header. That is 0x800FFFC0--0x80100000 should not be used for any
 362  * other needs.
 363  */
 364 #define CONFIG_SYS_TEXT_BASE            0x80100000
 365 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 366 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 367
 368 #endif /* __CONFIG_H */