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1 /*
2 * am3517_evm.h - Default configuration for AM3517 EVM board.
3 *
4 * Author: Vaibhav Hiremath <hvaibhav@ti.com>
5 *
6 * Based on omap3_evm_config.h
7 *
8 * Copyright (C) 2010 Texas Instruments Incorporated
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #ifndef __CONFIG_H
26 #define __CONFIG_H
27
28 /*
29 * High Level Configuration Options
30 */
31 #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
32 #define CONFIG_OMAP 1 /* in a TI OMAP core */
33 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
34 #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */
35
36 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
37
38 #include <asm/arch/cpu.h> /* get chip and board defs */
39 #include <asm/arch/omap3.h>
40
41 /*
42 * Display CPU and Board information
43 */
44 #define CONFIG_DISPLAY_CPUINFO 1
45 #define CONFIG_DISPLAY_BOARDINFO 1
46
47 /* Clock Defines */
48 #define V_OSCK 26000000 /* Clock output from T2 */
49 #define V_SCLK (V_OSCK >> 1)
50
51 #undef CONFIG_USE_IRQ /* no support for IRQs */
52 #define CONFIG_MISC_INIT_R
53
54 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
55 #define CONFIG_SETUP_MEMORY_TAGS 1
56 #define CONFIG_INITRD_TAG 1
57 #define CONFIG_REVISION_TAG 1
58
59 /*
60 * Size of malloc() pool
61 */
62 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
63 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
64 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
65 /* initial data */
66 /*
67 * DDR related
68 */
69 #define CONFIG_OMAP3_MICRON_DDR 1 /* Micron DDR */
70 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
71
72 /*
73 * Hardware drivers
74 */
75
76 /*
77 * NS16550 Configuration
78 */
79 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
80
81 #define CONFIG_SYS_NS16550
82 #define CONFIG_SYS_NS16550_SERIAL
83 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
84 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
85
86 /*
87 * select serial console configuration
88 */
89 #define CONFIG_CONS_INDEX 3
90 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
91 #define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */
92
93 /* allow to overwrite serial and ethaddr */
94 #define CONFIG_ENV_OVERWRITE
95 #define CONFIG_BAUDRATE 115200
96 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
97 115200}
98 #define CONFIG_MMC 1
99 #define CONFIG_OMAP3_MMC 1
100 #define CONFIG_DOS_PARTITION 1
101
102 /* commands to include */
103 #include <config_cmd_default.h>
104
105 #define CONFIG_CMD_EXT2 /* EXT2 Support */
106 #define CONFIG_CMD_FAT /* FAT support */
107 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
108
109 #define CONFIG_CMD_I2C /* I2C serial bus support */
110 #define CONFIG_CMD_MMC /* MMC support */
111 #define CONFIG_CMD_NAND /* NAND support */
112 #define CONFIG_CMD_DHCP
113 #define CONFIG_CMD_PING
114
115 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
116 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
117 #undef CONFIG_CMD_IMI /* iminfo */
118 #undef CONFIG_CMD_IMLS /* List all found images */
119
120 #define CONFIG_SYS_NO_FLASH
121 #define CONFIG_HARD_I2C 1
122 #define CONFIG_SYS_I2C_SPEED 100000
123 #define CONFIG_SYS_I2C_SLAVE 1
124 #define CONFIG_SYS_I2C_BUS 0
125 #define CONFIG_SYS_I2C_BUS_SELECT 1
126 #define CONFIG_DRIVER_OMAP34XX_I2C 1
127
128 #undef CONFIG_CMD_NET
129 /*
130 * Board NAND Info.
131 */
132 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
133 /* to access nand */
134 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
135 /* to access */
136 /* nand at CS0 */
137
138 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
139 /* NAND devices */
140 #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
141
142 #define CONFIG_JFFS2_NAND
143 /* nand device jffs2 lives on */
144 #define CONFIG_JFFS2_DEV "nand0"
145 /* start of jffs2 partition */
146 #define CONFIG_JFFS2_PART_OFFSET 0x680000
147 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
148
149 /* Environment information */
150 #define CONFIG_BOOTDELAY 10
151
152 #define CONFIG_BOOTFILE uImage
153
154 #define CONFIG_EXTRA_ENV_SETTINGS \
155 "loadaddr=0x82000000\0" \
156 "console=ttyS2,115200n8\0" \
157 "mmcargs=setenv bootargs console=${console} " \
158 "root=/dev/mmcblk0p2 rw " \
159 "rootfstype=ext3 rootwait\0" \
160 "nandargs=setenv bootargs console=${console} " \
161 "root=/dev/mtdblock4 rw " \
162 "rootfstype=jffs2\0" \
163 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
164 "bootscript=echo Running bootscript from mmc ...; " \
165 "source ${loadaddr}\0" \
166 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
167 "mmcboot=echo Booting from mmc ...; " \
168 "run mmcargs; " \
169 "bootm ${loadaddr}\0" \
170 "nandboot=echo Booting from nand ...; " \
171 "run nandargs; " \
172 "nand read ${loadaddr} 280000 400000; " \
173 "bootm ${loadaddr}\0" \
174
175 #define CONFIG_BOOTCOMMAND \
176 "if mmc init; then " \
177 "if run loadbootscript; then " \
178 "run bootscript; " \
179 "else " \
180 "if run loaduimage; then " \
181 "run mmcboot; " \
182 "else run nandboot; " \
183 "fi; " \
184 "fi; " \
185 "else run nandboot; fi"
186
187 #define CONFIG_AUTO_COMPLETE 1
188 /*
189 * Miscellaneous configurable options
190 */
191 #define V_PROMPT "AM3517_EVM # "
192
193 #define CONFIG_SYS_LONGHELP /* undef to save memory */
194 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
195 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
196 #define CONFIG_SYS_PROMPT V_PROMPT
197 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
198 /* Print Buffer Size */
199 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
200 sizeof(CONFIG_SYS_PROMPT) + 16)
201 #define CONFIG_SYS_MAXARGS 32 /* max number of command */
202 /* args */
203 /* Boot Argument Buffer Size */
204 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
205 /* memtest works on */
206 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
207 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
208 0x01F00000) /* 31MB */
209
210 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
211 /* address */
212
213 /*
214 * AM3517 has 12 GP timers, they can be driven by the system clock
215 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
216 * This rate is divided by a local divisor.
217 */
218 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
219 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
220 #define CONFIG_SYS_HZ 1000
221
222 /*-----------------------------------------------------------------------
223 * Stack sizes
224 *
225 * The stack sizes are set up in start.S using the settings below
226 */
227 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
228 #ifdef CONFIG_USE_IRQ
229 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
230 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
231 #endif
232
233 /*-----------------------------------------------------------------------
234 * Physical Memory Map
235 */
236 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
237 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
238 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
239 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
240
241 /* SDRAM Bank Allocation method */
242 #define SDRC_R_B_C 1
243
244 /*-----------------------------------------------------------------------
245 * FLASH and environment organization
246 */
247
248 /* **** PISMO SUPPORT *** */
249
250 /* Configure the PISMO */
251 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
252 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
253
254 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
255 /* on one chip */
256 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
257 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
258
259 #define CONFIG_SYS_FLASH_BASE boot_flash_base
260
261 /* Monitor at start of flash */
262 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
263
264 #define CONFIG_NAND_OMAP_GPMC
265 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
266 #define CONFIG_ENV_IS_IN_NAND 1
267 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
268
269 #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
270 #define CONFIG_ENV_OFFSET boot_flash_off
271 #define CONFIG_ENV_ADDR boot_flash_env_addr
272
273 /*-----------------------------------------------------------------------
274 * CFI FLASH driver setup
275 */
276 /* timeout values are in ticks */
277 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
278 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
279
280 /* Flash banks JFFS2 should use */
281 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
282 CONFIG_SYS_MAX_NAND_DEVICE)
283 #define CONFIG_SYS_JFFS2_MEM_NAND
284 /* use flash_info[2] */
285 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
286 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
287
288 #ifndef __ASSEMBLY__
289 extern unsigned int boot_flash_base;
290 extern volatile unsigned int boot_flash_env_addr;
291 extern unsigned int boot_flash_off;
292 extern unsigned int boot_flash_sec;
293 extern unsigned int boot_flash_type;
294 #endif
295
296 #endif /* __CONFIG_H */