include/configs/at91rm9200dk.h

   1 /*
   2  * Rick Bronson <rick@efn.org>
   3  *
   4  * Configuration settings for the AT91RM9200DK board.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 #define CONFIG_AT91_LEGACY
  29
  30 /* ARM asynchronous clock */
  31 #define AT91C_MAIN_CLOCK        179712000       /* from 18.432 MHz crystal (18432000 / 4 * 39) */
  32 #define AT91C_MASTER_CLOCK      59904000        /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
  33 /* #define AT91C_MASTER_CLOCK   44928000 */     /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
  34
  35 #define AT91_SLOW_CLOCK         32768   /* slow clock */
  36
  37 #define CONFIG_ARM920T          1       /* This is an ARM920T Core      */
  38 #define CONFIG_AT91RM9200       1       /* It's an Atmel AT91RM9200 SoC */
  39 #define CONFIG_AT91RM9200DK     1       /* on an AT91RM9200DK Board     */
  40 #undef  CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff  */
  41 #define USE_920T_MMU            1
  42
  43 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs      */
  44 #define CONFIG_SETUP_MEMORY_TAGS 1
  45 #define CONFIG_INITRD_TAG       1
  46
  47 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  48 #define CONFIG_SYS_USE_MAIN_OSCILLATOR          1
  49 /* flash */
  50 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
  51 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
  52
  53 /* clocks */
  54 #define CONFIG_SYS_PLLAR_VAL    0x20263E04 /* 179.712000 MHz for PCK */
  55 #define CONFIG_SYS_PLLBR_VAL    0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
  56 #define CONFIG_SYS_MCKR_VAL     0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
  57
  58 /* sdram */
  59 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
  60 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
  61 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
  62 #define CONFIG_SYS_EBI_CSA_VAL  0x00000002 /* CS1=CONFIG_SYS_SDRAM */
  63 #define CONFIG_SYS_SDRC_CR_VAL  0x2188c155 /* set up the CONFIG_SYS_SDRAM */
  64 #define CONFIG_SYS_SDRAM        0x20000000 /* address of the CONFIG_SYS_SDRAM */
  65 #define CONFIG_SYS_SDRAM1       0x20000080 /* address of the CONFIG_SYS_SDRAM */
  66 #define CONFIG_SYS_SDRAM_VAL    0x00000000 /* value written to CONFIG_SYS_SDRAM */
  67 #define CONFIG_SYS_SDRC_MR_VAL  0x00000002 /* Precharge All */
  68 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
  69 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
  70 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
  71 #define CONFIG_SYS_SDRC_TR_VAL  0x000002E0 /* Write refresh rate */
  72 #endif  /* CONFIG_SKIP_LOWLEVEL_INIT */
  73 /*
  74  * Size of malloc() pool
  75  */
  76 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + 128*1024)
  77
  78 #define CONFIG_BAUDRATE 115200
  79
  80 /*
  81  * Hardware drivers
  82  */
  83
  84 /* define one of these to choose the DBGU, USART0  or USART1 as console */
  85 #define CONFIG_AT91RM9200_USART
  86 #define CONFIG_DBGU
  87 #undef CONFIG_USART0
  88 #undef CONFIG_USART1
  89
  90 #undef  CONFIG_HWFLOW                   /* don't include RTS/CTS flow control support   */
  91
  92 #undef  CONFIG_MODEM_SUPPORT            /* disable modem initialization stuff */
  93
  94 #define CONFIG_BOOTDELAY      3
  95 /* #define CONFIG_ENV_OVERWRITE 1 */
  96
  97
  98 /*
  99  * BOOTP options
 100  */
 101 #define CONFIG_BOOTP_BOOTFILESIZE
 102 #define CONFIG_BOOTP_BOOTPATH
 103 #define CONFIG_BOOTP_GATEWAY
 104 #define CONFIG_BOOTP_HOSTNAME
 105
 106
 107 /*
 108  * Command line configuration.
 109  */
 110 #include <config_cmd_default.h>
 111
 112 #define CONFIG_CMD_DHCP
 113 #define CONFIG_CMD_MII
 114
 115 #include <asm/arch/AT91RM9200.h>        /* needed for port definitions */
 116
 117 #define CONFIG_NR_DRAM_BANKS 1
 118 #define PHYS_SDRAM 0x20000000
 119 #define PHYS_SDRAM_SIZE 0x2000000  /* 32 megs */
 120
 121 #define CONFIG_SYS_MEMTEST_START                PHYS_SDRAM
 122 #define CONFIG_SYS_MEMTEST_END                  CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
 123
 124 #define CONFIG_NET_MULTI                1
 125 #ifdef CONFIG_NET_MULTI
 126 #define CONFIG_DRIVER_AT91EMAC          1
 127 #define CONFIG_SYS_RX_ETH_BUFFER        8
 128 #else
 129 #define CONFIG_DRIVER_ETHER             1
 130 #endif
 131
 132 #define CONFIG_NET_RETRY_COUNT          20
 133 #define CONFIG_AT91C_USE_RMII
 134
 135 /* AC Characteristics */
 136 /* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
 137 #define DATAFLASH_TCSS  (0xC << 16)
 138 #define DATAFLASH_TCHS  (0x1 << 24)
 139
 140 #define CONFIG_HAS_DATAFLASH            1
 141 #define CONFIG_SYS_SPI_WRITE_TOUT               (5*CONFIG_SYS_HZ)
 142 #define CONFIG_SYS_MAX_DATAFLASH_BANKS          2
 143 #define CONFIG_SYS_MAX_DATAFLASH_PAGES          16384
 144 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000      /* Logical adress for CS0 */
 145 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3     0xD0000000      /* Logical adress for CS3 */
 146
 147 #define PHYS_FLASH_1                    0x10000000
 148 #define PHYS_FLASH_SIZE                 0x200000  /* 2 megs main flash */
 149 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
 150 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 151 #define CONFIG_SYS_MAX_FLASH_SECT               256
 152 #define CONFIG_SYS_FLASH_ERASE_TOUT             (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 153 #define CONFIG_SYS_FLASH_WRITE_TOUT             (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 154
 155 #undef  CONFIG_ENV_IS_IN_DATAFLASH
 156
 157 #ifdef CONFIG_ENV_IS_IN_DATAFLASH
 158 #define CONFIG_ENV_OFFSET                       0x20000
 159 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 160 #define CONFIG_ENV_SIZE                 0x2000  /* 0x8000 */
 161 #else
 162 #define CONFIG_ENV_IS_IN_FLASH          1
 163 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 164 #define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0xe000)  /* between boot.bin and u-boot.bin.gz */
 165 #define CONFIG_ENV_SIZE                 0x2000  /* 0x8000 */
 166 #else
 167 #define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0x60000)  /* after u-boot.bin */
 168 #define CONFIG_ENV_SIZE                 0x10000 /* sectors are 64K here */
 169 #endif  /* CONFIG_SKIP_LOWLEVEL_INIT */
 170 #endif  /* CONFIG_ENV_IS_IN_DATAFLASH */
 171
 172
 173 #define CONFIG_SYS_LOAD_ADDR            0x21000000  /* default load address */
 174
 175 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 176 #define CONFIG_SYS_BOOT_SIZE            0x6000 /* 24 KBytes */
 177 #define CONFIG_SYS_U_BOOT_BASE          (PHYS_FLASH_1 + 0x10000)
 178 #define CONFIG_SYS_U_BOOT_SIZE          0x10000 /* 64 KBytes */
 179 #else
 180 #define CONFIG_SYS_BOOT_SIZE            0x00 /* 0 KBytes */
 181 #define CONFIG_SYS_U_BOOT_BASE          PHYS_FLASH_1
 182 #define CONFIG_SYS_U_BOOT_SIZE          0x60000 /* 384 KBytes */
 183 #endif  /* CONFIG_SKIP_LOWLEVEL_INIT */
 184
 185 #define CONFIG_SYS_BAUDRATE_TABLE       { 115200, 19200, 38400, 57600, 9600 }
 186
 187 #define CONFIG_SYS_PROMPT               "U-Boot> "      /* Monitor Command Prompt */
 188 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size */
 189 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 190 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 191
 192 #define CONFIG_SYS_HZ 1000
 193 #define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2        /* AT91C_TC0_CMR is implicitly set to */
 194                                                 /* AT91C_TC_TIMER_DIV1_CLOCK */
 195
 196 #define CONFIG_STACKSIZE        (32*1024)       /* regular stack */
 197
 198 #ifdef CONFIG_USE_IRQ
 199 #error CONFIG_USE_IRQ not supported
 200 #endif
 201
 202 #endif