include/configs/at91rm9200ek.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
   4  *
   5  * based on previous work by
   6  *
   7  * Ulf Samuelsson <ulf@atmel.com>
   8  * Rick Bronson <rick@efn.org>
   9  *
  10  * Configuration settings for the AT91RM9200EK board.
  11  */
  12
  13 #ifndef __AT91RM9200EK_CONFIG_H__
  14 #define __AT91RM9200EK_CONFIG_H__
  15
  16 #include <linux/sizes.h>
  17
  18 /*
  19  * set some initial configurations depending on configure target
  20  *
  21  * at91rm9200ek_config     -> boot from 0x0 in NOR Flash at CS0
  22  * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
  23  *                            initialisation was done by some preloader
  24  */
  25 #ifdef CONFIG_RAMBOOT
  26 #define CONFIG_SKIP_LOWLEVEL_INIT
  27 #endif
  28
  29 /*
  30  * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
  31  * AT91C_MAIN_CLOCK is the frequency of PLLA output
  32  * AT91C_MASTER_CLOCK is the peripherial clock
  33  * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
  34  *  set in arch/arm/cpu/arm920t/at91/timer.c)
  35  * CONFIG_SYS_HZ is the tick rate for timer tc0
  36  */
  37 #define AT91C_XTAL_CLOCK                18432000
  38 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
  39 #define AT91C_MAIN_CLOCK                ((AT91C_XTAL_CLOCK / 4) * 39)
  40 #define AT91C_MASTER_CLOCK              (AT91C_MAIN_CLOCK / 3 )
  41 #define CONFIG_SYS_HZ_CLOCK             (AT91C_MASTER_CLOCK / 2)
  42
  43 /* CPU configuration */
  44 #define CONFIG_AT91RM9200
  45 #define CONFIG_AT91RM9200EK
  46 #define USE_920T_MMU
  47
  48 #include <asm/hardware.h>       /* needed for port definitions */
  49
  50 #define CONFIG_CMDLINE_TAG
  51 #define CONFIG_SETUP_MEMORY_TAGS
  52 #define CONFIG_INITRD_TAG
  53
  54 /*
  55  * Memory Configuration
  56  */
  57 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  58 #define CONFIG_SYS_SDRAM_SIZE           SZ_32M
  59
  60 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  61 #define CONFIG_SYS_MEMTEST_END          \
  62                 (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
  63
  64 /*
  65  * LowLevel Init
  66  */
  67 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  68 #define CONFIG_SYS_USE_MAIN_OSCILLATOR
  69 /* flash */
  70 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
  71 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
  72
  73 /* clocks */
  74 #define CONFIG_SYS_PLLAR_VAL    0x20263E04 /* 179.712000 MHz for PCK */
  75 #define CONFIG_SYS_PLLBR_VAL    0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
  76 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
  77 #define CONFIG_SYS_MCKR_VAL     0x00000202
  78
  79 /* sdram */
  80 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
  81 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
  82 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
  83 #define CONFIG_SYS_EBI_CSA_VAL  0x00000002 /* CS1=CONFIG_SYS_SDRAM */
  84 #define CONFIG_SYS_SDRC_CR_VAL  0x2188c155 /* set up the CONFIG_SYS_SDRAM */
  85 #define CONFIG_SYS_SDRAM        CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
  86 #define CONFIG_SYS_SDRAM1       (CONFIG_SYS_SDRAM_BASE+0x80)
  87 #define CONFIG_SYS_SDRAM_VAL    0x00000000 /* value written to CONFIG_SYS_SDRAM */
  88 #define CONFIG_SYS_SDRC_MR_VAL  0x00000002 /* Precharge All */
  89 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
  90 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
  91 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
  92 #define CONFIG_SYS_SDRC_TR_VAL  0x000002E0 /* Write refresh rate */
  93 #endif  /* CONFIG_SKIP_LOWLEVEL_INIT */
  94
  95 /*
  96  * Hardware drivers
  97  */
  98 /*
  99  * Choose a USART for serial console
 100  * CONFIG_DBGU is DBGU unit on J10
 101  * CONFIG_USART1 is USART1 on J14
 102  */
 103 #define CONFIG_ATMEL_USART
 104 #define CONFIG_USART_BASE       ATMEL_BASE_DBGU
 105 #define CONFIG_USART_ID         0/* ignored in arm */
 106
 107 /*
 108  * Command line configuration.
 109  */
 110
 111 /*
 112  * Network Driver Setting
 113  */
 114 #define CONFIG_DRIVER_AT91EMAC
 115 #define CONFIG_SYS_RX_ETH_BUFFER        16
 116 #define CONFIG_RMII
 117
 118 /*
 119  * NOR Flash
 120  */
 121 #define CONFIG_SYS_FLASH_BASE           0x10000000
 122 #define PHYS_FLASH_1                    CONFIG_SYS_FLASH_BASE
 123 #define PHYS_FLASH_SIZE                 SZ_8M
 124 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 125 #define CONFIG_SYS_MAX_FLASH_SECT       256
 126
 127 /*
 128  * USB Config
 129  */
 130 #define CONFIG_USB_ATMEL                        1
 131 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 132 #define CONFIG_USB_OHCI_NEW                     1
 133
 134 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
 135 #define CONFIG_SYS_USB_OHCI_REGS_BASE           ATMEL_USB_HOST_BASE
 136 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91rm9200"
 137 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 138
 139 /*
 140  * Environment Settings
 141  */
 142
 143 /*
 144  * after u-boot.bin
 145  */
 146
 147 /* The following #defines are needed to get flash environment right */
 148 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 149 #define CONFIG_SYS_MONITOR_LEN          SZ_256K
 150
 151 /*
 152  * Boot option
 153  */
 154
 155 /* default load address */
 156 #define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_SDRAM_BASE + SZ_16M
 157 #define CONFIG_ENV_OVERWRITE
 158
 159 /*
 160  * Shell Settings
 161  */
 162
 163 /*
 164  * Size of malloc() pool
 165  */
 166 #define CONFIG_SYS_MALLOC_LEN           ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
 167                                              SZ_4K)
 168
 169 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + SZ_4K \
 170                                         - GENERATED_GBL_DATA_SIZE)
 171
 172 #endif /* __AT91RM9200EK_CONFIG_H__ */