include/configs/atc.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU               */
  37 #define CONFIG_ATC              1       /* ...on a ATC board    */
  38
  39 /*
  40  * select serial console configuration
  41  *
  42  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  43  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  44  * for SCC).
  45  *
  46  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  47  * defined elsewhere (for example, on the cogent platform, there are serial
  48  * ports on the motherboard which are used for the serial console - see
  49  * cogent/cma101/serial.[ch]).
  50  */
  51 #define  CONFIG_CONS_ON_SMC             /* define if console on SMC */
  52 #undef CONFIG_CONS_ON_SCC               /* define if console on SCC */
  53 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  54 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
  55
  56 #define CONFIG_BAUDRATE         115200
  57
  58 /*
  59  * select ethernet configuration
  60  *
  61  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  62  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  63  * for FCC)
  64  *
  65  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  66  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  67  * from CONFIG_COMMANDS to remove support for networking.
  68  *
  69  */
  70 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  71 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  72 #define CONFIG_ETHER_ON_FCC
  73
  74 #define CONFIG_NET_MULTI
  75 #define CONFIG_ETHER_ON_FCC2
  76
  77 /*
  78  * - Rx-CLK is CLK13
  79  * - Tx-CLK is CLK14
  80  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  81  * - Enable Full Duplex in FSMR
  82  */
  83 # define CFG_CMXFCR_MASK2       (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  84 # define CFG_CMXFCR_VALUE2      (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
  85 # define CFG_CPMFCR_RAMTYPE     0
  86 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
  87
  88 #define CONFIG_ETHER_ON_FCC3
  89
  90 /*
  91  * - Rx-CLK is CLK15
  92  * - Tx-CLK is CLK16
  93  * - RAM for BD/Buffers is on the local Bus (see 28-13)
  94  * - Enable Half Duplex in FSMR
  95  */
  96 # define CFG_CMXFCR_MASK3       (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
  97 # define CFG_CMXFCR_VALUE3      (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
  98
  99 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 100 #define CONFIG_8260_CLKIN       64000000        /* in Hz */
 101
 102 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 103
 104 #undef  CONFIG_CLOCKS_IN_MHZ            /* clocks passsed to Linux in Hz */
 105
 106 #define CONFIG_PREBOOT                                                  \
 107         "echo;"                                                         \
 108         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\
 109         "echo"
 110
 111 #undef  CONFIG_BOOTARGS
 112 #define CONFIG_BOOTCOMMAND                                              \
 113         "bootp;"                                                        \
 114         "setenv bootargs root=/dev/nfs rw "                             \
 115         "nfsroot=$(serverip):$(rootpath) "                              \
 116         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\
 117         "bootm"
 118
 119 /*-----------------------------------------------------------------------
 120  * Miscellaneous configuration options
 121  */
 122
 123 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 124 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
 125
 126 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
 127
 128 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL | \
 129                                  CFG_CMD_EEPROM | \
 130                                  CFG_CMD_PCI | \
 131                                  CFG_CMD_PCMCIA | \
 132                                  CFG_CMD_IDE)
 133 #define CONFIG_DOS_PARTITION
 134
 135 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 136 #include <cmd_confdefs.h>
 137
 138 /*
 139  * Miscellaneous configurable options
 140  */
 141 #define CFG_LONGHELP                    /* undef to save memory         */
 142 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 143 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 144 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 145 #else
 146 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 147 #endif
 148 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 149 #define CFG_MAXARGS     16              /* max number of command args   */
 150 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 151
 152 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 153 #define CFG_MEMTEST_END 0x0C00000       /* 4 ... 12 MB in DRAM  */
 154
 155 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 156
 157 #define CFG_PIO_MODE            0       /* IDE interface in PIO Mode 0  */
 158
 159 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 160
 161 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 162
 163 #define CFG_RESET_ADDRESS 0xFFF00100    /* "bad" address                */
 164
 165 #define CFG_ALLOC_DPRAM
 166
 167 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 168
 169 #define CONFIG_SPI
 170
 171 /*
 172  * For booting Linux, the board info and command line data
 173  * have to be in the first 8 MB of memory, since this is
 174  * the maximum mapped by the Linux kernel during initialization.
 175  */
 176 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 177
 178 /*-----------------------------------------------------------------------
 179  * Flash configuration
 180  */
 181
 182 #define CFG_BOOTROM_BASE        0xFF800000
 183 #define CFG_BOOTROM_SIZE        0x00080000
 184 #define CFG_FLASH_BASE          0xFF000000
 185 #define CFG_FLASH_SIZE          0x00800000
 186
 187 /*-----------------------------------------------------------------------
 188  * FLASH organization
 189  */
 190 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 191 #define CFG_MAX_FLASH_SECT      128     /* max num of sects on one chip */
 192
 193 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 194 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 195
 196 #define CONFIG_FLASH_16BIT
 197
 198 /*-----------------------------------------------------------------------
 199  * Hard Reset Configuration Words
 200  *
 201  * if you change bits in the HRCW, you must also change the CFG_*
 202  * defines for the various registers affected by the HRCW e.g. changing
 203  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 204  */
 205 #define CFG_HRCW_MASTER         (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 206                                  HRCW_BPS10 | HRCW_DPPC10 |\
 207                                  HRCW_APPC10)
 208
 209 /* no slaves so just fill with zeros */
 210 #define CFG_HRCW_SLAVE1         0
 211 #define CFG_HRCW_SLAVE2         0
 212 #define CFG_HRCW_SLAVE3         0
 213 #define CFG_HRCW_SLAVE4         0
 214 #define CFG_HRCW_SLAVE5         0
 215 #define CFG_HRCW_SLAVE6         0
 216 #define CFG_HRCW_SLAVE7         0
 217
 218 /*-----------------------------------------------------------------------
 219  * Internal Memory Mapped Register
 220  */
 221 #define CFG_IMMR                0xF0000000
 222
 223 /*-----------------------------------------------------------------------
 224  * Definitions for initial stack pointer and data area (in DPRAM)
 225  */
 226 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 227 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 228 #define CFG_GBL_DATA_SIZE       128 /* size in bytes reserved for initial data*/
 229 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 230 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 231
 232 /*-----------------------------------------------------------------------
 233  * Start addresses for the final memory configuration
 234  * (Set up by the startup code)
 235  * Please note that CFG_SDRAM_BASE _must_ start at 0
 236  *
 237  * 60x SDRAM is mapped at CFG_SDRAM_BASE.
 238  */
 239 #define CFG_SDRAM_BASE          0x00000000
 240 #define CFG_SDRAM_MAX_SIZE      0x08000000      /* max. 128 MB          */
 241 #define CFG_MONITOR_BASE        TEXT_BASE
 242 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor */
 243 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()*/
 244
 245 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 246 # define CFG_RAMBOOT
 247 #endif
 248
 249 #define CONFIG_PCI
 250 #define CONFIG_PCI_PNP
 251 #define CFG_PCI_MSTR_IO_BUS     0x00000000      /* PCI base   */
 252
 253 #if 1
 254 /* environment is in Flash */
 255 #define CFG_ENV_IS_IN_FLASH     1
 256 # define CFG_ENV_ADDR           (CFG_FLASH_BASE+0x30000)
 257 # define CFG_ENV_SIZE           0x10000
 258 # define CFG_ENV_SECT_SIZE      0x10000
 259 #else
 260 #define CFG_ENV_IS_IN_EEPROM    1
 261 #define CFG_ENV_OFFSET          0
 262 #define CFG_ENV_SIZE            2048
 263 #define CFG_EEPROM_PAGE_WRITE_BITS      4       /* 16-byte page size    */
 264 #endif
 265 /*
 266  * Internal Definitions
 267  *
 268  * Boot Flags
 269  */
 270 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH*/
 271 #define BOOTFLAG_WARM           0x02    /* Software reboot                 */
 272
 273
 274 /*-----------------------------------------------------------------------
 275  * Cache Configuration
 276  */
 277 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 278 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 279 # define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 280 #endif
 281
 282 /*-----------------------------------------------------------------------
 283  * HIDx - Hardware Implementation-dependent Registers                    2-11
 284  *-----------------------------------------------------------------------
 285  * HID0 also contains cache control - initially enable both caches and
 286  * invalidate contents, then the final state leaves only the instruction
 287  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 288  * but Soft reset does not.
 289  *
 290  * HID1 has only read-only information - nothing to set.
 291  */
 292 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
 293                          HID0_DCI|HID0_IFEM|HID0_ABE)
 294 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 295 #define CFG_HID2        0
 296
 297 /*-----------------------------------------------------------------------
 298  * RMR - Reset Mode Register                                     5-5
 299  *-----------------------------------------------------------------------
 300  * turn on Checkstop Reset Enable
 301  */
 302 #define CFG_RMR         RMR_CSRE
 303
 304 /*-----------------------------------------------------------------------
 305  * BCR - Bus Configuration                                       4-25
 306  *-----------------------------------------------------------------------
 307  */
 308 #define BCR_APD01       0x10000000
 309 #define CFG_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 310
 311 /*-----------------------------------------------------------------------
 312  * SIUMCR - SIU Module Configuration                             4-31
 313  *-----------------------------------------------------------------------
 314  */
 315 #define CFG_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC10|SIUMCR_APPC10|\
 316                          SIUMCR_CS10PC00|SIUMCR_BCTLC10)
 317
 318 /*-----------------------------------------------------------------------
 319  * SYPCR - System Protection Control                             4-35
 320  * SYPCR can only be written once after reset!
 321  *-----------------------------------------------------------------------
 322  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 323  */
 324 #if defined(CONFIG_WATCHDOG)
 325 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 326                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 327 #else
 328 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 329                          SYPCR_SWRI|SYPCR_SWP)
 330 #endif /* CONFIG_WATCHDOG */
 331
 332 /*-----------------------------------------------------------------------
 333  * TMCNTSC - Time Counter Status and Control                     4-40
 334  *-----------------------------------------------------------------------
 335  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 336  * and enable Time Counter
 337  */
 338 #define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 339
 340 /*-----------------------------------------------------------------------
 341  * PISCR - Periodic Interrupt Status and Control                 4-42
 342  *-----------------------------------------------------------------------
 343  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 344  * Periodic timer
 345  */
 346 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 347
 348 /*-----------------------------------------------------------------------
 349  * SCCR - System Clock Control                                   9-8
 350  *-----------------------------------------------------------------------
 351  * Ensure DFBRG is Divide by 16
 352  */
 353 #define CFG_SCCR        SCCR_DFBRG01
 354
 355 /*-----------------------------------------------------------------------
 356  * RCCR - RISC Controller Configuration                         13-7
 357  *-----------------------------------------------------------------------
 358  */
 359 #define CFG_RCCR        0
 360
 361 #define CFG_MIN_AM_MASK 0xC0000000
 362 /*-----------------------------------------------------------------------
 363  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 364  *-----------------------------------------------------------------------
 365  */
 366 #define CFG_MPTPR       0x1F00
 367
 368 /*-----------------------------------------------------------------------
 369  * PSRT - Refresh Timer Register                                10-16
 370  *-----------------------------------------------------------------------
 371  */
 372 #define CFG_PSRT        0x0f
 373
 374 /*-----------------------------------------------------------------------
 375  * PSRT - SDRAM Mode Register                                   10-10
 376  *-----------------------------------------------------------------------
 377  */
 378
 379         /* SDRAM initialization values for 8-column chips
 380          */
 381 #define CFG_OR2_8COL    (CFG_MIN_AM_MASK                |\
 382                          ORxS_BPD_4                     |\
 383                          ORxS_ROWST_PBI1_A7             |\
 384                          ORxS_NUMR_12)
 385
 386 #define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
 387                          PSDMR_SDAM_A15_IS_A5           |\
 388                          PSDMR_BSMA_A15_A17             |\
 389                          PSDMR_SDA10_PBI1_A7            |\
 390                          PSDMR_RFRC_7_CLK               |\
 391                          PSDMR_PRETOACT_3W              |\
 392                          PSDMR_ACTTORW_2W               |\
 393                          PSDMR_LDOTOPRE_1C              |\
 394                          PSDMR_WRC_1C                   |\
 395                          PSDMR_CL_2)
 396
 397         /* SDRAM initialization values for 9-column chips
 398          */
 399 #define CFG_OR2_9COL    (CFG_MIN_AM_MASK                |\
 400                          ORxS_BPD_4                     |\
 401                          ORxS_ROWST_PBI1_A6             |\
 402                          ORxS_NUMR_12)
 403
 404 #define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
 405                          PSDMR_SDAM_A16_IS_A5           |\
 406                          PSDMR_BSMA_A15_A17             |\
 407                          PSDMR_SDA10_PBI1_A6            |\
 408                          PSDMR_RFRC_7_CLK               |\
 409                          PSDMR_PRETOACT_3W              |\
 410                          PSDMR_ACTTORW_2W               |\
 411                          PSDMR_LDOTOPRE_1C              |\
 412                          PSDMR_WRC_1C                   |\
 413                          PSDMR_CL_2)
 414
 415 /*
 416  * Init Memory Controller:
 417  *
 418  * Bank Bus     Machine PortSz  Device
 419  * ---- ---     ------- ------  ------
 420  *  0   60x     GPCM    8  bit  Boot ROM
 421  *  1   60x     GPCM    64 bit  FLASH
 422  *  2   60x     SDRAM   64 bit  SDRAM
 423  *
 424  */
 425
 426 #define CFG_MRS_OFFS    0x00000000
 427
 428 /* Bank 0 - FLASH
 429  */
 430 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
 431                          BRx_PS_16                      |\
 432                          BRx_MS_GPCM_P                  |\
 433                          BRx_V)
 434
 435 #define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
 436                          ORxG_CSNT                      |\
 437                          ORxG_ACS_DIV1                  |\
 438                          ORxG_SCY_3_CLK                 |\
 439                          ORxU_EHTR_8IDLE)
 440
 441
 442 /* Bank 2 - 60x bus SDRAM
 443  */
 444 #ifndef CFG_RAMBOOT
 445 #define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
 446                          BRx_PS_64                      |\
 447                          BRx_MS_SDRAM_P                 |\
 448                          BRx_V)
 449
 450 #define CFG_OR2_PRELIM   CFG_OR2_8COL
 451
 452 #define CFG_PSDMR        CFG_PSDMR_8COL
 453 #endif /* CFG_RAMBOOT */
 454
 455 /*-----------------------------------------------------------------------
 456  * PCMCIA stuff
 457  *-----------------------------------------------------------------------
 458  *
 459  */
 460 #define CONFIG_I82365
 461
 462 #define CFG_PCMCIA_MEM_ADDR     0x81000000
 463 #define CFG_PCMCIA_MEM_SIZE     0x1000
 464
 465 /*-----------------------------------------------------------------------
 466  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 467  *-----------------------------------------------------------------------
 468  */
 469
 470 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 471
 472 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 473 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 474 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 475
 476 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 477 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 478
 479 #define CFG_ATA_IDE0_OFFSET     0x0000
 480
 481 #define CFG_ATA_BASE_ADDR       0xa0000000
 482
 483 /* Offset for data I/O                  */
 484 #define CFG_ATA_DATA_OFFSET     0x100
 485
 486 /* Offset for normal register accesses  */
 487 #define CFG_ATA_REG_OFFSET      0x100
 488
 489 /* Offset for alternate registers       */
 490 #define CFG_ATA_ALT_OFFSET      0x108
 491
 492 #endif  /* __CONFIG_H */